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* [IR] Switch static const to an enum to silence MSVC linker warningsDavid Majnemer2015-07-102-4/+2
| | | | | | | Integral class statics are handled oddly in MSVC, we don't need them in this case, use an enum instead. llvm-svn: 241958
* MC: Remove MCSubtargetInfo() default constructorDuncan P. N. Exon Smith2015-07-1018-73/+51
| | | | | | | | | | | | | | | | | | | | | Force all creators of `MCSubtargetInfo` to immediately initialize it, merging the default constructor and the initializer into an initializing constructor. Besides cleaning up the code a little, this makes it clear that the initializer is never called again later. Out-of-tree backends need a trivial change: instead of calling: auto *X = new MCSubtargetInfo(); InitXYZMCSubtargetInfo(X, ...); return X; they should call: return createXYZMCSubtargetInfoImpl(...); There's no real functionality change here. llvm-svn: 241957
* MC: Remove MCSubtargetInfo::InitCPUSched()Duncan P. N. Exon Smith2015-07-104-13/+1
| | | | | | | | | | | | Remove all calls to `MCSubtargetInfo::InitCPUSched()` and merge its body into the only relevant caller, `MCSubtargetInfo::InitMCProcessorInfo()`. We were only calling the former after explicitly calling the latter with the same CPU; it's confusing to have both methods exposed. Besides a minor (surely unmeasurable) speedup in ARM and X86 from avoiding running the logic twice, no functionality change. llvm-svn: 241956
* [InstCombine] Actually combine AA metadata when replacing one load with anotherBjorn Steinbrink2015-07-102-6/+2
| | | | | | Fixes PR24083 llvm-svn: 241955
* AMDGPU: Use requested chain when lowering argumentsMatt Arsenault2015-07-101-1/+1
| | | | | | | No test since I'm not aware of any case where this will end up being a different chain. llvm-svn: 241954
* ARM: Use SpecificBumpPtrAllocator to fix leak introduced in r241920Matthias Braun2015-07-101-3/+3
| | | | llvm-svn: 241951
* [SEH] Push reloads of the SEH code past phi nodesReid Kleckner2015-07-102-6/+119
| | | | | | | | | | | This in turn would sometimes introduce new cleanupblocks that didn't previously exist. The uses were being introduced by SSA value demotion. We actually want to *promote* uses of EH pointers and selectors, so I added some spcecial casing to avoid demoting such instructions. This is getting overly complicated, but hopefully we'll come along and delete it in the new representation. llvm-svn: 241950
* Add <type_traits> for is_pod, fixing r241947Duncan P. N. Exon Smith2015-07-101-0/+1
| | | | llvm-svn: 241949
* DAGCombiner: Assume invariant load cannot alias a storeMatt Arsenault2015-07-102-0/+44
| | | | | | | | | | The motivation is to allow GatherAllAliases / FindBetterChain to not give up on dependent loads of a pointer from constant memory. This is important for AMDGPU, because most loads are pointers derived from a load of a kernel argument from constant memory. llvm-svn: 241948
* MC: Remove the copy of MCSchedModel in MCSubtargetInfoDuncan P. N. Exon Smith2015-07-105-30/+46
| | | | | | | | | | | `MCSchedModel` is large. Make `MCSchedModel::GetDefaultSchedModel()` return by-reference instead of by-value, so we can store a pointer in `MCSubtargetInfo::CPUSchedModel` instead of a copy. Note: since `MCSchedModel` is POD, this doesn't create a static constructor. llvm-svn: 241947
* [ShrinkWrap][PEI] Do not insert epilogue for unreachable blocks.Quentin Colombet2015-07-103-3/+86
| | | | | | | Although this is not incorrect to insert such code, it is useless and it hurts the binary size. llvm-svn: 241946
* [MC] Switch static const to an enum to silence MSVC linker warningsDavid Majnemer2015-07-102-5/+2
| | | | | | | Integral class statics are handled oddly in MSVC, we don't need them in this case, use an enum instead. llvm-svn: 241945
* Fix AArch64 prologue for empty frame with dynamic allocas.Evgeniy Stepanov2015-07-102-8/+54
| | | | | | | | Fixes PR23804: assertion failure in emitPrologue in the case of a function with an empty frame and a dynamic alloca that needs stack realignment. This is a typical case for AddressSanitizer. llvm-svn: 241943
* [TTI] BasicTTIImpl assumes no vector registersJingyue Wu2015-07-104-12/+9
| | | | | | | | | | | | | | | | | | | | | | | Summary: Following the discussion on r241884, it's more reasonable to assume that a target has no vector registers by default instead of letting every such target overrides getNumberOfRegisters. Therefore, this patch modifies BasicTTIImpl::getNumberOfRegisters to return 0 when Vector is true, and partially reverts r241884 which modifies NVPTXTTIImpl::getNumberOfRegisters. It also fixes a performance bug in LoopVectorizer. Even if a target has no vector registers, vectorization may still help ILP. So, we need both checks to be false before disabling loop vectorization all together. Reviewers: hfinkel Subscribers: llvm-commits, jholewinski Differential Revision: http://reviews.llvm.org/D11108 llvm-svn: 241942
* Fix `llvm-config` to emit the linker flag for the combined shared object ↵JF Bastien2015-07-104-2/+50
| | | | | | | | | | | | | | | | | built by autoconfig/make instead of the individual components. Summary: This fixes `llvm-config` instead of fixing the makefiles because, AIUI, LLVM's autoconfig/make build system is on the way out anyway. This change only affects builds that use autoconfig/make. Reviewers: jfb Subscribers: echristo, dschuff, llvm-commits Differential Revision: http://reviews.llvm.org/D10716 llvm-svn: 241938
* [Object][ELF] Handle the dynamic string table in files without a section table.Michael J. Spencer2015-07-102-6/+44
| | | | llvm-svn: 241937
* Fix enum BitcodeError to not define a zero-valued error code.Jan Wen Voung2015-07-101-1/+1
| | | | | | | | | | | | | Summary: std::error_code assumes it isn't an error if the error code is zero. Patch by Karl Schimpf Reviewers: rafael Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10815 llvm-svn: 241933
* [LoopDist/LoopVer] Move LoopVersioning to a new module, NFCAdam Nemet2015-07-104-115/+208
| | | | | | | | | | | | | | | | | | | Summary: The class will obviously need improvement down the road. For one, there is no reason that addPHINodes would have to be exposed like that. I will make this and other improvements in follow-up patches. The main goal is to be able to share this functionality. The LoopLoadElimination pass I am working on needs it too. Later we can move other clients as well (LV and Ashutosh's LICMVer). Reviewers: hfinkel, ashutosh.nema Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10577 llvm-svn: 241932
* [LoopDist] Move loop-versioning helper functions to Cloning, NFCAdam Nemet2015-07-103-66/+86
| | | | | | | | | | | | | | Summary: This makes them available to the LoopVersioning class as that is moved to its own module in the next patch. Reviewers: ashutosh.nema, hfinkel Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10576 llvm-svn: 241931
* ARMLoadStoreOpt: Merge subs/adds into LDRD/STRD; Factor out common codeMatthias Braun2015-07-102-170/+238
| | | | | | | | | | | | This commit factors out common code from MergeBaseUpdateLoadStore() and MergeBaseUpdateLSMultiple() and introduces a new function MergeBaseUpdateLSDouble() which merges adds/subs preceding/following a strd/ldrd instruction into an strd/ldrd instruction with writeback where possible. Differential Revision: http://reviews.llvm.org/D10676 llvm-svn: 241928
* ComputeKnownBits: be a bit smarter about ADDsFiona Glaser2015-07-103-12/+22
| | | | | | | | If our two inputs have known top-zero bit counts M and N, we trivially know that the output cannot have any bits set in the top (min(M, N)-1) bits, since nothing could carry past that point. llvm-svn: 241927
* ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2Matthias Braun2015-07-107-45/+132
| | | | | | Differential Revision: http://reviews.llvm.org/D10623 llvm-svn: 241926
* WebAssembly: basic instructions todo, and basic register info.JF Bastien2015-07-1016-19/+331
| | | | | | | | | | | | | | Summary: This code is based on AArch64 for modern backend good practice, and NVPTX for virtual ISA concerns. Reviewers: sunfish Subscribers: aemerson, llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11070 llvm-svn: 241923
* MIR Serialization: Initial serialization of stack objects.Alex Lorenz2015-07-104-4/+121
| | | | | | | | | | | | | | This commit implements the initial serialization of stack objects from the MachineFrameInfo class. It can only serialize the ordinary stack objects (including ordinary spill slots), but it doesn't serialize variable sized or fixed stack objects yet. The stack objects are serialized using a YAML sequence of YAML inline mappings. Each mapping has the object's ID, type, size, offset and alignment. The stack objects are a part of machine function's YAML mapping. Reviewers: Duncan P. N. Exon Smith llvm-svn: 241922
* Target RegisterInfo: devirtualize TargetFrameLoweringJF Bastien2015-07-109-61/+62
| | | | | | | | | | | | | Summary: The target frame lowering's concrete type is always known in RegisterInfo, yet it's only sometimes devirtualized through a static_cast. This change adds an auto-generated static function <Target>GenRegisterInfo::getFrameLowering(const MachineFunction &MF) which does this devirtualization, and uses this function in all targets which can. This change was suggested by sunfish in D11070 for WebAssembly, I figure that I may as well improve the other targets while I'm here. Subscribers: sunfish, ted, llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11093 llvm-svn: 241921
* ARMLoadStoreOptimizer: Rewrite LDM/STM matching logic.Matthias Braun2015-07-102-553/+483
| | | | | | | | | | | | | | | | | | | | | This improves the logic in several ways and is a preparation for followup patches: - First perform an analysis and create a list of merge candidates, then transform. This simplifies the code in that you have don't have to care to much anymore that you may be holding iterators to MachineInstrs that get removed. - Analyze/Transform basic blocks in reverse order. This allows to use LivePhysRegs to find free registers instead of the RegisterScavenger. The RegisterScavenger will become less precise in the future as it relies on the deprecated kill-flags. - Return the newly created node in MergeOps so there's no need to look around in the schedule to find it. - Rename some MBBI iterators to InsertBefore to make their role clear. - General code cleanup. Differential Revision: http://reviews.llvm.org/D10140 llvm-svn: 241920
* Actually support volatile memcpys in NVPTX loweringEli Bendersky2015-07-102-8/+23
| | | | | | Differential Revision: http://reviews.llvm.org/D11091 llvm-svn: 241914
* NFC. Added a blank line for consistency.Nemanja Ivanovic2015-07-101-0/+1
| | | | llvm-svn: 241913
* [InstSimplify] Fold away ord/uno fcmps when nnan is present.Benjamin Kramer2015-07-104-11/+35
| | | | | | | This is important to fold away the slow case of complex multiplies emitted by clang. llvm-svn: 241911
* Add support for fast-math flags to the FCmp instruction.James Molloy2015-07-108-54/+149
| | | | | | | | | | | | | | FCmp behaves a lot like a floating-point binary operator in many ways, and can benefit from fast-math information. Flags such as nsz and nnan can affect if this fcmp (in combination with a select) can be treated as a fminnum/fmaxnum operation. This adds backwards-compatible bitcode support, IR parsing and writing, LangRef changes and IRBuilder changes. I'll need to audit InstSimplify and InstCombine in a followup to find places where flags should be copied. llvm-svn: 241901
* Add missing builtins to the PPC back end for ABI compliance (vol. 3)Nemanja Ivanovic2015-07-102-0/+5
| | | | | | | | | This patch corresponds to review: http://reviews.llvm.org/D10973 Back end portion of the third round of additions to altivec.h. llvm-svn: 241900
* Disable loop re-rotation for -Oz (patch by Andrey Turetsky)Alexey Bataev2015-07-102-2/+32
| | | | | | | After changes in rL231820 loop re-rotation is performed even in -Oz mode. Since loop rotation is disabled for -Oz, it seems loop re-rotation should be disabled too. Differential Revision: http://reviews.llvm.org/D10961 llvm-svn: 241897
* [llvm-stress] Enhance scalar type selection from command line.Pawel Bylica2015-07-101-39/+54
| | | | | | | | | | llvm-stress command line options like -generate-x86-fp80 has been replaced with one list-like option -types. E.g. llvm-stress -types=x86_fp80,i100,i256,half. Default types (i1, i8, i16, i32, i64, float, double) are always added at the beginning of that list. Reviewers: hfinkel Differential Revision: http://reviews.llvm.org/D10667 llvm-svn: 241896
* llvm/Object/ELF.h: Appease g++-4.7.2.NAKAMURA Takumi2015-07-101-1/+1
| | | | llvm-svn: 241895
* Revert the new EH instructionsDavid Majnemer2015-07-1035-2129/+93
| | | | | | This reverts commits r241888-r241891, I didn't mean to commit them. llvm-svn: 241893
* Add missing 'const'. I don't think this is strictly required, but someDaniel Jasper2015-07-101-1/+1
| | | | | | | compiler configuration is giving me an error and it seems to be recommended anyway. llvm-svn: 241892
* Tighten the verifier check for catchblock.David Majnemer2015-07-102-9/+10
| | | | llvm-svn: 241891
* Address Joseph's review comments.David Majnemer2015-07-105-13/+92
| | | | llvm-svn: 241890
* Address Reid's review feedback.David Majnemer2015-07-103-22/+27
| | | | llvm-svn: 241889
* New EH representation for MSVC compatibilityDavid Majnemer2015-07-1035-91/+2042
| | | | | | | | | | | | | | | Summary: This introduces new instructions neccessary to implement MSVC-compatible exception handling support. Most of the middle-end and none of the back-end haven't been audited or updated to take them into account. Reviewers: rnk, JosephTremoulet, reames, nlewycky, rjmccall Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11041 llvm-svn: 241888
* [InstCombine] Employ AliasAnalysis in FindAvailableLoadedValueBjorn Steinbrink2015-07-104-8/+33
| | | | llvm-svn: 241887
* [InstCombine] Properly combine metadata when replacing a load with anotherBjorn Steinbrink2015-07-102-1/+49
| | | | | | | | Not doing this can lead to misoptimizations down the line, e.g. because of range metadata on the replacing load excluding values that are valid for the load that is being replaced. llvm-svn: 241886
* [NVPTX] declare no vector registersJingyue Wu2015-07-103-0/+47
| | | | | | | | | | | | | | | | | Summary: Without this patch, LoopVectorizer in certain cases (see loop-vectorize.ll) produces code with complex control flow which hurts later optimizations. Since NVPTX doesn't have vector registers in LLVM's sense (NVPTXTTI::getRegisterBitWidth(true) == 32), we for now declare no vector registers to effectively disable loop vectorization. Reviewers: jholewinski Subscribers: jingyue, llvm-commits, jholewinski Differential Revision: http://reviews.llvm.org/D11089 llvm-svn: 241884
* [WinEH] Make sure LSDA tables are 4 byte alignedReid Kleckner2015-07-107-2/+12
| | | | | | | | | | Apparently this is important, otherwise _except_handler3 assumes that the registration node is corrupted and ignores it. Also fix a bug in WinEHPrepare where we would insert code after a terminator instruction. llvm-svn: 241877
* Replace index-loops by range-based loopsEli Bendersky2015-07-091-6/+3
| | | | | | NFC llvm-svn: 241875
* [x86] enable machine combiner reassociations for scalar double-precision ↵Sanjay Patel2015-07-092-1/+26
| | | | | | multiplies llvm-svn: 241873
* [x86] enable machine combiner reassociations for scalar double-precision addsSanjay Patel2015-07-092-1/+25
| | | | llvm-svn: 241871
* Fix shadowing.Michael J. Spencer2015-07-092-2/+2
| | | | llvm-svn: 241870
* [Object][ELF] Support dumping hash-tables from files with no section table.Michael J. Spencer2015-07-098-27/+102
| | | | | | This time without breaking the bots. llvm-svn: 241869
* MIR Serialization: Serialize the virtual register definitions.Alex Lorenz2015-07-095-7/+141
| | | | | | | | | | | | The virtual registers are serialized using a YAML sequence of YAML inline mappings. Each mapping has the id of the virtual register and the register class. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10981 llvm-svn: 241868
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