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* [llvm-config][GlobalISel] Canonicalize LLVM_HAS_GLOBAL_ISEL on ON/OFF.Quentin Colombet2016-07-211-1/+5
| | | | | | | | | | | Previously LLVM_HAS_GLOBAL_ISEL would directly get the value of LLVM_BUILD_GLOBAL_ISEL. This could be any integer value and not just ON and OFF. The problem is that lit.cfg was checking for ON to define that global-isel was supported, thus if we were setting LLVM_BUILD_GLOBAL_ISEL with an integer value, say 1, this test would fail whereas we do build global-isel and want to test it. llvm-svn: 276307
* [CMake][GlobalISel] Turn LLVM_BUILD_GLOBAL_ISEL into an option. NFC.Quentin Colombet2016-07-211-1/+1
| | | | | | | | Previously LLVM_BUILD_GLOBAL_ISEL was a boolean variable and although, this is strictly identical to an option, it did not convey the information that the user may set it. Options are here for that. llvm-svn: 276306
* [IRTranslator] Add comments to explain the ordering of the switch. NFC.Quentin Colombet2016-07-211-0/+3
| | | | | | Group arithmetic operations, bitwise operations, and branch operations. llvm-svn: 276305
* [InstCombine] break up visitICmpInstWithInstAndIntCst(); NFCISanjay Patel2016-07-212-155/+166
| | | | | | | Making smaller pieces out of some of these ~1000 line functions should make it easier to incrementally upgrade them to handle vector types. llvm-svn: 276304
* Adding RELEASE_TESTERS.TXTRenato Golin2016-07-212-0/+60
| | | | llvm-svn: 276302
* [AMDGPU] Emit read-only data to .rodata for hsaKonstantin Zhuravlyov2016-07-213-3/+4
| | | | | | Differential Revision: https://reviews.llvm.org/D22538 llvm-svn: 276298
* [IRTranslator] Add G_AND opcode.Quentin Colombet2016-07-214-0/+36
| | | | | | This commit adds a generic AND opcode to global-isel. llvm-svn: 276297
* AMDGPU/SI: Add support for R_AMDGPU_ABS32Konstantin Zhuravlyov2016-07-213-0/+18
| | | | | | Differential Revision: https://reviews.llvm.org/D21646 llvm-svn: 276294
* [AArch64] Load/store opt: Don't count transient instructions towards search ↵Geoff Berry2016-07-212-15/+155
| | | | | | | | | | | | | | | | | | limits. Summary: This change also changes findMatchingInsn and findMatchingUpdateInsnForward to take DBG_VALUE opcodes into account when tracking register defs and uses, which could potentially inhibit these optimizations in the presence of debug information. Reviewers: mcrosier Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D22582 llvm-svn: 276293
* Weaken ThreadSafeRefCountedBase atomics.Benjamin Kramer2016-07-211-2/+2
| | | | | | | Doesn't make a difference on x86, but avoids memory barriers on weakly-ordered archs like PowerPC and ARM. llvm-svn: 276291
* [X86][SSE] Allow folding of store/zext with PEXTRW of 0'th elementSimon Pilgrim2016-07-2118-131/+85
| | | | | | | | | | | | | | Under normal circumstances we prefer the higher performance MOVD to extract the 0'th element of a v8i16 vector instead of PEXTRW. But as detailed on PR27265, this prevents the SSE41 implementation of PEXTRW from folding the store of the 0'th element. Additionally it prevents us from making use of the fact that the (SSE2) reg-reg version of PEXTRW implicitly zero-extends the i16 element to the i32/i64 destination register. This patch only preferentially lowers to MOVD if we will not be zero-extending the extracted i16, nor prevent a store from being folded (on SSSE41). Fix for PR27265. Differential Revision: https://reviews.llvm.org/D22509 llvm-svn: 276289
* Fixed line endingsSimon Pilgrim2016-07-211-105/+105
| | | | llvm-svn: 276287
* [X86][SSE] Pull out duplicate EXTRW lowering code. NFCI.Simon Pilgrim2016-07-211-26/+16
| | | | | | As requested on D22509, I've pulled out the v8i16 extraction lowering as the SSE41 and pre-SSE41 implementations are effectively the same. llvm-svn: 276285
* [profdata] Remove constructor that MSVC 2013 pretends to not understand.Benjamin Kramer2016-07-211-6/+2
| | | | | | No functionality change intended. llvm-svn: 276284
* [X86][AVX] Added support for lowering to VBROADCASTF128/VBROADCASTI128Simon Pilgrim2016-07-2111-207/+167
| | | | | | | | | | | | As reported on PR26235, we don't currently make use of the VBROADCASTF128/VBROADCASTI128 instructions (or the AVX512 equivalents) to load+splat a 128-bit vector to both lanes of a 256-bit vector. This patch enables lowering from subvector insertion/concatenation patterns and auto-upgrades the llvm.x86.avx.vbroadcastf128.pd.256 / llvm.x86.avx.vbroadcastf128.ps.256 intrinsics to match. We could possibly investigate using VBROADCASTF128/VBROADCASTI128 to load repeated constants as well (similar to how we already do for scalar broadcasts). Differential Revision: https://reviews.llvm.org/D22460 llvm-svn: 276281
* [DemandedBits] Reduce number of duplicated DenseMap lookups.Benjamin Kramer2016-07-211-5/+4
| | | | | | No functionality change intended. llvm-svn: 276278
* [DenseMap] Add a C++17-style try_emplace method.Benjamin Kramer2016-07-212-37/+45
| | | | | | | | This provides an elegant pattern to solve the "construct if not in map already" problem we have many times in LLVM. Without try_emplace we either have to rely on a sentinel value (nullptr) or do two lookups. llvm-svn: 276277
* Rename StringMap::emplace_second to try_emplace.Benjamin Kramer2016-07-215-9/+7
| | | | | | | Coincidentally this function maps to the C++17 try_emplace. Rename it for consistentcy with C++17 std::map. NFC. llvm-svn: 276276
* [AMDGPU] Some code cleaning in SIRegisterInfo.tdSam Kolton2016-07-211-33/+23
| | | | | | | | | | Reviewers: tstellarAMD, vpykhtin Subscribers: arsenm, kzhuravl Differential Revision: https://reviews.llvm.org/D22620 llvm-svn: 276274
* ExecutionDepsFix - Fix bug in clearance calculationMarina Yatsina2016-07-212-2/+10
| | | | | | | | The clearance calculation did not take into account registers defined as outputs or clobbers in inline assembly machine instructions because these register defs are implicit. Differential Revision: http://reviews.llvm.org/D22580 llvm-svn: 276266
* [GCOV] Remove a layer of indirection.Benjamin Kramer2016-07-211-18/+10
| | | | | | | StringMap is designed to hold large values. No functionality change intended. llvm-svn: 276265
* [docs] Update release docsRenato Golin2016-07-211-151/+91
| | | | llvm-svn: 276264
* AMDGPU: Fix phis from blocks split due to register indexingMatt Arsenault2016-07-212-27/+69
| | | | llvm-svn: 276257
* [GVNHoist] Preserve optimization hints which agreeDavid Majnemer2016-07-212-3/+61
| | | | | | | If we have optimization hints with agree with each other along different paths, preserve them. llvm-svn: 276248
* [GVNHoist] Don't wrongly preserve TBAADavid Majnemer2016-07-212-0/+41
| | | | | | | We hoisted loads/stores without taking into account which can cause miscompiles. llvm-svn: 276240
* [MergedLoadStoreMotion] Remove out of date commentDavid Majnemer2016-07-211-1/+0
| | | | llvm-svn: 276239
* Add missing import to fix the buildAmaury Sechet2016-07-211-0/+1
| | | | llvm-svn: 276237
* Expose AttributeSetNode, use it to provide aggregate getter for attribute in ↵Amaury Sechet2016-07-215-68/+133
| | | | | | | | | | | | | | the C API. Summary: See D19181 for context. Reviewers: whitequark, Wallbraker, jyknight, echristo, bkramer, void Subscribers: mehdi_amini Differential Revision: http://reviews.llvm.org/D21265 llvm-svn: 276236
* IPRA: Fix RegMask calculation for alias registersMatthias Braun2016-07-212-12/+13
| | | | | | | | | | | | | | | | | | | | | | | This patch fixes a very subtle bug in regmask calculation. Thanks to zan jyu Wong <zyfwong@gmail.com> for bringing this to notice. For example if CL is only clobbered than CH should not be marked clobbered but CX, RCX and ECX should be mark clobbered. Previously for each modified register all of its aliases are marked clobbered by markRegClobbred() in RegUsageInfoCollector.cpp but that is wrong because when CL is clobbered then MRI::isPhysRegModified() will return true for CL, CX, ECX, RCX which is correct behavior but then for CX, EXC, RCX we mark CH also clobbered as CH is aliased to CX,ECX,RCX so markRegClobbred() is not required because isPhysRegModified already take cares of proper aliasing register. A very simple test case has been added to verify this change. Please find relevant bug report here : http://llvm.org/PR28567 Patch by Vivek Pandya <vivekvpandya@gmail.com> Differential Revision: https://reviews.llvm.org/D22400 llvm-svn: 276235
* [OptDiag] Missed these when making the IR Value a const pointerAdam Nemet2016-07-212-5/+8
| | | | llvm-svn: 276224
* [OptDiag,LV] Add hotness attribute to applied-optimization remarksAdam Nemet2016-07-215-13/+44
| | | | | | | Test coverage is provided by modifying the function in the FP-math testcase that we are allowed to vectorize. llvm-svn: 276223
* X86InstrInfo: No need for liveness analysis in classifyLEAReg()Matthias Braun2016-07-211-18/+2
| | | | | | | | | | | | | | | | | | | | classifyLEAReg() deals with switching operands from 32bit to 64bit in order to use a LEA64_32 instruction (for three address code goodness). It currently performs a liveness analysis to determine the kill/undef flag for the newly added operand. This should not be necessary: - If the previous operand had a kill flag, then the 32bit part of the register gets killed, this will kill the super register as well. - If the previous operand had an undef flag then we didn't care what value we read, just use the same flag on the new operand. (No matter what an operand with an undef flag won't affect liveness) This makes the code independent of the presence of kill flags because it avoids a call to MachineBasicBlock::computeRegisterLiveness(). Differential Revision: http://reviews.llvm.org/D22283 llvm-svn: 276222
* [InstCombine] LogicOpc (zext X), C --> zext (LogicOpc X, C) (PR28476)Sanjay Patel2016-07-219-82/+58
| | | | | | | | | | | | | | | | The benefits of this change include: 1. Remove DeMorgan-matching code that was added specifically to work-around the missing transform in http://reviews.llvm.org/rL248634. 2. Makes the DeMorgan transform work for vectors too. 3. Fix PR28476: https://llvm.org/bugs/show_bug.cgi?id=28476 Extending this transform to other casts and other associative operators may be useful too. See https://reviews.llvm.org/D22421 for a prerequisite for doing that though. Differential Revision: https://reviews.llvm.org/D22271 llvm-svn: 276221
* [OptDiag,LV] Add hotness attribute to the derived analysis remarksAdam Nemet2016-07-205-24/+189
| | | | | | | | This includes FPCompute and Aliasing. Testcase is based on no_fpmath.ll. llvm-svn: 276211
* [InstSimplify][InstCombine] don't crash when folding vector selects of icmpSanjay Patel2016-07-204-2/+42
| | | | | | Differential Revision: https://reviews.llvm.org/D22602 llvm-svn: 276209
* Make help text more consistent. NFC.George Burgess IV2016-07-201-1/+1
| | | | llvm-svn: 276205
* GlobalISel: Remove explicit enumerator values from .def file.Tim Northover2016-07-203-31/+31
| | | | | | | | | | They were all auto-incremented from 0 anyway, and I'm getting really annoying conflicts and runtime failures when different people add more for GlobalISel (and even when I'm refactoring my own patches). NFC. llvm-svn: 276204
* Fix test failure on WinXinliang David Li2016-07-201-5/+5
| | | | llvm-svn: 276202
* [CFLAA] Add offset tracking in CFLGraph.George Burgess IV2016-07-201-13/+122
| | | | | | | | | | | | | | | | (Also, refactor our constexpr handling to be less insane). This patch lets us track field offsets in the CFL Graph, which is the first step to making CFLAA field/offset sensitive. Woohoo! Note that this patch shouldn't visibly change our behavior (since we make no use of the offsets we're now tracking), so we can't quite add tests for this yet. Patch by Jia Chen. Differential Revision: https://reviews.llvm.org/D22598 llvm-svn: 276201
* [utils] Add script to check for code coverage regressionsVedant Kumar2016-07-201-0/+135
| | | | | | Differential Revision: https://reviews.llvm.org/D22544 llvm-svn: 276199
* Reapply r276185Xinliang David Li2016-07-203-18/+65
| | | | | | Fix the test case that should not depend on dir iteration order. llvm-svn: 276197
* [NVPTX] Enable the load-store vectorizer on nvptx.Justin Lebar2016-07-204-17/+44
| | | | | | | | | | Reviewers: tra Subscribers: jholewinski, arsenm, asbirlea Differential Revision: https://reviews.llvm.org/D22592 llvm-svn: 276196
* Revert r276185 -- build bot failure Xinliang David Li2016-07-203-65/+18
| | | | llvm-svn: 276194
* [AArch64] Register AArch64LoadStoreOptimizer so it can be run by llc ↵Geoff Berry2016-07-204-8/+2
| | | | | | -run-pass. NFCI. llvm-svn: 276193
* [OptDiag,LV] Add hotness attribute to analysis remarksAdam Nemet2016-07-207-60/+299
| | | | | | | | The earlier change added hotness attribute to missed-optimization remarks. This follows up with the analysis remarks (the ones explaining the reason for the missed optimization). llvm-svn: 276192
* [OptDiag] Take the IR Value as a const pointerAdam Nemet2016-07-202-4/+5
| | | | | | | | This helps because LoopAccessReport is passed around as a const reference and we derive the basic block passed as the Value parameter from the instruction in LoopAccessReport. llvm-svn: 276191
* [OptDiag] Wrap a long lineAdam Nemet2016-07-201-1/+2
| | | | llvm-svn: 276190
* [NVPTX] Renamed NVPTXLowerKernelArgs -> NVPTXLowerArgs. NFC.Artem Belevich2016-07-205-22/+22
| | | | | | | | After r276153 the pass applies to both kernels and regular functions. Differential Revision: https://reviews.llvm.org/D22583 llvm-svn: 276189
* [Profile] support directory reading in profile mergingXinliang David Li2016-07-203-18/+65
| | | | | | Differential Revision: http://reviews.llvm.org/D22560 llvm-svn: 276185
* GlobalISel: implement Legalization querying framework.Tim Northover2016-07-207-0/+400
| | | | | | | This adds an (incomplete, inefficient) framework for deciding what to do with some operation on a given type. llvm-svn: 276184
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