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* Rename BlackList class to SpecialCaseList and move it to Transforms/Utils.Peter Collingbourne2013-07-097-24/+24
| | | | | | Differential Revision: http://llvm-reviews.chandlerc.com/D1089 llvm-svn: 185975
* InstSimplify: X >> X -> 0David Majnemer2013-07-093-3/+27
| | | | llvm-svn: 185973
* move test into the appropriate subdir.Adrian Prantl2013-07-091-0/+0
| | | | llvm-svn: 185972
* Typo.Adrian Prantl2013-07-091-1/+1
| | | | llvm-svn: 185971
* Fix PR16571, which is a bug in the code that checks that all of the types in ↵Nadav Rotem2013-07-092-1/+25
| | | | | | the bundle are uniform. llvm-svn: 185970
* Reapply an improved version of r180816/180817.Adrian Prantl2013-07-0914-54/+237
| | | | | | | | | | | | | | | Change the informal convention of DBG_VALUE machine instructions so that we can express a register-indirect address with an offset of 0. The old convention was that a DBG_VALUE is a register-indirect value if the offset (operand 1) is nonzero. The new convention is that a DBG_VALUE is register-indirect if the first operand is a register and the second operand is an immediate. For plain register values the combination reg, reg is used. MachineInstrBuilder::BuildMI knows how to build the new DBG_VALUES. rdar://problem/13658587 llvm-svn: 185966
* Fixed up the comments in FastISel.h so that they conform to the LLVM style ↵Michael Gottesman2013-07-091-150/+122
| | | | | | guide. llvm-svn: 185964
* Added "mode: c++" to FastISel.h header.Michael Gottesman2013-07-091-1/+1
| | | | llvm-svn: 185963
* Appease buildbots after r185956: just set -mcpu explicitly, as it should ↵Stephen Lin2013-07-092-4/+4
| | | | | | have been from the beginning. llvm-svn: 185962
* Appease Atom buildbot after r185956 (explicitly turn on AVX)Stephen Lin2013-07-092-2/+2
| | | | llvm-svn: 185961
* WidenVecRes_BUILD_VECTOR must use the first operand's typeHal Finkel2013-07-092-1/+27
| | | | | | | | | | | Because integer BUILD_VECTOR operands may have a larger type than the result's vector element type, and all operands must have the same type, when widening a BUILD_VECTOR node by adding UNDEFs, we cannot use the vector element type, but rather must use the type of the existing operands. Another bug found by llvm-stress. llvm-svn: 185960
* [PowerPC] Better fix for PR16556.Bill Schmidt2013-07-092-9/+44
| | | | | | | | | | | | | | | | | A more complete example of the bug in PR16556 was recently provided, showing that the previous fix was not sufficient. The previous fix is reverted herein. The real problem is that ReplaceNodeResults() uses LowerFP_TO_INT as custom lowering for FP_TO_SINT during type legalization, without checking whether the input type is handled by that routine. LowerFP_TO_INT requires the input to be f32 or f64, so we fail when the input is ppcf128. I'm leaving the test case from the initial fix (r185821) in place, and adding the new test as another crash-only check. llvm-svn: 185959
* Attempt to appease buildbot after r185956 by explicitly turning setting ↵Stephen Lin2013-07-092-2/+2
| | | | | | -fma,-fma4 attrs (I'm assuming they're set because the bot is running on machine that has one or the other.) llvm-svn: 185958
* AArch64/PowerPC/SystemZ/X86: This patch fixes the interface, usage, and allStephen Lin2013-07-0917-37/+329
| | | | | | | | | | | | | | | | | | | | | | | in-tree implementations of TargetLoweringBase::isFMAFasterThanMulAndAdd in order to resolve the following issues with fmuladd (i.e. optional FMA) intrinsics: 1. On X86(-64) targets, ISD::FMA nodes are formed when lowering fmuladd intrinsics even if the subtarget does not support FMA instructions, leading to laughably bad code generation in some situations. 2. On AArch64 targets, ISD::FMA nodes are formed for operations on fp128, resulting in a call to a software fp128 FMA implementation. 3. On PowerPC targets, FMAs are not generated from fmuladd intrinsics on types like v2f32, v8f32, v4f64, etc., even though they promote, split, scalarize, etc. to types that support hardware FMAs. The function has also been slightly renamed for consistency and to force a merge/build conflict for any out-of-tree target implementing it. To resolve, see comments and fixed in-tree examples. llvm-svn: 185956
* Don't crash in SE dealing with ashr x, -1Hal Finkel2013-07-092-1/+19
| | | | | | | | | | | | | | ScalarEvolution::getSignedRange uses ComputeNumSignBits from ValueTracking on ashr instructions. ComputeNumSignBits can return zero, but this case was not handled correctly by the code in getSignedRange which was calling: APInt::getSignedMinValue(BitWidth).ashr(NS - 1) with NS = 0, resulting in an assertion failure in APInt::ashr. Now, we just return the conservative result (as with NS == 1). Another bug found by llvm-stress. llvm-svn: 185955
* ValueTracking: Fix bugs in isKnownToBeAPowerOfTwoDavid Majnemer2013-07-092-21/+4
| | | | | | | (add nsw x, (and x, y)) isn't a power of two if x is zero, it's zero (add nsw x, (xor x, y)) isn't a power of two if y has bits set that aren't set in x llvm-svn: 185954
* Set the default insert point to the first instruction, and not to end()Nadav Rotem2013-07-091-1/+1
| | | | llvm-svn: 185953
* IRBuilder: add an assertion that checks if we try to get a debug loc from ↵Nadav Rotem2013-07-091-0/+1
| | | | | | ->end(); llvm-svn: 185952
* DAGCombine tryFoldToZero cannot create illegal types after type legalizationHal Finkel2013-07-092-4/+28
| | | | | | | | | | | When folding sub x, x (and other similar constructs), where x is a vector, the result is a vector of zeros. After type legalization, make sure that the input zero elements have a legal type. This type may be larger than the result's vector element type. This was another bug found by llvm-stress. llvm-svn: 185949
* [PowerPC] Revert r185476 and fix up TLS variant kindsUlrich Weigand2013-07-0910-11/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the commit message to r185476 I wrote: >The PowerPC-specific modifiers VK_PPC_TLSGD and VK_PPC_TLSLD >correspond exactly to the generic modifiers VK_TLSGD and VK_TLSLD. >This causes some confusion with the asm parser, since VK_PPC_TLSGD >is output as @tlsgd, which is then read back in as VK_TLSGD. > >To avoid this confusion, this patch removes the PowerPC-specific >modifiers and uses the generic modifiers throughout. (The only >drawback is that the generic modifiers are printed in upper case >while the usual convention on PowerPC is to use lower-case modifiers. >But this is just a cosmetic issue.) This was unfortunately incorrect, there is is fact another, serious drawback to using the default VK_TLSLD/VK_TLSGD variant kinds: using these causes ELFObjectWriter::RelocNeedsGOT to return true, which in turn causes the ELFObjectWriter to emit an undefined reference to _GLOBAL_OFFSET_TABLE_. This is a problem on powerpc64, because it uses the TOC instead of the GOT, and the linker does not provide _GLOBAL_OFFSET_TABLE_, so the symbol remains undefined. This means shared libraries using TLS built with the integrated assembler are currently broken. While the whole RelocNeedsGOT / _GLOBAL_OFFSET_TABLE_ situation probably ought to be properly fixed at some point, for now I'm simply reverting the r185476 commit. Now this in turn exposes the breakage of handling @tlsgd/@tlsld in the asm parser that this check-in was originally intended to fix. To avoid this regression, I'm also adding a different fix for this problem: while common code now parses @tlsgd as VK_TLSGD, a special hack in the asm parser translates this code to the platform-specific VK_PPC_TLSGD that the back-end now expects. While this is not really pretty, it's self-contained and shouldn't hurt anything else for now. One the underlying problem is fixed, this hack can be reverted again. llvm-svn: 185945
* R600: Do not predicated basic block with multiple alu clauseVincent Lejeune2013-07-097-8/+65
| | | | | | | | | Test is not included as it is several 1000 lines long. To test this functionnality, a test case must generate at least 2 ALU clauses, where an ALU clause is ~110 instructions long. NOTE: This is a candidate for the stable branch. llvm-svn: 185943
* R600: Fix a rare bug where swizzle optimization returns wrong valuesVincent Lejeune2013-07-092-2/+37
| | | | llvm-svn: 185942
* R600: Fix wrong export reswizzlingVincent Lejeune2013-07-092-4/+100
| | | | llvm-svn: 185941
* R600: Use DAG lowering pass to handle fcos/fsinVincent Lejeune2013-07-096-23/+58
| | | | | NOTE: This is a candidate for the stable branch. llvm-svn: 185940
* R600: Print Export SwizzleVincent Lejeune2013-07-091-2/+2
| | | | llvm-svn: 185939
* Add missing getters. They will be used in llvm-ar.Rafael Espindola2013-07-092-0/+46
| | | | llvm-svn: 185937
* Archive members cannot be larger than 4GB. Return a uint32_t.Rafael Espindola2013-07-092-6/+7
| | | | llvm-svn: 185936
* We never compare iterators from two archives. Assert that.Rafael Espindola2013-07-091-1/+2
| | | | llvm-svn: 185934
* Add getHeader helper and move ToHeader to the cpp file.Rafael Espindola2013-07-092-7/+11
| | | | llvm-svn: 185933
* Add MC assembly/disassembly support for VRINT{A, N, P, M} to V8FP.Joey Gouly2013-07-095-3/+102
| | | | llvm-svn: 185929
* Add MC assembly/disassembly support for VRINT{Z, X, R} to V8FP.Joey Gouly2013-07-093-0/+55
| | | | llvm-svn: 185926
* Document LLVM_USE_SANITIZER CMake optionAlexey Samsonov2013-07-091-0/+5
| | | | llvm-svn: 185925
* [PowerPC] Support ".machine any"Ulrich Weigand2013-07-092-0/+41
| | | | | | | | | | | | The PowerPC assembler is supposed to provide a directive .machine that allows switching the supported CPU instruction set on the fly. Since we do not yet check CPU feature sets at all and always accept any available instruction, this is not really useful at this point. However, it makes sense to accept (and ignore) ".machine any" to avoid spuriously rejecting existing assembler files that use this. llvm-svn: 185924
* Revert r185872 - "Stop emitting weak symbols into the "coal" sections"Alexander Potapenko2013-07-093-83/+10
| | | | | | | | | | | | | This patch broke `make check-asan` on Mac, causing ld warnings like the following one: ld: warning: direct access in __GLOBAL__I_a to global weak symbol ___asan_mapping_scale means the weak symbol cannot be overridden at runtime. This was likely caused by different translation units being compiled with different visibility settings. The resulting test binaries crashed with incorrect ASan warnings. llvm-svn: 185923
* Add MC assembly/disassembly support for VCVT{A, N, P, M} to V8FP.Joey Gouly2013-07-095-6/+173
| | | | llvm-svn: 185922
* [SystemZ] Use MVC for simple load/store pairsRichard Sandiford2013-07-096-2/+506
| | | | | | | | | | | | Look for patterns of the form (store (load ...), ...) in which the two locations are known not to partially overlap. (Identical locations are OK.) These sequences are better implemented by MVC unless either the load or the store could use RELATIVE LONG instructions. The testcase showed that we weren't using LHRL and LGHRL for extload16, only sextloadi16. The patch fixes that too. llvm-svn: 185919
* [SystemZ] Use "STC;MVC" for memsetRichard Sandiford2013-07-097-0/+1171
| | | | | | | | | | | | Use "STC;MVC" for memsets that are too big for two STCs or MV...Is yet small enough for a single MVC. As with memcpy, I'm leaving longer cases till later. The number of tests might seem excessive, but f33 & f34 from memset-04.ll failed the first cut because I'd not added the "?:" on the calculation of Size1. llvm-svn: 185918
* InstCombine: Fix typo in comment for visitICmpInstWithInstAndIntCstDavid Majnemer2013-07-091-2/+2
| | | | llvm-svn: 185916
* InstCombine: variations on 0xffffffff - x >= 4David Majnemer2013-07-092-0/+30
| | | | | | | | | | The following transforms are valid if -C is a power of 2: (icmp ugt (xor X, C), ~C) -> (icmp ult X, C) (icmp ult (xor X, C), -C) -> (icmp uge X, C) These are nice, they get rid of the xor. llvm-svn: 185915
* InstCombine: X & -C != -C -> X <= u ~CDavid Majnemer2013-07-092-40/+9
| | | | | | Tests were added in r185910 somehow. llvm-svn: 185912
* [PowerPC] Support .llong and fix .wordUlrich Weigand2013-07-094-2/+60
| | | | | | | | This adds support for the .llong PowerPC-specifc assembler directive. In doing so, I notices that .word is currently incorrect: it is supposed to define a 2-byte data element, not a 4-byte one. llvm-svn: 185911
* Commit r185909 was a misapplied patch, fix itDavid Majnemer2013-07-093-24/+73
| | | | llvm-svn: 185910
* InstCombine: add more transformsDavid Majnemer2013-07-094-5/+87
| | | | | | | | | C1-X <u C2 -> (X|(C2-1)) == C1 C1-X >u C2 -> (X|C2) == C1 X-C1 <u C2 -> (X & -C2) == C1 X-C1 >u C2 -> (X & ~C2) == C1 llvm-svn: 185909
* PPC: Allocate RS spill slot for unaligned i64 load/storeHal Finkel2013-07-092-2/+152
| | | | | | | | | | | | | | | | | | | This fixes another bug found by llvm-stress! If we happen to be doing an i64 load or store into a stack slot that has less than a 4-byte alignment, then the frame-index elimination may need to use an indexed load or store instruction (because the offset may not be a multiple of 4, a requirement of the STD/LD instructions). The extra register needed to hold the offset comes from the register scavenger, and it is possible that the scavenger will need to use an emergency spill slot. As a result, we need to make sure that a spill slot is allocated when doing an i64 load/store into a less-than-4-byte-aligned stack slot. Because test cases for things like this tend to be fairly fragile, I've concatenated a few small bugpoint-reduced test cases together to form the regression test. llvm-svn: 185907
* Compute the size of an archive member in the constructor.Rafael Espindola2013-07-092-16/+15
| | | | | | | It is always computed the same way (by parsing the header). Doing it in the constructor simplifies the callers a bit. llvm-svn: 185905
* Remove declare but not implemented methods.Rafael Espindola2013-07-091-4/+0
| | | | llvm-svn: 185904
* Move some code out of line. No functionality change.Rafael Espindola2013-07-092-65/+76
| | | | llvm-svn: 185901
* X86: Add comment.Jim Grosbach2013-07-091-0/+5
| | | | llvm-svn: 185900
* X86 fast-isel: Avoid explicit AH subreg reference for [SU]Rem.Jim Grosbach2013-07-091-4/+31
| | | | | | | | | | | | | Explicit references to %AH for an i8 remainder instruction can lead to references to %AH in a REX prefixed instruction, which causes things to blow up. Do the same thing in FastISel as we do for DAG isel and instead shift %AX right by 8 bits and then extract the 8-bit subreg from that result. rdar://14203849 http://llvm.org/bugs/show_bug.cgi?id=16105 llvm-svn: 185899
* Make BinaryRef output correctly in case of empty data.Sean Silva2013-07-096-1/+68
| | | | | | | Previously, it would simply output nothing, but it should output an empty string `""`. llvm-svn: 185894
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