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* Documentation: Lexicon.rst: add 'SLP' acronymDmitri Gribenko2012-12-111-1/+7
| | | | llvm-svn: 169928
* PR14574. Fix a bug in the code that calculates the mask the converted PHIs ↵Nadav Rotem2012-12-112-1/+45
| | | | | | in if-conversion. llvm-svn: 169916
* Add R600 backendTom Stellard2012-12-11146-1/+20232
| | | | | | A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915
* This patch implements the general dynamic TLS model for 64-bit PowerPC.Bill Schmidt2012-12-1115-15/+246
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Given a thread-local symbol x with global-dynamic access, the generated code to obtain x's address is: Instruction Relocation Symbol addis ra,r2,x@got@tlsgd@ha R_PPC64_GOT_TLSGD16_HA x addi r3,ra,x@got@tlsgd@l R_PPC64_GOT_TLSGD16_L x bl __tls_get_addr(x@tlsgd) R_PPC64_TLSGD x R_PPC64_REL24 __tls_get_addr nop <use address in r3> The implementation borrows from the medium code model work for introducing special forms of ADDIS and ADDI into the DAG representation. This is made slightly more complicated by having to introduce a call to the external function __tls_get_addr. Using the full call machinery is overkill and, more importantly, makes it difficult to add a special relocation. So I've introduced another opcode GET_TLS_ADDR to represent the function call, and surrounded it with register copies to set up the parameter and return value. Most of the code is pretty straightforward. I ran into one peculiarity when I introduced a new PPC opcode BL8_NOP_ELF_TLSGD, which is just like BL8_NOP_ELF except that it takes another parameter to represent the symbol ("x" above) that requires a relocation on the call. Something in the TblGen machinery causes BL8_NOP_ELF and BL8_NOP_ELF_TLSGD to be treated identically during the emit phase, so this second operand was never visited to generate relocations. This is the reason for the slightly messy workaround in PPCMCCodeEmitter.cpp:getDirectBrEncoding(). Two new tests are included to demonstrate correct external assembly and correct generation of relocations using the integrated assembler. Comments welcome! Thanks, Bill llvm-svn: 169910
* Update some comments.Eric Christopher2012-12-112-6/+6
| | | | llvm-svn: 169907
* Loop Vectorize: optimize the vectorization of trunc(induction_var). The ↵Nadav Rotem2012-12-115-5/+46
| | | | | | truncation is now done on scalars. llvm-svn: 169904
* Remove the RelaxAll overrule in MCAssembler::fixupNeedsRelaxation,Eli Bendersky2012-12-111-3/+2
| | | | | | | | | | | | because that method is only getting called for MCInstFragment. These fragments aren't even generated when RelaxAll is set, which is why the flag reference here is superfluous. Removing it simplifies the code with no harmful effects. An assertion is added higher up to make sure this path is never reached. llvm-svn: 169886
* Use an ArrayRef instead of a std::vector&.Rafael Espindola2012-12-112-6/+6
| | | | llvm-svn: 169881
* Add comment for load foldingJoel Jones2012-12-111-0/+5
| | | | llvm-svn: 169880
* Documentation: convert Passes.html to reST.Dmitri Gribenko2012-12-112-2025/+1264
| | | | | | | | | Since now we have an autogenerated TOC, a manually written table of all passes was removed. Patch by Anthony Mykhailenko with small fixes by me. llvm-svn: 169867
* llvm/test/TableGen: Remove XFAIL:vg_leak in dozen of tests, according to ↵NAKAMURA Takumi2012-12-1136-36/+0
| | | | | | llvm-x86_64-linux-vg_leak. llvm-svn: 169862
* [msan] Use explicitely aligned stores and loads with function argument shadow.Evgeniy Stepanov2012-12-111-8/+13
| | | | | | | | Use explicitely aligned store and load instructions to deal with argument and retval shadow. This matters when an argument's alignment is higher than __msan_param_tls alignment (which is the case with __m128i). llvm-svn: 169859
* Revert EVT->MVT changes, r169836-169851, due to buildbot failures.Patrik Hagglund2012-12-1128-281/+245
| | | | llvm-svn: 169854
* Holding my nose and moving the accumulation routine to GEPOperatorChandler Carruth2012-12-113-62/+44
| | | | | | | | | | | | | | | | | instead of the instruction. I've left a forwarding wrapper for the instruction so users with the instruction don't need to create a GEPOperator themselves. This lets us remove the copy of this code in instsimplify. I've looked at most of the other copies of similar code, and this is the only one I've found that is actually exactly the same. The one in InlineCost is very close, but it requires re-mapping non-constant indices through the cost analysis value simplification map. I could add direct support for this to the generic routine, but it seems overly specific. llvm-svn: 169853
* Hoist the GEP constant address offset computation to a common home onChandler Carruth2012-12-114-25/+46
| | | | | | | | | | | the GEP instruction class. This is part of the continued refactoring and cleaning of the infrastructure used by SROA. This particular operation is also done in a few other places which I'll try to refactor to share this implementation. llvm-svn: 169852
* Change RegVT in BitTestBlock and RegsForValue, to contain MVTs,Patrik Hagglund2012-12-112-13/+12
| | | | | | instead of EVTs. llvm-svn: 169851
* Change TargetLowering::getTypeForExtArgOrReturn to take and returnPatrik Hagglund2012-12-115-8/+30
| | | | | | | | MVTs, instead of EVTs. Accordingly, add bitsLT (and similar) to MVT. llvm-svn: 169850
* Change a parameter of TargetLowering::getVectorTypeBreakdown to MVT,Patrik Hagglund2012-12-113-18/+25
| | | | | | from EVT. llvm-svn: 169849
* Change TargetLowering::RegisterTypeForVT to contain MVTs, instead ofPatrik Hagglund2012-12-117-24/+24
| | | | | | EVTs. llvm-svn: 169848
* Change TargetLowering::TransformToType to contain MVTs, instead ofPatrik Hagglund2012-12-112-13/+13
| | | | | | EVTs. llvm-svn: 169847
* Change TargetLowering::getRepRegClassCostFor, getIndexedLoadAction,Patrik Hagglund2012-12-111-19/+16
| | | | | | | getIndexedStoreAction, and addRegisterClass to take an MVT, instead of EVT. llvm-svn: 169846
* Change TargetLowering::findRepresentativeClass to take an MVT, insteadPatrik Hagglund2012-12-116-9/+9
| | | | | | of EVT. llvm-svn: 169845
* Change TargetLowering::getTypeToPromoteTo to take and return MVTs,Patrik Hagglund2012-12-113-12/+12
| | | | | | instead of EVTs. llvm-svn: 169844
* Change TargetLowering::isCondCodeLegal to take an MVT, instead of EVT.Patrik Hagglund2012-12-113-15/+18
| | | | llvm-svn: 169843
* Change TargetLowering::getCondCodeAction to take an MVT, instead ofPatrik Hagglund2012-12-113-10/+10
| | | | | | EVT. llvm-svn: 169842
* Change TargetLowering::getTruncStoreAction to take MVTs, instead of EVTs.Patrik Hagglund2012-12-113-9/+9
| | | | llvm-svn: 169841
* Change TargetLowering::getLoadExtAction to take an MVT, instead of EVT.Patrik Hagglund2012-12-113-7/+7
| | | | llvm-svn: 169840
* Change TargetLowering::setTypeAction to take an MVT, instead fo EVT.Patrik Hagglund2012-12-112-3/+3
| | | | llvm-svn: 169839
* Change TargetLowering::getRepRegClassFor to take an MVT, instead ofPatrik Hagglund2012-12-115-15/+14
| | | | | | | | EVT. Accordingly, change RegDefIter to contain MVTs instead of EVTs. llvm-svn: 169838
* Change TargetLowering::getRegClassFor to take an MVT, instead of EVT.Patrik Hagglund2012-12-1113-78/+87
| | | | | | | | | Accordingly, add helper funtions getSimpleValueType (in parallel to getValueType) in SDValue, SDNode, and TargetLowering. This is the first, in a series of patches. llvm-svn: 169837
* revert the test changeHao Liu2012-12-111-1/+0
| | | | llvm-svn: 169823
* A newbie try a test commitHao Liu2012-12-111-0/+1
| | | | llvm-svn: 169821
* [CMake] Remove dependencies to intrinsics_gen I introduced in r169724.NAKAMURA Takumi2012-12-113-3/+3
| | | | llvm-svn: 169819
* llvm/Target/TargetMachine.h: Remove two dependent headers.NAKAMURA Takumi2012-12-111-2/+2
| | | | | | | -#include "llvm/Target/TargetTransformImpl.h" -#include "llvm/TargetTransformInfo.h" llvm-svn: 169818
* llvm/tools: Add #include "llvm/TargetTransformInfo.h"NAKAMURA Takumi2012-12-113-0/+3
| | | | llvm-svn: 169817
* Use multiclass for new-value store instructions with MEMri operand.Jyotsna Verma2012-12-111-148/+46
| | | | llvm-svn: 169814
* Fix PR14565. Don't if-convert loops that have switch statements in them.Nadav Rotem2012-12-112-0/+43
| | | | llvm-svn: 169813
* Change some functions to take const pointers.Rafael Espindola2012-12-112-24/+26
| | | | llvm-svn: 169812
* Stylistic tweak.Evan Cheng2012-12-111-9/+8
| | | | llvm-svn: 169811
* Add a triple to this test.Chad Rosier2012-12-111-1/+1
| | | | llvm-svn: 169803
* Fix a miscompile in the DAG combiner. Previously, we would incorrectlyChandler Carruth2012-12-112-4/+29
| | | | | | | | | | | | | | | | | | | | | | | try to reduce the width of this load, and would end up transforming: (truncate (lshr (sextload i48 <ptr> as i64), 32) to i32) to (truncate (zextload i32 <ptr+4> as i64) to i32) We lost the sext attached to the load while building the narrower i32 load, and replaced it with a zext because lshr always zext's the results. Instead, bail out of this combine when there is a conflict between a sextload and a zext narrowing. The rest of the DAG combiner still optimize the code down to the proper single instruction: movswl 6(...),%eax Which is exactly what we wanted. Previously we read past the end *and* missed the sign extension: movl 6(...), %eax llvm-svn: 169802
* move X86-specific testPaul Redmond2012-12-111-1/+1
| | | | | | | | This test case uses -mcpu=corei7 so it belongs in CodeGen/X86 Reviewed by: Nadav llvm-svn: 169801
* Fix grammar-o.Bill Wendling2012-12-111-1/+1
| | | | llvm-svn: 169798
* Fall back to the selection dag isel to select tail calls.Chad Rosier2012-12-116-17/+20
| | | | | | | | | | | | | | | | | | | This shouldn't affect codegen for -O0 compiles as tail call markers are not emitted in unoptimized compiles. Testing with the external/internal nightly test suite reveals no change in compile time performance. Testing with -O1, -O2 and -O3 with fast-isel enabled did not cause any compile-time or execution-time failures. All tests were performed on my x86 machine. I'll monitor our arm testers to ensure no regressions occur there. In an upcoming clang patch I will be marking the objc_autoreleaseReturnValue and objc_retainAutoreleaseReturnValue as tail calls unconditionally. While it's theoretically true that this is just an optimization, it's an optimization that we very much want to happen even at -O0, or else ARC applications become substantially harder to debug. Part of rdar://12553082 llvm-svn: 169796
* Refactor out the abbreviation handling into a separate class thatEric Christopher2012-12-103-25/+58
| | | | | | | | | | | | controls each of the abbreviation sets (only a single one at the moment) and computes offsets separately as well for each set of DIEs. No real function change, ordering of abbreviations for the skeleton CU changed but only because we're computing in a separate order. Fix the testcase not to care. llvm-svn: 169793
* Some enhancements for memcpy / memset inline expansion.Evan Cheng2012-12-1015-85/+299
| | | | | | | | | | | | | | | | | | | | | 1. Teach it to use overlapping unaligned load / store to copy / set the trailing bytes. e.g. On 86, use two pairs of movups / movaps for 17 - 31 byte copies. 2. Use f64 for memcpy / memset on targets where i64 is not legal but f64 is. e.g. x86 and ARM. 3. When memcpy from a constant string, do *not* replace the load with a constant if it's not possible to materialize an integer immediate with a single instruction (required a new target hook: TLI.isIntImmLegal()). 4. Use unaligned load / stores more aggressively if target hooks indicates they are "fast". 5. Update ARM target hooks to use unaligned load / stores. e.g. vld1.8 / vst1.8. Also increase the threshold to something reasonable (8 for memset, 4 pairs for memcpy). This significantly improves Dhrystone, up to 50% on ARM iOS devices. rdar://12760078 llvm-svn: 169791
* Optimistically analyse Phi cyclesArnold Schwaighofer2012-12-102-43/+76
| | | | | | | | | | Analyse Phis under the starting assumption that they are NoAlias. Recursively look at their inputs. If they MayAlias/MustAlias there must be an input that makes them so. Addresses bug 14351. llvm-svn: 169788
* Defer call to InitSections until after MCContext has been initialized. IfLang Hames2012-12-104-2/+18
| | | | | | | | InitSections is called before the MCContext is initialized it could cause duplicate temporary symbols to be emitted later (after context initialization resets the temporary label counter). llvm-svn: 169785
* Fix PR14568: Avoid the DFA packetizer from making an invalid readAnshuman Dasgupta2012-12-101-1/+10
| | | | | | | | | | beyond array bounds. No test case since I cannot reproduce an ICE with this bug. According to Carlos -- the bug reporter -- a segfault occurs only when LLVM is compiled with a specific version of GCC. llvm-svn: 169783
* Rearrange vars and make comments more obvious.Eric Christopher2012-12-101-3/+5
| | | | llvm-svn: 169780
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