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* Rename DiagnosticInfoOptimizationWarning to DiagnosticInfoOptimizationFailureTyler Nowicki2014-07-182-9/+9
| | | | | | | | so the severity of the message is not part of the type name. Reviewed by Alp Toker llvm-svn: 213399
* Use CHECK-LABEL where appropriate in this test.Eli Bendersky2014-07-181-18/+18
| | | | llvm-svn: 213398
* Add loop unrolling metadata descriptions to docs/LangRef.rst.Mark Heffernan2014-07-181-54/+97
| | | | llvm-svn: 213397
* MergedLoadStoreMotion passGerolf Hoflehner2014-07-1811-1/+736
| | | | | | | | | | | Merges equivalent loads on both sides of a hammock/diamond and hoists into into the header. Merges equivalent stores on both sides of a hammock/diamond and sinks it to the footer. Can enable if conversion and tolerate better load misses and store operand latencies. llvm-svn: 213396
* Reapply "DebugInfo: Ensure that all debug location scope chains from ↵David Blaikie2014-07-183-4/+34
| | | | | | | | | | | | | | | | | instructions within a function, lead to the function itself.""" Recommits 212776 which was reverted in r212793. This has been committed and recommitted a few times as I try to test it harder and find/fix more issues. The most recent revert was due to an asan bot failure which I can't seem to reproduce locally, though I believe I'm following all the steps the buildbot does. So I'm going to recommit this in the hopes of investigating the failure on the buildbot itself... apologies in advance for the bot noise. If anyone sees failures with this /please/ provide me with any reproductions, etc. llvm-svn: 213391
* Fix build failure on windowsDavid Peixotto2014-07-182-1/+3
| | | | | | Add explicit constructor to struct instead of using brace initialization. llvm-svn: 213389
* MC: support different sized constants in constant poolsDavid Peixotto2014-07-1810-67/+200
| | | | | | | | | | | | | | | On AArch64 the pseudo instruction ldr <reg>, =... supports both 32-bit and 64-bit constants. Add support for 64 bit constants for the pools to support the pseudo instruction fully. Changes the AArch64 ldr-pseudo tests to use 32-bit registers and adds tests with 64-bit registers. Patch by Janne Grunau! Differential Revision: http://reviews.llvm.org/D4279 llvm-svn: 213387
* Add a dereferenceable attributeHal Finkel2014-07-1822-18/+388
| | | | | | | | | This attribute indicates that the parameter or return pointer is dereferenceable. Practically speaking, loads from such a pointer within the associated byte range are safe to speculatively execute. Such pointer parameters are common in source languages (C++ references, for example). llvm-svn: 213385
* Add MIPS Technologies to the vendors in llvm::Triple.Daniel Sanders2014-07-182-0/+3
| | | | | | | | This is a prerequisite for checking for 'mti' and 'img' in a consistent way in clang. Previously 'img' could use Triple::getVendor() but 'mti' could only use Triple::getVendorName(). llvm-svn: 213381
* AArch64: implement efficient f16 bitcastsTim Northover2014-07-182-0/+64
| | | | | | | | Because i16 is illegal, there's no native DAG method to represent a bitcast to or from an f16 type. This meant LLVM was inserting a stack store/load pair which is really not ideal. llvm-svn: 213378
* NVPTX: support fpext/fptrunc to and from f16.Tim Northover2014-07-182-0/+43
| | | | llvm-svn: 213377
* R600: support fpext/fptrunc operations to and from f16.Tim Northover2014-07-182-0/+35
| | | | llvm-svn: 213376
* AArch64: support f16 extend/trunc operations.Tim Northover2014-07-182-0/+37
| | | | llvm-svn: 213375
* X86: support fpext/fptrunc operations to and from 16-bit floats.Tim Northover2014-07-182-0/+47
| | | | llvm-svn: 213374
* ARM: support legalisation of "fptrunc ... to half" operations.Tim Northover2014-07-184-4/+80
| | | | llvm-svn: 213373
* CodeGen: soften f16 type by default instead of marking legal.Tim Northover2014-07-187-1/+147
| | | | | | | | | | | | Actual support for softening f16 operations is still limited, and can be added when it's needed. But Soften is much closer to being a useful thing to try than keeping it Legal when no registers can actually hold such values. Longer term, we probably want something between Soften and Promote semantics for most targets, it'll be more efficient to promote the 4 basic operations to f32 than libcall them. llvm-svn: 213372
* Suppress 'not handled in switch' warningRenato Golin2014-07-181-0/+2
| | | | llvm-svn: 213371
* [ARM] Add earlyclobber constraint to pre/post-indexed ARM STR instructions.Tilmann Scheller2014-07-182-4/+19
| | | | | | | | | | The post-indexed instructions were missing the constraint, causing unpredictable STR instructions to be emitted. The earlyclobber constraint on the pre-indexed STR instructions is not strictly necessary, as the instruction selection for pre-indexed STR instructions goes through an additional layer of pseudo instructions which have the constraint defined, however it doesn't hurt to specify the constraint directly on the pre-indexed instructions as well, since at some point someone might create instances of them programmatically and then the constraint is definitely needed. This fixes PR20323. llvm-svn: 213369
* Refactor ARM subarchitecture parsingRenato Golin2014-07-183-82/+120
| | | | | | | | | Re-commit of a patch to rework the triple parsing on ARM to a more sane model. Patch by Gabor Ballabas. llvm-svn: 213367
* extracting swapStruct into include/llvm/Support/MachO.h (no functional change)Artyom Skrobov2014-07-182-208/+216
| | | | llvm-svn: 213361
* R600: rename misleading fp16 test.Tim Northover2014-07-181-2/+2
| | | | | | | This test is actually going in the opposite direction to what the filename and function name suggested. llvm-svn: 213358
* R600: support f16 -> f64 conversion intrinsic.Tim Northover2014-07-182-0/+16
| | | | | | | | Unfortunately, we don't seem to have a direct truncation, but the extension can be legally split into two operations so we should support that. llvm-svn: 213357
* NVPTX: support direct f16 <-> f64 conversions via intrinsics.Tim Northover2014-07-182-0/+50
| | | | | | | | Clang may well start emitting these soon, and while it may not be directly relevant for OpenCL or GLSL, the instructions were just sitting there waiting to be used. llvm-svn: 213356
* Rename AlignAttribute to IntAttributeHal Finkel2014-07-185-29/+29
| | | | | | | | | | | | Currently the only kind of integer IR attributes that we have are alignment attributes, and so the attribute kind that takes an integer parameter is called AlignAttr, but that will change (we'll soon be adding a dereferenceable attribute that also takes an integer value). Accordingly, rename AlignAttribute to IntAttribute (class names, enums, etc.). No functionality change intended. llvm-svn: 213352
* R600: Implement TTI:getPopcntSupportMatt Arsenault2014-07-184-2/+119
| | | | | | | The test is just copied from X86, and I don't know of a better way to test it. llvm-svn: 213351
* X86: Constant fold converting vector setcc results to float.Jim Grosbach2014-07-182-0/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the result of a SETCC for X86 is 0 or -1 in each lane, we can move unary operations, in this case [su]int_to_fp through the mask operation and constant fold the operation away. Generally speaking: UNARYOP(AND(VECTOR_CMP(x,y), constant)) --> AND(VECTOR_CMP(x,y), constant2) where constant2 is UNARYOP(constant). This implements the transform where UNARYOP is [su]int_to_fp. For example, consider the simple function: define <4 x float> @foo(<4 x float> %val, <4 x float> %test) nounwind { %cmp = fcmp oeq <4 x float> %val, %test %ext = zext <4 x i1> %cmp to <4 x i32> %result = sitofp <4 x i32> %ext to <4 x float> ret <4 x float> %result } Before this change, the SSE code is generated as: LCPI0_0: .long 1 ## 0x1 .long 1 ## 0x1 .long 1 ## 0x1 .long 1 ## 0x1 .section __TEXT,__text,regular,pure_instructions .globl _foo .align 4, 0x90 _foo: ## @foo cmpeqps %xmm1, %xmm0 andps LCPI0_0(%rip), %xmm0 cvtdq2ps %xmm0, %xmm0 retq After, the code is improved to: LCPI0_0: .long 1065353216 ## float 1.000000e+00 .long 1065353216 ## float 1.000000e+00 .long 1065353216 ## float 1.000000e+00 .long 1065353216 ## float 1.000000e+00 .section __TEXT,__text,regular,pure_instructions .globl _foo .align 4, 0x90 _foo: ## @foo cmpeqps %xmm1, %xmm0 andps LCPI0_0(%rip), %xmm0 retq The cvtdq2ps has been constant folded away and the floating point 1.0f vector lanes are materialized directly via the ModRM operand of andps. llvm-svn: 213342
* AArch64: Constant fold converting vector setcc results to float.Jim Grosbach2014-07-183-0/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the result of a SETCC for AArch64 is 0 or -1 in each lane, we can move unary operations, in this case [su]int_to_fp through the mask operation and constant fold the operation away. Generally speaking: UNARYOP(AND(VECTOR_CMP(x,y), constant)) --> AND(VECTOR_CMP(x,y), constant2) where constant2 is UNARYOP(constant). This implements the transform where UNARYOP is [su]int_to_fp. For example, consider the simple function: define <4 x float> @foo(<4 x float> %val, <4 x float> %test) nounwind { %cmp = fcmp oeq <4 x float> %val, %test %ext = zext <4 x i1> %cmp to <4 x i32> %result = sitofp <4 x i32> %ext to <4 x float> ret <4 x float> %result } Before this change, the code is generated as: fcmeq.4s v0, v0, v1 movi.4s v1, #0x1 // Integer splat value. and.16b v0, v0, v1 // Mask lanes based on the comparison. scvtf.4s v0, v0 // Convert each lane to f32. ret After, the code is improved to: fcmeq.4s v0, v0, v1 fmov.4s v1, #1.00000000 // f32 splat value. and.16b v0, v0, v1 // Mask lanes based on the comparison. ret The svvtf.4s has been constant folded away and the floating point 1.0f vector lanes are materialized directly via fmov.4s. Rather than do the folding manually in the target code, teach getNode() in the generic SelectionDAG to handle folding constant operands of vector [su]int_to_fp nodes. It is reasonable (as noted in a FIXME) to do additional constant folding there as well, but I don't have test cases for those operations, so leaving them for another time when it becomes appropriate. rdar://17693791 llvm-svn: 213341
* Revert "[x86] Fold extract_vector_elt of a load into the Load's address ↵Michael J. Spencer2014-07-182-143/+91
| | | | | | | | | computation." There's a bug where this can create cycles in the DAG. It will take a bit to fix, so I'm backing it out for now. llvm-svn: 213339
* Reset the Subtarget in the AsmPrinter for each machine functionEric Christopher2014-07-182-6/+11
| | | | | | | and add explanatory comment about dual initialization. Fix use of the Subtarget to grab the information off of the target machine. llvm-svn: 213336
* Avoid resetting the UseSoftFloat and FloatABIType on the TargetMachineEric Christopher2014-07-187-18/+15
| | | | | | | | | | Options struct and move the comment to inMips16HardFloat. Use the fact that we now know whether or not we cared about soft float to set the libcalls. Accordingly rename mipsSEUsesSoftFloat to abiUsesSoftFloat and propagate since it's no longer CPU specific. llvm-svn: 213335
* [MCJIT] Fix the alignment requirements for ARM and AArch64 which were mistakenlyLang Hames2014-07-172-2/+2
| | | | | | | | | | relaxed in the big RuntimeDyldMachO cleanup of r213293. No test case yet - this was found via inspection and there's no easy way to test GOT alignment in RuntimeDyldChecker at the moment. I'm working on adding support for this now, and hope to have a test case for this soon. llvm-svn: 213331
* Tweak formating to match what clang-format would be for llvm-nm.cpp .Kevin Enderby2014-07-171-3/+2
| | | | | | No functional change. llvm-svn: 213330
* Add printing of Mach-O stabs in llvm-nm.Kevin Enderby2014-07-174-2/+103
| | | | llvm-svn: 213327
* Remove rules against std::function from the programmer's manualReid Kleckner2014-07-171-12/+8
| | | | | | Clarify that llvm::function_ref is like StringRef for callables. llvm-svn: 213326
* ms inline asm: Don't add x86 segment registers to the clobber list.Nico Weber2014-07-173-1/+10
| | | | | | | Clang tries to check the clobber list but doesn't list segment registers in its x86 register list. This fixes PR20343. llvm-svn: 213303
* Make myself code owner of MCJIT.Lang Hames2014-07-171-2/+2
| | | | llvm-svn: 213302
* Drop the udis86 wrapper from llvm::sysAlp Toker2014-07-178-155/+0
| | | | | | | | This optional dependency on the udis86 library was added some time back to aid JIT development, but doesn't make much sense to link into LLVM binaries these days. llvm-svn: 213300
* TableGen: Add 'static' to a large array to avoid a huge stack allocationReid Kleckner2014-07-171-1/+1
| | | | | | | | Speculative fix for a -Wframe-larger-than warning from gcc. Clang will implicitly promote such constant arrays to globals, so in theory it won't hit this. llvm-svn: 213298
* [AArch64] Cleanup AsmParser: no need to use dyn_cast + assert. cast does it ↵Arnaud A. de Grandmaison2014-07-171-41/+21
| | | | | | for us. llvm-svn: 213296
* Rectify r213231. Use proper version of 'ComputeNumSignBits'.Suyog Sarda2014-07-171-1/+1
| | | | | | | | | Earlier when the code was in InstCombine, we were calling the version of ComputeNumSignBits in InstCombine.h that automatically added the DataLayout* before calling into ValueTracking. When the code moved to InstSimplify, we are calling into ValueTracking directly without passing in the DataLayout*. This patch rectifies the same by passing DataLayout in ComputeNumSignBits. llvm-svn: 213295
* [MCJIT] Significantly refactor the RuntimeDyldMachO class.Lang Hames2014-07-177-826/+1097
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The previous implementation of RuntimeDyldMachO mixed logic for all targets within a single class, creating problems for readability, maintainability, and performance. To address these issues, this patch strips the RuntimeDyldMachO class down to just target-independent functionality, and moves all target-specific functionality into target-specific subclasses RuntimeDyldMachO. The new class hierarchy is as follows: class RuntimeDyldMachO Implemented in RuntimeDyldMachO.{h,cpp} Contains logic that is completely independent of the target. This consists mostly of MachO helper utilities which the derived classes use to get their work done. template <typename Impl> class RuntimeDyldMachOCRTPBase<Impl> : public RuntimeDyldMachO Implemented in RuntimeDyldMachO.h Contains generic MachO algorithms/data structures that defer to the Impl class for target-specific behaviors. RuntimeDyldMachOARM : public RuntimeDyldMachOCRTPBase<RuntimeDyldMachOARM> RuntimeDyldMachOARM64 : public RuntimeDyldMachOCRTPBase<RuntimeDyldMachOARM64> RuntimeDyldMachOI386 : public RuntimeDyldMachOCRTPBase<RuntimeDyldMachOI386> RuntimeDyldMachOX86_64 : public RuntimeDyldMachOCRTPBase<RuntimeDyldMachOX86_64> Implemented in their respective *.h files in lib/ExecutionEngine/RuntimeDyld/MachOTargets Each of these contains the relocation logic specific to their target architecture. llvm-svn: 213293
* [ASan] Don't instrument load/stores with !nosanitize metadata.Alexey Samsonov2014-07-172-0/+55
| | | | | | | | | This is used to avoid instrumentation of instructions added by UBSan in Clang frontend (see r213291). This fixes PR20085. Reviewed in http://reviews.llvm.org/D4544. llvm-svn: 213292
* Typo: exists -> exitsHans Wennborg2014-07-171-1/+1
| | | | llvm-svn: 213290
* [NVPTX] Improve handling of FP fusionJustin Holewinski2014-07-1710-53/+103
| | | | | | | | | We now consider the FPOpFusion flag when determining whether to fuse ops. We also explicitly emit add.rn when fusion is disabled to prevent ptxas from fusing the operations on its own. llvm-svn: 213287
* Fix typosMatt Arsenault2014-07-172-4/+4
| | | | llvm-svn: 213285
* [BUG] Due to a typo introduced in r199933 and r200027 two tests for FMA ↵Zinovy Nis2014-07-171-4/+4
| | | | | | were never even started. llvm-svn: 213283
* [X86] AVX512: Add disassembler support for compressed displacementAdam Nemet2014-07-176-5/+80
| | | | | | | | | | | | There are two parts here. First is to modify tablegen to adjust the encoding type ENCODING_RM with the scaling factor. The second is to use the new encoding types to compute the correct displacement in the decoder. Fixes <rdar://problem/17608489> llvm-svn: 213281
* [X86] AVX512: Rename EVEX_CD8V to CD8_FormAdam Nemet2014-07-171-5/+5
| | | | | | | | This is to match the naming of CD8_EltSize, CD8_Scale, etc. No functional change. llvm-svn: 213280
* [X86] AVX512: Use the TD version of CD8_Scale in the assemblerAdam Nemet2014-07-173-62/+16
| | | | | | | | | | | Passes the computed scaling factor in TSFlags rather than the old attributes. Also removes the C++ version of computing the scaling factor (MemObjSize) along with the asserts added by the previous patch. No functional change. llvm-svn: 213279
* [X86] AVX512: Move compressed displacement logic to TDAdam Nemet2014-07-172-0/+34
| | | | | | | | | | | | | | | This does not actually move the logic yet but reimplements it in the Tablegen language. Then asserts that the new implementation results in the same value. The next patch will remove the assert and the temporary use of the TSFlags and remove the C++ implementation. The formula requires a limited form of the logical left and right operators. I implemented these with the bit-extract/insert operator (i.e. blah{bits}). No functional change. llvm-svn: 213278
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