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* [tablegen] Handle common load/store predicates inside tablegen. NFC.Daniel Sanders2017-10-154-179/+533
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: GlobalISel and SelectionDAG require different code for the common load/store predicates due to differences in the representation. For example: SelectionDAG: (load<signext,i8>:i32 GPR32:$addr) // The <> denote properties of the SDNode that are not printed in the DAG GlobalISel: (G_SEXT:s32 (G_LOAD:s8 GPR32:$addr)) Even without that, differences in the IR (SDNode vs MachineInstr) require differences in the C++ predicate. This patch moves the implementation of the common load/store predicates into tablegen so that it can handle these differences. It's NFC for SelectionDAG since it emits equivalent code and it's NFC for GlobalISel since the rules involving the relevant predicates are still rejected by the importer. Depends on D36618 Reviewers: ab, qcolombet, t.p.northover, rovka, aditya_nandakumar Subscribers: llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D37443 Includes a partial revert of r315826 since this patch makes it necessary for getPredCode() to return a std::string and getImmCode() should have the same interface as getPredCode(). llvm-svn: 315841
* [Hexagon] Mark RangeTree::dump() with LLVM_DUMP_METHOD.Davide Italiano2017-10-141-1/+1
| | | | | | | GCC otherwise emits a "defined but not used" warning on the member function. llvm-svn: 315838
* AMDGPU: Temporary disable pal metadata check line in llvm-readobj testKonstantin Zhuravlyov2017-10-141-1/+2
| | | | | | It fails on mips llvm-svn: 315837
* AMDGPU: Don't use TargetStreamer if it has not been initializedKonstantin Zhuravlyov2017-10-142-10/+16
| | | | | | | | | | Fixes cfe/trunk/test/Misc/backend-resource-limit-diagnostics.cl test after r315808 We may hit few other similar issues, but I want to discuss good solution offline. llvm-svn: 315830
* [X86] Remove a bunch of dead FileCheck lines with the wrong prefix.Craig Topper2017-10-141-1105/+0
| | | | llvm-svn: 315828
* [TableGen] Avoid unnecessary std::string creationsSimon Pilgrim2017-10-143-19/+18
| | | | | | Avoid unnecessary std::string creations in the TreePredicateFn getters. llvm-svn: 315826
* [X86][SSE] Don't attempt to reduce the imul vector width of odd sized ↵Simon Pilgrim2017-10-142-1/+109
| | | | | | vectors (PR34947) llvm-svn: 315825
* [X86][SSE] Test vector imul reduction on 32 and 64-bit targetsSimon Pilgrim2017-10-141-358/+846
| | | | llvm-svn: 315824
* Revert "[AArch64][RegisterBankInfo] Use the statically computed mappings for ↵Bruno Cardoso Lopes2017-10-141-32/+4
| | | | | | | | | COPY" This reverts commit r315781, breaks: http://green.lab.llvm.org/green/job/Compiler_Verifiers_GlobalISEL/9882 llvm-svn: 315823
* AMDGPU: Add AMDGPU HSA Kernel DescriptorKonstantin Zhuravlyov2017-10-142-91/+252
| | | | | | | | | | - Update docs to match llvm coding style - Add missing FP16_OVFL bit for gfx9 - Fix the size of the kernel descriptor in the docs Differential Revision: https://reviews.llvm.org/D38902 llvm-svn: 315822
* AMDGPU: Bring HSA metadata on par with the specificationKonstantin Zhuravlyov2017-10-1419-337/+428
| | | | | | Differential Revision: https://reviews.llvm.org/D38753 llvm-svn: 315821
* llvm-readobj: Print AMDGPU note contentsKonstantin Zhuravlyov2017-10-1412-68/+69
| | | | | | Differential Revision: https://reviews.llvm.org/D38752 llvm-svn: 315819
* Pull out repeated calls to VT.getVectorNumElements(). NFCI.Simon Pilgrim2017-10-141-10/+11
| | | | llvm-svn: 315818
* Cleanup update_llc_test_checks.py notes.Simon Pilgrim2017-10-145-5/+2
| | | | llvm-svn: 315817
* AMDGPU: Cleanup elf-notes.ll testKonstantin Zhuravlyov2017-10-141-26/+25
| | | | llvm-svn: 315816
* Use DAG::getBitcast() helper. NFCI.Simon Pilgrim2017-10-141-4/+4
| | | | llvm-svn: 315815
* llvm-readobj: Print AMDGPU note type namesKonstantin Zhuravlyov2017-10-143-8/+61
| | | | | | Differential Revision: https://reviews.llvm.org/D38751 llvm-svn: 315813
* AMDGPU: Improve note directive verification in assemblerKonstantin Zhuravlyov2017-10-143-1/+36
| | | | | | | | | | - Do not allow amd_amdgpu_isa directives on non-amdgcn architectures - Do not allow amd_amdgpu_hsa_metadata on non-amdhsa OSes - Do not allow amd_amdgpu_pal_metadata on non-amdpal OSes Differential Revision: https://reviews.llvm.org/D38750 llvm-svn: 315812
* AMDGPU: Do not emit deprecated notes for code object v3Konstantin Zhuravlyov2017-10-149-21/+58
| | | | | | Differential Revision: https://reviews.llvm.org/D38749 llvm-svn: 315810
* AMDGPU: Add support for isa version noteKonstantin Zhuravlyov2017-10-1410-10/+163
| | | | | | | | | | - Emit NT_AMD_AMDGPU_ISA - Add assembler parsing for isa version directive - If isa version directive does not match command line arguments, then return error Differential Revision: https://reviews.llvm.org/D38748 llvm-svn: 315808
* [X86][SSE] Support combining AND(EXTRACT(SHUF(X)), C) -> EXTRACT(SHUF(X))Simon Pilgrim2017-10-142-16/+47
| | | | | | | | If we are applying a byte mask to a value extracted from a shuffle, see if we can combine the mask into shuffle. Fixes the last issue with PR22415 llvm-svn: 315807
* [X86] Add patterns for vzmovl+cvtpd2dq/cvttpd2dq with a load.Craig Topper2017-10-143-13/+83
| | | | llvm-svn: 315802
* [X86] Add AVX512 versions of VCVTPD2PS to load folding tables.Craig Topper2017-10-143-0/+27
| | | | llvm-svn: 315801
* [X86] Add patterns for vzmovl+cvtpd2ps with a load.Craig Topper2017-10-143-24/+60
| | | | llvm-svn: 315800
* [X86] Remove some patterns for bitcasted alignednonedtemporalloads.Craig Topper2017-10-141-18/+0
| | | | | | These select the same instruction as the non-bitcasted pattern. So this provides no additional value. llvm-svn: 315799
* [X86] Remove unnecessary bitconverts as the root of patterns for zero ↵Craig Topper2017-10-141-4/+4
| | | | | | | | extended VCVTPD2UDQZ128rr and VCVTTPD2UDQZ128rr. We don't need a bitconvert as a root pattern in these cases. The types in the other parts of the pattern are sufficient to express the behavior of these instructions. llvm-svn: 315798
* [X86] Add additional patterns for folding loads with 128-bit VCVTDQ2PD and ↵Craig Topper2017-10-141-0/+10
| | | | | | | | | | VCVTUDQ2PD. This matches the patterns we have for the SSE/AVX version. This is a prerequisite for D38714. llvm-svn: 315797
* [X86] Add AVX512 flavors of VCVTDQ2PD plus VCVTUDQ2PD to the load folding ↵Craig Topper2017-10-143-0/+56
| | | | | | tables. llvm-svn: 315796
* [X86] Remove TB_NO_REVERSE from VCVTDQ2PDYrr and VCVTPS2PDYrr in the load ↵Craig Topper2017-10-141-2/+2
| | | | | | | | folding tables. I believe these were added incorrectly under the belief that the load size was smaller than the input register size, but that's not true. llvm-svn: 315795
* [X86] Add an additional isel pattern to CVTDQ2PDrm/VCVTDQ2PDrm to enable ↵Craig Topper2017-10-141-2/+6
| | | | | | | | load folding without the peephole pass. This pattern is already used in AVX512VL version of these instructions. Though AVX512VL version is missing other patterns. llvm-svn: 315794
* Revert "lit.py: Add new %{shared_output(LABEL)} substitution"Jordan Rose2017-10-149-56/+11
| | | | | | | This reverts r315697 and my ill-fated attempts to fix it on Windows. I'll try again when I get access to a Windows machine. llvm-svn: 315793
* lit.py: Give up and disable the new shared-output.py test on WindowsJordan Rose2017-10-141-0/+3
| | | | | | | | | | "No such file or directory: C:\\...\\tests\\Output\\shared-output.py.tmp/Output/Shared/SHARED.tmp" And yet other forward-slashes don't seem to be causing the same problem. I'll see if I can get ahold of a Windows machine to poke at this directly later. llvm-svn: 315792
* Fix assembler for alloca of multiple elements in non-zero addr spaceYaxun Liu2017-10-142-5/+41
| | | | | | | | | | | | | Currently llvm assembler emits parsing error for valid IR assembly alloca i32, i32 9, addrspace(5) when alloca addr space is 5. This patch fixes that. Differential Revision: https://reviews.llvm.org/D38713 llvm-svn: 315791
* [Dominators] Remove the NCA checkJakub Kuderski2017-10-141-37/+2
| | | | | | | | | | | | | | | | | | Summary: This patch removes the `verifyNCD` check. The reason for this is that the other checks are sufficient to prove or disprove correctness of any DominatorTree, and that `verifyNCD` doesn't provide (in my option) better error messages then the other ones. Additionally, this should give a (small) improvement to the total verification time, as the check is O(n), and checking the sibling property takes O(n^3). Reviewers: dberlin, grosser, davide, brzycki Reviewed By: brzycki Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38802 llvm-svn: 315790
* [llvm-cov] Factor out logic to iterate over line coverage stats (NFC)Vedant Kumar2017-10-145-50/+121
| | | | | | | | | | There were two copies of the logic needed to construct a line stats object for each line in a range: this patch brings it down to one. In the future, this will make it easier for IDE clients to display coverage in-line in source editors. To do that, we just need to move the new LineCoverageIterator class to libCoverage. llvm-svn: 315789
* [globalisel][tablegen] Fix an unused variable warning caused by a typo ↵Daniel Sanders2017-10-141-1/+1
| | | | | | | | (corrected OtherInsnID->OtherOpIdx). The tests were passing by luck since the instruction ID and operand index happened to be the same. llvm-svn: 315788
* [globalisel][tablegen] Fix undefined references to dump()Daniel Sanders2017-10-141-2/+0
| | | | | | Two debugging statements snuck into the commit. llvm-svn: 315783
* lit.py: Previous test fix was a red herring; backslashes are escapesJordan Rose2017-10-141-1/+1
| | | | | | | I don't have access to a Windows machine at the moment, so if this doesn't fix it I'll just revert for now. llvm-svn: 315782
* [AArch64][RegisterBankInfo] Use the statically computed mappings for COPYQuentin Colombet2017-10-141-4/+32
| | | | | | | | | | | | | | | | | | | | We use to resort on the generic implementation to get the mappings for COPYs. The generic implementation resorts on table lookup and dynamically allocated objects to get the valid mappings. Given we already know how to map G_BITCAST and have the static mappings for them, use that code path for COPY as well. This is much more efficient. Improve the compile time of RegBankSelect by up to 20%. Note: When we eventually generate all the mappings via TableGen, we wouldn't have to do that dance to shave compile time. The intent of this change was to make sure that moving to static structure really pays off. NFC. llvm-svn: 315781
* [globalisel][tablegen] Simplify named operand/operator lookups and fix a ↵Daniel Sanders2017-10-145-108/+274
| | | | | | | | | | | | | | | | | | | | | | wrong-code bug this revealed. Summary: Operand variable lookups are now performed by the RuleMatcher rather than searching the whole matcher hierarchy for a match. This revealed a wrong-code bug that currently affects ARM and X86 where patterns that use a variable more than once in the match pattern will be imported but won't check that the operands are identical. This can cause the tablegen-erated matcher to accept matches that should be rejected. Depends on D36569 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Subscribers: aemerson, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D36618 llvm-svn: 315780
* lit.py: Fix new test harder for systems that don't use / as os.path.sepJordan Rose2017-10-141-1/+1
| | | | | | | I didn't think about '%{inputs}' having the same problem. This one should be a fully Windows path name. llvm-svn: 315779
* lit.py: Fix new test for systems that don't use / as os.path.sepJordan Rose2017-10-131-1/+1
| | | | llvm-svn: 315773
* Revert r315763: "[Hexagon] Rangify some loops, NFC"Krzysztof Parzyszek2017-10-132-26/+44
| | | | | | Broke some builds (using libstdc++). llvm-svn: 315769
* [X86] Use X86ISD::VBROADCAST in place of v2f64 X86ISD::MOVDDUP when AVX2 is ↵Craig Topper2017-10-134-18/+55
| | | | | | | | | | | | | | | | available This is particularly important for AVX512VL where we are better able to recognize the VBROADCAST loads to fold with other operations. For AVX512VL we now use X86ISD::VBROADCAST for all of the patterns and remove the 128-bit X86ISD::VMOVDDUP. We may be able to use this for AVX1 as well which would allow us to remove more isel patterns. I also had to add X86ISD::VBROADCAST as a node to call combineShuffle for so that we treat it similar to X86ISD::MOVDDUP. Differential Revision: https://reviews.llvm.org/D38836 llvm-svn: 315768
* [X86] Use fsub in the movddup scheduling tests to prevent a future patch ↵Craig Topper2017-10-131-10/+10
| | | | | | from folding movddup as a broadcast load. llvm-svn: 315767
* [globalisel][tablegen] Fix a use-after free bug that manifests on non-macOS ↵Daniel Sanders2017-10-131-1/+1
| | | | | | machines. llvm-svn: 315765
* [Hexagon] Rangify some loops, NFCKrzysztof Parzyszek2017-10-132-44/+26
| | | | llvm-svn: 315763
* [InstCombine] use m_Neg() to reduce code; NFCISanjay Patel2017-10-131-13/+9
| | | | llvm-svn: 315762
* [globalisel][tablegen] Add support for fpimm and import of APInt/APFloat ↵Daniel Sanders2017-10-1310-45/+279
| | | | | | | | | | | | | | | | | | | | | | based ImmLeaf. Summary: There's only a tablegen testcase for IntImmLeaf and not a CodeGen one because the relevant rules are rejected for other reasons at the moment. On AArch64, it's because there's an SDNodeXForm attached to the operand. On X86, it's because the rule either emits multiple instructions or has another predicate using PatFrag which cannot easily be supported at the same time. Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: qcolombet Subscribers: aemerson, javed.absar, igorb, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D36569 llvm-svn: 315761
* [Transforms] Fix some Clang-tidy modernize and Include What You Use ↵Eugene Zelenko2017-10-1310-148/+344
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 315760
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