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* Make llvm-objdump handle both arm and thumb disassembly from the same Mach-OKevin Enderby2014-08-185-13/+185
| | | | | | | | | | file with -macho, the Mach-O specific object file parser option. After some discussion I chose to do this implementation contained in the logic of llvm-objdump’s MachODump.cpp using a second disassembler for thumb when needed and with updates mostly contained in the MachOObjectFile class. llvm-svn: 215931
* [X86][Haswell][SchedModel] Tidy up.Quentin Colombet2014-08-181-56/+63
| | | | | | <rdar://problem/15607571> llvm-svn: 215924
* [X86][Haswell][SchedModel] Add architecture specific scheduling models.Quentin Colombet2014-08-181-0/+30
| | | | | | | | | Group: Floating Point XMM and YMM instructions. Sub-group: Other instructions. <rdar://problem/15607571> llvm-svn: 215923
* [X86][Haswell][SchedModel] Add architecture specific scheduling models.Quentin Colombet2014-08-181-0/+9
| | | | | | | | | Group: Floating Point XMM and YMM instructions. Sub-group: Logic instructions. <rdar://problem/15607571> llvm-svn: 215922
* [X86][Haswell][SchedModel] Add architecture specific scheduling models.Quentin Colombet2014-08-181-0/+68
| | | | | | | | | Group: Floating Point XMM and YMM instructions. Sub-group: Math instructions. <rdar://problem/15607571> llvm-svn: 215921
* [X86][Haswell][SchedModel] Add architecture specific scheduling models.Quentin Colombet2014-08-181-0/+170
| | | | | | | | | Group: Floating Point XMM and YMM instructions. Sub-group: Arithmetic instructions. <rdar://problem/15607571> llvm-svn: 215920
* [X86][Haswell][SchedModel] Add architecture specific scheduling models.Quentin Colombet2014-08-181-0/+170
| | | | | | | | | Group: Floating Point XMM and YMM instructions. Sub-group: Conversion instructions. <rdar://problem/15607571> llvm-svn: 215919
* [X86][Haswell][SchedModel] Add architecture specific scheduling models.Quentin Colombet2014-08-181-0/+144
| | | | | | | | | Group: Floating Point XMM and YMM instructions. Sub-group: Move instructions. <rdar://problem/15607571> llvm-svn: 215918
* [X86][Haswell][SchedModel] Add architecture specific scheduling models.Quentin Colombet2014-08-181-0/+9
| | | | | | | | | Group: Integer MMX and XMM instructions. Sub-group: Other instructions. <rdar://problem/15607571> llvm-svn: 215917
* [X86][Haswell][SchedModel] Add architecture specific scheduling models.Quentin Colombet2014-08-181-0/+31
| | | | | | | | | Group: Integer MMX and XMM instructions. Sub-group: Logic instructions. <rdar://problem/15607571> llvm-svn: 215916
* [X86][Haswell][SchedModel] Add architecture specific scheduling models.Quentin Colombet2014-08-181-0/+63
| | | | | | | | | Group: Integer MMX and XMM instructions. Sub-group: Arithmetic instructions. <rdar://problem/15607571> llvm-svn: 215915
* [X86][Haswell][SchedModel] Add architecture specific scheduling models.Quentin Colombet2014-08-181-0/+251
| | | | | | | | | Group: Integer MMX and XMM instructions. Sub-group: Move instructions. <rdar://problem/15607571> llvm-svn: 215914
* [X86][Haswell][SchedModel] Add architecture specific scheduling models.Quentin Colombet2014-08-181-0/+16
| | | | | | | | | Group: Floating Point x87 instructions. Sub-group: Math instructions. <rdar://problem/15607571> llvm-svn: 215913
* [X86][Haswell][SchedModel] Add architecture specific scheduling models.Quentin Colombet2014-08-181-0/+70
| | | | | | | | | Group: Floating Point x87 instructions. Sub-group: Arithmetic instructions. <rdar://problem/15607571> llvm-svn: 215912
* [X86][Haswell][SchedModel] Add architecture specific scheduling models.Quentin Colombet2014-08-181-0/+126
| | | | | | | | | Group: Floating Point x87 instructions. Sub-group: Move instructions. <rdar://problem/15607571> llvm-svn: 215911
* [X86][Haswell][SchedModel] Add architecture specific scheduling models.Quentin Colombet2014-08-181-0/+37
| | | | | | | | | Group: Integer instructions. Sub-group: Other instructions. <rdar://problem/15607571> llvm-svn: 215910
* [X86][Haswell][SchedModel] Add architecture specific scheduling models.Quentin Colombet2014-08-181-0/+26
| | | | | | | | | Group: Integer instructions. Sub-group: Synchronization instructions. <rdar://problem/15607571> llvm-svn: 215909
* [X86][Haswell][SchedModel] Add architecture specific scheduling models.Quentin Colombet2014-08-181-0/+42
| | | | | | | | | Group: Integer instructions. Sub-group: String instructions. <rdar://problem/15607571> llvm-svn: 215908
* [X86][Haswell][SchedModel] Add architecture specific scheduling models.Quentin Colombet2014-08-181-0/+60
| | | | | | | | | Group: Integer instructions. Sub-group: Control transfer instructions. <rdar://problem/15607571> llvm-svn: 215907
* [X86][Haswell][SchedModel] Add architecture specific scheduling models.Quentin Colombet2014-08-181-0/+216
| | | | | | | | | Group: Integer instructions. Sub-group: Logic instructions. <rdar://problem/15607571> llvm-svn: 215906
* [X86][Haswell][SchedModel] Add architecture specific scheduling models.Quentin Colombet2014-08-181-0/+192
| | | | | | | | | Group: Integer instructions. Sub-group: Arithmetic instructions. <rdar://problem/15607571> llvm-svn: 215905
* [X86][Haswell][SchedModel] Add architecture specific scheduling models.Quentin Colombet2014-08-181-0/+145
| | | | | | | | | Group: Integer instructions. Sub-group: Move instructions. <rdar://problem/15607571> llvm-svn: 215904
* Make use of isAtLeastRelease/Acquire in the ARM/AArch64 backendsRobin Morisset2014-08-184-15/+10
| | | | | | | | | | | | | | | | | Summary: Make use of isAtLeastRelease/Acquire in the ARM/AArch64 backends These helper functions are introduced in D4844. Depends D4844 Test Plan: make check-all passes Reviewers: jfb Subscribers: aemerson, llvm-commits, mcrosier, reames Differential Revision: http://reviews.llvm.org/D4937 llvm-svn: 215902
* Disabling an MSVC warning ('var' : definition from the for loop is ignored; ↵Aaron Ballman2014-08-181-0/+1
| | | | | | the definition from the enclosing scope is used) which will trigger false positives more than true positives. llvm-svn: 215895
* Teach the AArch64 backend to handle f16Oliver Stannard2014-08-183-0/+121
| | | | | | | This allows the AArch64 backend to handle fadd, fsub, fmul and fdiv operations on f16 (half-precision) types by promoting to f32. llvm-svn: 215891
* [ARM,AArch64] Do not tail-call to an externally-defined function with weak ↵Oliver Stannard2014-08-184-0/+47
| | | | | | | | | | | | | linkage Externally-defined functions with weak linkage should not be tail-called on ARM or AArch64, as the AAELF spec requires normal calls to undefined weak functions to be replaced with a NOP or jump to the next instruction. The behaviour of branch instructions in this situation (as used for tail calls) is implementation-defined, so we cannot rely on the linker replacing the tail call with a return. llvm-svn: 215890
* AVX-512: Fixed a bug in emitting compare for MVT:i1 type.Elena Demikhovsky2014-08-185-12/+44
| | | | | | Added a test. llvm-svn: 215889
* Silencing an MSVC warning about loop variable conflicting with a variable ↵Aaron Ballman2014-08-181-1/+1
| | | | | | from an outer scope. NFC. llvm-svn: 215888
* TableGen: allow use of uint64_t for available features mask.Tim Northover2014-08-1810-62/+64
| | | | | | | | | | ARM in particular is getting dangerously close to exceeding 32 bits worth of possible subtarget features. When this happens, various parts of MC start to fail inexplicably as masks get truncated to "unsigned". Mostly just refactoring at present, and there's probably no way to test. llvm-svn: 215887
* Added forgotten noexcept.Abramo Bagnara2014-08-181-1/+1
| | | | llvm-svn: 215886
* Revert "Repace SmallPtrSet with SmallPtrSetImpl in function arguments to ↵Craig Topper2014-08-1849-114/+114
| | | | | | | | avoid needing to mention the size." Getting a weird buildbot failure that I need to investigate. llvm-svn: 215870
* Repace SmallPtrSet with SmallPtrSetImpl in function arguments to avoid ↵Craig Topper2014-08-1749-114/+114
| | | | | | needing to mention the size. llvm-svn: 215868
* Use copy initialization to initialize std::unique_ptr.Rafael Espindola2014-08-173-3/+3
| | | | | | Thanks to David Blaikie for the suggestion. llvm-svn: 215867
* ARM: mark missing functions from RTABISaleem Abdulrasool2014-08-171-0/+24
| | | | | | | Simply indicate the functions that are part of the runtime library that we do not setup libcalls for. This is merely for ease of identification. NFC. llvm-svn: 215863
* ARM: improve RTABI 4.2 conformance on LinuxSaleem Abdulrasool2014-08-172-58/+38
| | | | | | | | | | | | | | | | The set of functions defined in the RTABI was separated for no real reason. This brings us closer to proper utilisation of the functions defined by the RTABI. It also sets the ground for correctly emitting function calls to AEABI functions on all AEABI conforming platforms. The previously existing lie on the behaviour of __ldivmod and __uldivmod is propagated as it is beyond the scope of the change. The changes to the test are due to the fact that we now use the divmod functions which return both the quotient and remainder and thus we no longer need to invoke two functions on Linux (making it closer to EABI's behaviour). llvm-svn: 215862
* ARM: whitespaceSaleem Abdulrasool2014-08-171-5/+5
| | | | | | Whitespace fix, NFC. llvm-svn: 215861
* Remove unused member variable.Rafael Espindola2014-08-171-10/+7
| | | | llvm-svn: 215860
* Return a std::uinque_ptr. Every caller was already using one.Rafael Espindola2014-08-172-5/+6
| | | | llvm-svn: 215858
* Convert an ownership comment with std::uinque_ptr.Rafael Espindola2014-08-173-20/+13
| | | | llvm-svn: 215855
* Pass a std::uinque_ptr to ParseAssembly to make the ownership explicit. NFC.Rafael Espindola2014-08-173-20/+18
| | | | llvm-svn: 215852
* getLazyIRModule always takes ownership. Make that explicit.Rafael Espindola2014-08-171-10/+9
| | | | llvm-svn: 215851
* Return a std::unique_ptr to make the ownership explicit.Rafael Espindola2014-08-171-3/+3
| | | | llvm-svn: 215850
* Don't repeat the function name in comments. NFC.Rafael Espindola2014-08-171-19/+17
| | | | llvm-svn: 215849
* Don't repeat names in comments. NFC.Rafael Espindola2014-08-171-13/+13
| | | | llvm-svn: 215848
* Revert: r215698 - Current implementation of c.cond.fmt instructions only ↵Daniel Sanders2014-08-1714-234/+197
| | | | | | | | | | | accept default cc0 register... It causes a number of regressions when -fintegrated-as is enabled. This happens because there are codegen-only instructions that incorrectly uses the first operand as the encoding for the $fcc register. The regressions do not occur when -via-file-asm is also given. llvm-svn: 215847
* ARM: correct toggling behaviourSaleem Abdulrasool2014-08-172-8/+14
| | | | | | | | | | This was a thinko. The intent was to flip the explicit bits that need toggling rather than all bits. This would result in incorrect behaviour (which now is tested). Thanks to Nico Weber for pointing this out! llvm-svn: 215846
* llvm-objdump: don't print relocations in non-relocatable files.Rafael Espindola2014-08-178-0/+31
| | | | | | This matches the behavior of GNU objdump. llvm-svn: 215844
* Remove a redundant "public:". NFC.Rafael Espindola2014-08-171-1/+0
| | | | llvm-svn: 215842
* BumpPtrAllocator: remove 'no slabs allocated yet' checkHans Wennborg2014-08-172-4/+1
| | | | | | | | | | We already handle the no-slabs case when checking whether the current slab is large enough: if no slabs have been allocated, CurPtr and End are both 0. alignPtr(0), will still be 0, and so "if (Ptr + Size <= End)" fails. Differential Revision: http://reviews.llvm.org/D4943 llvm-svn: 215841
* Add a non-templated ELFObjectFileBase class.Rafael Espindola2014-08-172-63/+42
| | | | | | | Use it to implement some ELF only virtual interfaces instead of using error prone series of dyn_casts. llvm-svn: 215838
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