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* ARM: improve instruction validation for thumb modeSaleem Abdulrasool2014-12-184-29/+177
| | | | | | | | | | | | | | | | | | | | | | | | | The ARM Architecture Reference Manual states the following: LDM{,IA,DB}: The SP cannot be in the list. The PC can be in the list. If the PC is in the list: • the LR must not be in the list • the instruction must be either outside any IT block, or the last instruction in an IT block. POP: The PC can be in the list. If the PC is in the list: • the LR must not be in the list • the instruction must be either outside any IT block, or the last instruction in an IT block. PUSH: The SP and PC can be in the list in ARM instructions, but not in Thumb instructions. STM:{,IA,DB}: The SP and PC can be in the list in ARM instructions, but not in Thumb instructions. llvm-svn: 224502
* test: avoid unnecessary temporary filesSaleem Abdulrasool2014-12-181-8/+8
| | | | | | Use pipes and redirect the error output to FileCheck directly. NFC. llvm-svn: 224501
* [SROA] Cleanup - remove the use of std::mem_fun_ref nonsense and useChandler Carruth2014-12-181-1/+3
| | | | | | a lambda now that we have them. llvm-svn: 224500
* Modernize the getStreamedBitcodeModule interface a bit. NFC.Rafael Espindola2014-12-184-33/+29
| | | | llvm-svn: 224499
* [PowerPC] Use MCPhysReg for tables of registers. Const-correct the tables. ↵Craig Topper2014-12-181-12/+12
| | | | | | Only put the anonymous namespace around classes. NFC. llvm-svn: 224498
* [X86] Use correct opsize on indirect call and jump aliases.Craig Topper2014-12-181-4/+4
| | | | llvm-svn: 224497
* [X86] Don't use PS prefix on LDMXCSR/STMXCSR.Craig Topper2014-12-181-6/+8
| | | | | | Near as I can tell prefixes are ignored on these instructions except for a comment in the Intel docs about 0xf3. Binutils disassembler seems to ignore prefixes on these instructions. Our disassembler still doesn't distinguish PS and "no prefix" well enough for this to make a functional change, but it helps with experiments I'm doing on a potential new disassembler table builder. llvm-svn: 224496
* [X86] Remove unnecessary 'In64BitMode' predicate for instructions that ↵Craig Topper2014-12-181-14/+11
| | | | | | already indicate use of REX.W. llvm-svn: 224495
* Add a corresponding '@LOCAL' parse to match r224415.Justin Hibbits2014-12-181-0/+1
| | | | | | Pointed out by Jim Grosbach. llvm-svn: 224494
* Add a new string member to the TargetOptions struct for the nameEric Christopher2014-12-1813-71/+107
| | | | | | | | | | | | | of the abi we should be using. For targets that don't use the option there's no change, otherwise this allows external users to set the ABI via string and avoid some of the -backend-option pain in clang. Use this option to move the ABI for the ARM port from the Subtarget to the TargetMachine and update the testcases accordingly since it's no longer valid to set via -mattr. llvm-svn: 224492
* Model ARM backend ABI selection after the front end code doing theEric Christopher2014-12-186-25/+42
| | | | | | | | | | | | | | same. This will change the "bare metal" ABI from APCS to AAPCS. The only difference between the front and back end code is that the code for Triple::GNU was added for environment. That will migrate to the front end shortly. Tests updated with the ABI they were originally testing in the case of bare metal (e.g. -mtriple armv7) or with a -gnu for arm-linux triples. llvm-svn: 224489
* Reapply "Linker: Drop superseded subprograms"Duncan P. N. Exon Smith2014-12-183-0/+156
| | | | | | | | | | | | | | | | | | | | This reverts commit r224416, reapplying r224389. The buildbots hadn't recovered after my revert, waiting until David reverted a couple of his commits. It looks like it was just bad timing (where we were both modifying code related to the same assertion). Trying again... Here's the original text: When a function gets replaced by `ModuleLinker`, drop superseded subprograms. This ensures that the "first" subprogram pointing at a function is the same one that `!dbg` references point at. This is a stop-gap fix for PR21910. Notably, this fixes Release+Asserts bootstraps that are currently asserting out in `LexicalScopes::initialize()` due to the explicit instantiations in `lib/IR/Dominators.cpp` eventually getting replaced by -argpromotion. llvm-svn: 224487
* IR: Make DICompositeType mutators privateDuncan P. N. Exon Smith2014-12-181-0/+8
| | | | | | | | | | | Make `DICompositeType` mutators private to prevent misuse. All calls to `setArrays()` and `setContainingType()` should go through `DIBuilder::replaceArrays()` and `DIBuilder::replaceVTableHolder()`. This is a follow-up to r224482 (now that clang has been updated in r224483). llvm-svn: 224486
* Add printing the LC_LINKER_OPTION load command with llvm-objdump’s ↵Kevin Enderby2014-12-188-15/+61
| | | | | | | | | | -private-headers. Also corrected the name of the load command to not end in an ’S’ as well as corrected the name of the MachO::linker_option_command struct and other places that had the word option as plural which did not match the Mac OS X headers. llvm-svn: 224485
* IR: Handle self-referencing DICompositeTypes in DIBuilderDuncan P. N. Exon Smith2014-12-182-0/+46
| | | | | | | | | | | | | | | | | | | | Add API to DIBuilder to handle self-referencing `DICompositeType`s. Self-references aren't expected in the debug info graph, and we take advantage of that by only calling `resolveCycles()` on nodes that were once forward declarations (otherwise, DIBuilder needs an expensive tracking reference to every unresolved node it creates, which in cyclic graphs is *all of them*). However, clang seems to create self-referencing `DICompositeType`s. Add API to manage this safely. The paired commit to clang will include the regression test. I'll make the `DICompositeType` API `private` in a follow-up to prevent misuse (I've separated that to prevent build failures from missing the clang commit). llvm-svn: 224482
* [dsymutil] Fix missing member initializer.Alexey Samsonov2014-12-181-1/+2
| | | | | | | This bug was found by the MSan bootstrap bot: http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-bootstrap/builds/5330/steps/check-llvm%20msan/logs/stdio llvm-svn: 224481
* LTO: Lazy-load LTOModule in local contextsDuncan P. N. Exon Smith2014-12-171-7/+23
| | | | | | | | | | | | | | | | | | | | | | | | | Start lazy-loading `LTOModule`s that own their contexts. These can only really be used for parsing symbols, so its unnecessary to ever materialize their functions. I looked into using `IRObjectFile::create()` and optionally calling `materializAllPermanently()` afterwards, but this turned out to be awkward. - The default target triple and data layout logic needs to happen *before* the call to `IRObjectFile::IRObjectFile()`, but after `Module` was created. - I tried passing a lambda in to do the module initialization, but this seemed to require threading the error message from `TargetRegistry::lookupTarget()` through `std::error_code`. - I also looked at setting `errMsg` directly from within the lambda, but this didn't look any better. (I guess there's a reason we weren't already using that function.) llvm-svn: 224466
* [sanitizer] allow -fsanitize-coverage=N w/ -fsanitize=leak, llvm partKostya Serebryany2014-12-171-4/+2
| | | | llvm-svn: 224463
* RegisterCoalescer: Fix stripCopies() picking up main range instead of ↵Matthias Braun2014-12-171-50/+78
| | | | | | | | | | subregister range This fixes a problem where stripCopies() would switch to values in the main liverange when it crossed a copy instruction. However when joining subranges we need to stay in the respective subregister ranges. llvm-svn: 224461
* R600/SI: Fix f64 inline immediatesMatt Arsenault2014-12-179-46/+398
| | | | llvm-svn: 224458
* [Hexagon] Reconfiguring register alternate names.Colin LeMahieu2014-12-171-13/+9
| | | | llvm-svn: 224455
* Enable the P8Model entryWill Schmidt2014-12-171-1/+1
| | | | | | | | This was missed last time around, for the P8 Instruction Scheduling changes (223257). This will hook the P8Model entry in so those changes will actually be used. llvm-svn: 224452
* ExecutionDepsFix: Correctly handle wide registers.Matthias Braun2014-12-171-70/+71
| | | | | | | | | | | | | | The ExecutionDepsFix previously mapped each register to 1 or zero registers of the register class it was called with and therefore simulating liveness for. This was problematic for cases involving wider registers like Q0 on ARM where ExecutionDepsFix gets invoked for the Dxx registers. In these cases the wide register would get mapped to the last matching D register, while it should have been all matching D registers. This commit changes the AliasMap to use a SmallVector to map registers to potentially multiple destination regclass registers. This is required to avoid regressions with subregister liveness tracking enabled. llvm-svn: 224447
* Random Number Generator Refactoring (removing from Module)JF Bastien2014-12-174-52/+61
| | | | | | | | | | This patch removes the RNG from Module. Passes should instead create a new RNG for their use as needed. Patch by Stephen Crane @rinon. Differential revision: http://reviews.llvm.org/D4377 llvm-svn: 224444
* [NVPTX] Fix bugs related to isSingleValueTypeJingyue Wu2014-12-173-13/+27
| | | | | | | | | | | | | | | | | | | | Summary: With isSingleValueType starting to treat vector types as single-value types, code that uses this interface needs to be updated. Test Plan: vector-global.ll nvcl-param-align.ll Reviewers: jholewinski Reviewed By: jholewinski Subscribers: llvm-commits, meheff, eliben, jholewinski Differential Revision: http://reviews.llvm.org/D6573 llvm-svn: 224440
* Fix CR/LF line endings in test caseTimur Iskhodzhanov2014-12-171-83/+83
| | | | llvm-svn: 224437
* ARM: correct an off-by-one in an assertSaleem Abdulrasool2014-12-172-1/+10
| | | | | | | | The assert was off-by-one, resulting in failures for valid input. Thanks to Asiri Rathnayake for pointing out the failure! llvm-svn: 224432
* [DAGCombine] Slightly improve lowering of BUILD_VECTOR into a shuffle.Michael Kuperstein2014-12-176-11/+156
| | | | | | | | | | This handles the case of a BUILD_VECTOR being constructed out of elements extracted from a vector twice the size of the result vector. Previously this was always scalarized. Now, we try to construct a shuffle node that feeds on extract_subvectors. This fixes PR15872 and provides a partial fix for PR21711. Differential Revision: http://reviews.llvm.org/D6678 llvm-svn: 224429
* MipsABIInfo class is used in different libraries. Moving the files to ↵Vladimir Medic2014-12-175-2/+2
| | | | | | MCTargetDesc folder(LLVMMipsDesc library) prevents linkage errors. There are no functional changes. llvm-svn: 224427
* [mips] Set GCC-compatible MIPS asssembler options before inline asm blocks.Toma Tabacu2014-12-179-31/+64
| | | | | | | | | | | | | | | | | | | | Summary: When generating MIPS assembly, LLVM always overrides the default assembler options by emitting the '.set noreorder', '.set nomacro' and '.set noat' directives, while GCC uses the default options if an assembly-level function contains inline assembly code. This becomes a problem when the code generated by LLVM is interleaved with inline assembly which assumes GCC-like assembler options (from Linux, for example). This patch fixes these conflicts by setting the appropriate assembler options at the beginning of an inline asm block and popping them at the end. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6637 llvm-svn: 224425
* Revert 224119 "This patch recognizes (+ (+ v0, v1) (+ v2, v3)), reorders ↵Suyog Sarda2014-12-172-51/+2
| | | | | | | | | | them for bundling into vector of loads, and vectorizes it." This was re-ordering floating point data types resulting in mismatch in output. llvm-svn: 224424
* Teach lit.cfg to recognize -windows-gnu in addition to -mingw32.Yaron Keren2014-12-171-3/+3
| | | | llvm-svn: 224421
* Added 5 more tests related to sink store revision 224247Elena Demikhovsky2014-12-175-0/+219
| | | | | | | | - by Ella Bolshinsky http://reviews.llvm.org/D6420 llvm-svn: 224418
* Strength reduce intrinsics with overflow into regular arithmetic operations ↵Erik Eckstein2014-12-174-12/+152
| | | | | | | | | | if possible. Some intrinsics, like s/uadd.with.overflow and umul.with.overflow, are already strength reduced. This change adds other arithmetic intrinsics: s/usub.with.overflow, smul.with.overflow. It completes the work on PR20194. llvm-svn: 224417
* Revert "Linker: Drop superseded subprograms"Duncan P. N. Exon Smith2014-12-173-156/+0
| | | | | | | | | | | | | | This reverts commit r224389. Based on feedback from the bots, the assertion seems to be going off *more* often, not less (previously I was just seeing it in an internal bootstrap, now it's happening in public builds too). http://lab.llvm.org:8080/green/job/clang-stage2-configure-Rlto_build/936/ http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-bootstrap/builds/5325 Reverting in order to investigate. llvm-svn: 224416
* Add parsing of 'foo@local".Justin Hibbits2014-12-172-0/+3
| | | | | | | | | | | | | | | | | | Summary: Currently, it supports generating, but not parsing, this expression. Test added as well. Test Plan: New test added, no regressions due to this. Reviewers: hfinkel Reviewed By: hfinkel Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6672 llvm-svn: 224415
* Remove a debugging assert.Rafael Espindola2014-12-171-1/+0
| | | | | | Sorry for the noise, I have no idea how it survived to the final version. llvm-svn: 224414
* Remove unused includes and out of date comment. NFC.Rafael Espindola2014-12-176-6/+0
| | | | llvm-svn: 224413
* Fix the windows build.Rafael Espindola2014-12-171-0/+2
| | | | llvm-svn: 224412
* Refactor and simplify the code reading /proc/cpuinfo. NFC.Rafael Espindola2014-12-171-47/+32
| | | | llvm-svn: 224410
* RegisterCoalescer: Sprinkle some const modifiers.Matthias Braun2014-12-171-11/+12
| | | | llvm-svn: 224409
* llvm-lto: Add testing coverage for local contextsDuncan P. N. Exon Smith2014-12-173-0/+66
| | | | | | | | | | | Add coverage in `llvm-lto` for the API exposed by libLTO to create modules in local contexts. The goal here isn't to test the symbol-related API extensively, just to confirm that these modules work at all. (I'll be shifting code around soon that should be NFC and I realized there was no test coverage.) llvm-svn: 224408
* Delete debugging cruft that crept in with r223802.Nick Lewycky2014-12-171-3/+0
| | | | llvm-svn: 224407
* InstSimplify: shl nsw/nuw undef, %V -> undefDavid Majnemer2014-12-172-13/+35
| | | | | | | | | | We can always choose an value for undef which might cause %V to shift out an important bit except for one case, when %V is zero. However, shl behaves like an identity function when the right hand side is zero. llvm-svn: 224405
* Make ValueEnumerator::print use OS for metadata too. Noticed by inspection.Nick Lewycky2014-12-171-2/+1
| | | | llvm-svn: 224404
* [CodeGenPrepare] Reapply r224351 with a fix for the assertion failure:Quentin Colombet2014-12-175-48/+590
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The type promotion helper does not support vector type, so when make such it does not kick in in such cases. Original commit message: [CodeGenPrepare] Move sign/zero extensions near loads using type promotion. This patch extends the optimization in CodeGenPrepare that moves a sign/zero extension near a load when the target can combine them. The optimization may promote any operations between the extension and the load to make that possible. Although this optimization may be beneficial for all targets, in particular AArch64, this is enabled for X86 only as I have not benchmarked it for other targets yet. ** Context ** Most targets feature extended loads, i.e., loads that perform a zero or sign extension for free. In that context it is interesting to expose such pattern in CodeGenPrepare so that the instruction selection pass can form such loads. Sometimes, this pattern is blocked because of instructions between the load and the extension. When those instructions are promotable to the extended type, we can expose this pattern. ** Motivating Example ** Let us consider an example: define void @foo(i8* %addr1, i32* %addr2, i8 %a, i32 %b) { %ld = load i8* %addr1 %zextld = zext i8 %ld to i32 %ld2 = load i32* %addr2 %add = add nsw i32 %ld2, %zextld %sextadd = sext i32 %add to i64 %zexta = zext i8 %a to i32 %addza = add nsw i32 %zexta, %zextld %sextaddza = sext i32 %addza to i64 %addb = add nsw i32 %b, %zextld %sextaddb = sext i32 %addb to i64 call void @dummy(i64 %sextadd, i64 %sextaddza, i64 %sextaddb) ret void } As it is, this IR generates the following assembly on x86_64: [...] movzbl (%rdi), %eax # zero-extended load movl (%rsi), %es # plain load addl %eax, %esi # 32-bit add movslq %esi, %rdi # sign extend the result of add movzbl %dl, %edx # zero extend the first argument addl %eax, %edx # 32-bit add movslq %edx, %rsi # sign extend the result of add addl %eax, %ecx # 32-bit add movslq %ecx, %rdx # sign extend the result of add [...] The throughput of this sequence is 7.45 cycles on Ivy Bridge according to IACA. Now, by promoting the additions to form more extended loads we would generate: [...] movzbl (%rdi), %eax # zero-extended load movslq (%rsi), %rdi # sign-extended load addq %rax, %rdi # 64-bit add movzbl %dl, %esi # zero extend the first argument addq %rax, %rsi # 64-bit add movslq %ecx, %rdx # sign extend the second argument addq %rax, %rdx # 64-bit add [...] The throughput of this sequence is 6.15 cycles on Ivy Bridge according to IACA. This kind of sequences happen a lot on code using 32-bit indexes on 64-bit architectures. Note: The throughput numbers are similar on Sandy Bridge and Haswell. ** Proposed Solution ** To avoid the penalty of all these sign/zero extensions, we merge them in the loads at the beginning of the chain of computation by promoting all the chain of computation on the extended type. The promotion is done if and only if we do not introduce new extensions, i.e., if we do not degrade the code quality. To achieve this, we extend the existing “move ext to load” optimization with the promotion mechanism introduced to match larger patterns for addressing mode (r200947). The idea of this extension is to perform the following transformation: ext(promotableInst1(...(promotableInstN(load)))) => promotedInst1(...(promotedInstN(ext(load)))) The promotion mechanism in that optimization is enabled by a new TargetLowering switch, which is off by default. In other words, by default, the optimization performs the “move ext to load” optimization as it was before this patch. ** Performance ** Configuration: x86_64: Ivy Bridge fixed at 2900MHz running OS X 10.10. Tested Optimization Levels: O3/Os Tests: llvm-testsuite + externals. Results: - No regression beside noise. - Improvements: CINT2006/473.astar: ~2% Benchmarks/PAQ8p: ~2% Misc/perlin: ~3% The results are consistent for both O3 and Os. <rdar://problem/18310086> llvm-svn: 224402
* Add printing the LC_ENCRYPTION_INFO_64 load command with llvm-objdump’s ↵Kevin Enderby2014-12-175-2/+364
| | | | | | | | -private-headers and add tests for the two AArch64 binaries. llvm-svn: 224400
* PR21875: codegen for non-type template parameters of nullptr_t typeDavid Blaikie2014-12-172-48/+55
| | | | llvm-svn: 224399
* Revert "[CodeGenPrepare] Move sign/zero extensions near loads using type ↵Reid Kleckner2014-12-175-571/+48
| | | | | | | | | promotion." This reverts commit r224351. It causes assertion failures when building ICU. llvm-svn: 224397
* SelectionDAG switch lowering: use 'unsigned' to count destination popularityHans Wennborg2014-12-162-3/+3
| | | | | | | | | SwitchInst::getNumCases() returns unsinged, so using uint64_t to count cases seems unnecessary. Also fix a missing CHECK in the test case. llvm-svn: 224393
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