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* [py3] Teach the CMake build to reject Python versions older than 2.7.Chandler Carruth2014-12-291-1/+7
| | | | | | | Continue to require Python 2 however as recent experiments suggest LLDB's build requires it. llvm-svn: 224948
* [X86] Fix some cases where some 8-bit instructions were marked as being ↵Craig Topper2014-12-291-18/+24
| | | | | | convertible to three address instructions, but aren't really. llvm-svn: 224940
* [X86] Add the 0x82 instructions to the disassebmler. They are identical in ↵Craig Topper2014-12-291-6/+35
| | | | | | functionality to the 0x80 opcode instructions, but are not valid in 64-bit mode. llvm-svn: 224939
* [x86] Refactor some tablegen instruction info classes slightly to prepare ↵Craig Topper2014-12-291-29/+28
| | | | | | for another change. NFC. llvm-svn: 224938
* [x86] Remove unused classes from tablegen instruction info.Craig Topper2014-12-291-23/+0
| | | | llvm-svn: 224937
* Add segmented stack support for DragonFlyBSD.Rafael Espindola2014-12-294-3/+122
| | | | | | Patch by Michael Neumann. llvm-svn: 224936
* Refactor duplicated code.Rafael Espindola2014-12-2915-104/+74
| | | | | | No intended functionality change. llvm-svn: 224935
* [multilib] Add support to the autoconf build to substituteChandler Carruth2014-12-293-0/+14
| | | | | | | | | | | | a CLANG_LIBDIR_SUFFIX variable. This is necessary before I can add support for using that variable to CMake and the C++ code in Clang, and the autoconf build system does all substitutions in the LLVM tree. As mentioned before, I'm not planning to add actual multilib support to the autoconf build, just enough stubs for it to keep playing nicely with the CMake build once that one has support. llvm-svn: 224922
* [cmake] Teach the llvm-config program to respect LLVM_LIBDIR_SUFFIX.Chandler Carruth2014-12-293-4/+9
| | | | | | | | | | | | | | For this to work, we have to encode it in the build variables and use it from llvm-config.cpp. I've tried to do this reasonably cleanly, but the code for llvm-config.cpp is pretty strange. However, with this, llvm-config stops giving the wrong answer when using LLVM_LIBDIR_SUFFIX. Note that the configure+make build just sets this to an empty string as that build system has zero support for multilib of any form. I'm not planning to add support there either, but this should leave a path for anyone that wanted to. llvm-svn: 224921
* [cmake] Push LLVM_LIBDIR_SUFFIX through to the LLVMConfig.cmake fileChandler Carruth2014-12-291-0/+2
| | | | | | | | | that is used by other projects to build against LLVM. This will allow subsequent patches to them to use LLVM_LIBDIR_SUFFIX, both when built as part of the larger LLVM build an as part of a standalone build against an installed set of LLVM libraries. llvm-svn: 224920
* [cmake] Start making LLVM_LIBDIR_SUFFIX effective by adding it toChandler Carruth2014-12-294-8/+9
| | | | | | | | | | | | | | | | | *numerous* places where it was missing in the CMake build. The primary change here is that the suffix is now actually used for all of the lib directories in the LLVM project's CMake. The various subprojects still need similar treatment. This is the first of a series of commits to try to make LLVM's cmake effective in a multilib Linux installation. I don't think many people are seriously using this variable so I'm hoping the fallout will be minimal. A somewhat unfortunate consequence of the nature of these commits is that until I land all of them, they will in part make the brokenness of our multilib support more apparant. At the end, things should actually work. llvm-svn: 224919
* Fixed 2 minor typos in the documentation.Elena Demikhovsky2014-12-291-2/+2
| | | | llvm-svn: 224917
* llvm/test/CodeGen/X86/fast-isel-call-bool.ll: Add explicit ↵NAKAMURA Takumi2014-12-281-1/+1
| | | | | | -mtriple=x86_64-unknown to satisfy x64. llvm-svn: 224907
* [X86][ISel] Fix a regression I introduced in r224884Keno Fischer2014-12-283-5/+17
| | | | | | | | | | | | | The else case ResultReg was not checked for validity. To my surprise, this case was not hit in any of the existing test cases. This includes a new test cases that tests this path. Also drop the `target triple` declaration from the original test as suggested by H.J. Lu, because apparently with it the test won't be run on Linux llvm-svn: 224901
* [X86] Add missing memory variants to AVX false dependency breakingMichael Kuperstein2014-12-283-64/+99
| | | | | | | | Adds missing memory instruction variants to AVX false dependency breaking handling. (SSE was handled in r224246) Differential Revision: http://reviews.llvm.org/D6780 llvm-svn: 224900
* [CodeGenPrepare] Teach when it is profitable to speculate calls to ↵Andrea Di Biagio2014-12-285-0/+415
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | @llvm.cttz/ctlz. If the control flow is modelling an if-statement where the only instruction in the 'then' basic block (excluding the terminator) is a call to cttz/ctlz, CodeGenPrepare can try to speculate the cttz/ctlz call and simplify the control flow graph. Example: \code entry: %cmp = icmp eq i64 %val, 0 br i1 %cmp, label %end.bb, label %then.bb then.bb: %c = tail call i64 @llvm.cttz.i64(i64 %val, i1 true) br label %end.bb end.bb: %cond = phi i64 [ %c, %then.bb ], [ 64, %entry] \code In this example, basic block %then.bb is taken if value %val is not zero. Also, the phi node in %end.bb would propagate the size-of in bits of %val only if %val is equal to zero. With this patch, CodeGenPrepare will try to hoist the call to cttz from %then.bb into basic block %entry only if cttz is cheap to speculate for the target. Added two new hooks in TargetLowering.h to let targets customize the behavior (i.e. decide whether it is cheap or not to speculate calls to cttz/ctlz). The two new methods are 'isCheapToSpeculateCtlz' and 'isCheapToSpeculateCttz'. By default, both methods return 'false'. On X86, method 'isCheapToSpeculateCtlz' returns true only if the target has LZCNT. Method 'isCheapToSpeculateCttz' only returns true if the target has BMI. Differential Revision: http://reviews.llvm.org/D6728 llvm-svn: 224899
* Scalarizer for masked load and store intrinsics.Elena Demikhovsky2014-12-282-40/+289
| | | | | | | | Masked vector intrinsics are a part of common LLVM IR, but they are really supported on AVX2 and AVX-512 targets. I added a code that translates masked intrinsic for all other targets. The masked vector intrinsic is converted to a chain of scalar operations inside conditional basic blocks. http://reviews.llvm.org/D6436 llvm-svn: 224897
* [x86] Prevent instruction selection of AVX512 cmp.ps/pd/ss/sd intrinsics ↵Craig Topper2014-12-272-22/+23
| | | | | | with illegal immediates. Correctly this time. I did the wrong patterns the first time. llvm-svn: 224891
* PowerPC: CTR shouldn't fire if a TLS call is in the loopDavid Majnemer2014-12-272-1/+42
| | | | | | | | | | | | | | | Determining the address of a TLS variable results in a function call in certain TLS models. This means that a simple ICmpInst might actually result in invalidating the CTR register. In such cases, do not attempt to rely on the CTR register for loop optimization purposes. This fixes PR22034. Differential Revision: http://reviews.llvm.org/D6786 llvm-svn: 224890
* Fixing another -Wunused-variable warning, this time in release builds ↵Aaron Ballman2014-12-271-3/+3
| | | | | | without asserts. NFC. llvm-svn: 224889
* Removing a variable that is set but never used, to silence a ↵Aaron Ballman2014-12-271-4/+0
| | | | | | -Wunused-but-set-variable warning; NFC. llvm-svn: 224888
* [x86] Prevent instruction selection of AVX512 cmp.ps/pd/ss/sd intrinsics ↵Craig Topper2014-12-271-15/+18
| | | | | | with illegal immediates. Forgot to do this when I did SSE/SSE2/AVX/AVX2. llvm-svn: 224887
* [x86] Assert on invalid immediates in the instruction printer for ↵Craig Topper2014-12-272-4/+8
| | | | | | cmp.ps/pd/ss/sd instead of truncating the immediate. The assembly parser and instruction selection shouldn't generate invalid immediates. llvm-svn: 224886
* [x86] Prevent llvm.x86.cmp.ps/pd/ss/sd from being selected with bad ↵Craig Topper2014-12-272-26/+33
| | | | | | immediates. The frontend now checks this when the builtin is used. This will allow the instruction printer to not have to deal with invalid immediates on these instructions. llvm-svn: 224885
* [FastIsel][X86] Fix invalid register replacement for bool argsKeno Fischer2014-12-272-28/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Consider the following IR: %3 = load i8* undef %4 = trunc i8 %3 to i1 %5 = call %jl_value_t.0* @foo(..., i1 %4, ...) ret %jl_value_t.0* %5 Bools (that are the result of direct truncs) are lowered as whatever the argument to the trunc was and a "and 1", causing the part of the MBB responsible for this argument to look something like this: %vreg8<def,tied1> = AND8ri %vreg7<kill,tied0>, 1, %EFLAGS<imp-def>; GR8:%vreg8,%vreg7 Later, when the load is lowered, it will insert %vreg15<def> = MOV8rm %vreg14, 1, %noreg, 0, %noreg; mem:LD1[undef] GR8:%vreg15 GR64:%vreg14 but remember to (at the end of isel) replace vreg7 by vreg15. Now for the bug. In fast isel lowering, we mistakenly mark vreg8 as the result of the load instead of the trunc. This adds a fixup to have vreg8 replaced by whatever the result of the load is as well, so we end up with %vreg15<def,tied1> = AND8ri %vreg15<kill,tied0>, 1, %EFLAGS<imp-def>; GR8:%vreg15 which is an SSA violation and causes problems later down the road. This fixes PR21557. Test Plan: Test test case from PR21557 is added to the test suite. Reviewers: ributzka Reviewed By: ributzka Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6245 llvm-svn: 224884
* Convert test to llvm-readobj. NFC.Rafael Espindola2014-12-261-318/+361
| | | | llvm-svn: 224872
* [Hexagon] Adding auto-incrementing loads with and without byte reversal.Colin LeMahieu2014-12-262-0/+100
| | | | llvm-svn: 224871
* [Hexagon] Adding locked loads.Colin LeMahieu2014-12-262-0/+23
| | | | llvm-svn: 224870
* [Hexagon] Adding deallocframe and circular addressing loads.Colin LeMahieu2014-12-266-8/+163
| | | | llvm-svn: 224869
* [Hexagon] Adding remaining post-increment instruction variants. Removing ↵Colin LeMahieu2014-12-264-61/+61
| | | | | | unused classes. llvm-svn: 224868
* [Hexagon] Adding post-increment unsigned byte loads.Colin LeMahieu2014-12-264-16/+27
| | | | llvm-svn: 224867
* [Hexagon] Adding post-increment signed byte loads with tests.Colin LeMahieu2014-12-264-12/+127
| | | | llvm-svn: 224866
* Use llvm-readobj. NFC.Rafael Espindola2014-12-261-238/+162
| | | | llvm-svn: 224864
* [X86] Add the debug registers DR8-DR15 so we can assemble and disassemble ↵Craig Topper2014-12-264-11/+27
| | | | | | references to them. llvm-svn: 224862
* [X86] Don't fail disassembly if REX.R/REX.B is used on an MMX register. ↵Craig Topper2014-12-263-6/+18
| | | | | | Similar fix to not fail to disassembler CR9-CR15 references. llvm-svn: 224861
* Band-aid fix for PR22032: don't emit DWARF debug info if AddressSanitizer is ↵Timur Iskhodzhanov2014-12-262-3/+19
| | | | | | enabled on Windows llvm-svn: 224860
* No need to run llvm-as. NFC.Rafael Espindola2014-12-261-5/+4
| | | | llvm-svn: 224859
* InstCombine: Infer nuw for multipliesDavid Majnemer2014-12-264-6/+57
| | | | | | | A multiply cannot unsigned wrap if there are bitwidth, or more, leading zero bits between the two operands. llvm-svn: 224849
* ValueTracking: Small cleanup in ComputeNumSignBitsDavid Majnemer2014-12-261-2/+2
| | | | | | | Constant contains the isAllOnesValue and isNullValue predicates, not ConstantInt. llvm-svn: 224848
* InstCombe: Infer nsw for multipliesDavid Majnemer2014-12-265-89/+103
| | | | | | | We already utilize this logic for reducing overflow intrinsics, it makes sense to reuse it for normal multiplies as well. llvm-svn: 224847
* Teach disassembler to handle illegal immediates on (v)cmpps/pd/ss/sd ↵Craig Topper2014-12-266-71/+84
| | | | | | instructions. Instead of rejecting we'll just generate the _alt forms that don't try to alter the mnemonic. While I'm here, merge some common code in the Instruction printers for the condition code replacement and fix the mask on SSE to be 3-bits instead of 4. llvm-svn: 224846
* Use MCPhysReg for table of register encodings.Craig Topper2014-12-261-3/+3
| | | | llvm-svn: 224845
* [PowerPC] [FastISel] i1 constants must be zero extendedHal Finkel2014-12-252-1/+28
| | | | | | | | | | | When materializing constant i1 values, they must be zero extended. We represent i1 values as [0, 1], not [0, -1], in i32 registers. As it turns out, this code path was dead for i1 values prior to r216006 (which is why this did not manifest in miscompiles until recently). Fixes -O0 self-hosting on PPC64/Linux. llvm-svn: 224842
* Silence GCC's -Wparentheses warningDavid Majnemer2014-12-251-1/+1
| | | | | | No functionality change intended. llvm-svn: 224833
* Documentation for Masked Load and Store intrinsics.Elena Demikhovsky2014-12-251-0/+87
| | | | llvm-svn: 224832
* Masked Load/Store - Changed the order of parameters in intrinsics.Elena Demikhovsky2014-12-2511-74/+101
| | | | | | | No functional changes. The documentation is coming. llvm-svn: 224829
* CodeGen: Error on redefinitions instead of assertingDavid Majnemer2014-12-243-5/+29
| | | | | | | It's possible to have a prior definition of a symbol in module asm. Raise an error instead of crashing. llvm-svn: 224828
* CodeGen: Allow aliases to be overridden by variablesDavid Majnemer2014-12-242-0/+13
| | | | llvm-svn: 224827
* MC: address some comments in deprecation checksSaleem Abdulrasool2014-12-241-4/+4
| | | | | | | | | Bob Wilson pointed out the unnecessary checks that had been committed to the instruction check predicates. The check was meant to ensure that the check was not accidentally applied to non-ARM instructions. This is better served as an assertion rather than a condition check. llvm-svn: 224825
* MC: Label definitions are permitted after .set directivesDavid Majnemer2014-12-245-1/+49
| | | | | | | | | .set directives may be overridden by other .set directives as well as label definitions. This fixes PR22019. llvm-svn: 224811
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