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* [asan] more code to merge crash callbacks. Doesn't fully work yet, but ↵Kostya Serebryany2012-07-171-12/+58
| | | | | | allows to hold performance experiments llvm-svn: 160361
* Fix a crash in the legalization of large vectors.Nadav Rotem2012-07-172-6/+19
| | | | | | | When truncating a result of a vector that is split we need to use the result of the split vector, and not re-split the dead node. llvm-svn: 160357
* Implement r160312 as target indepedenet dag combine.Evan Cheng2012-07-174-53/+34
| | | | llvm-svn: 160354
* Revert commit r160307. We decide to move builtins selection to the backend.Simon Atanasyan2012-07-171-3/+1
| | | | llvm-svn: 160352
* Make sure constant bitwidth is <= 64 bit before calling getSExtValue().Evan Cheng2012-07-171-1/+2
| | | | llvm-svn: 160350
* This is another case where instcombine demanded bits optimization createdEvan Cheng2012-07-174-4/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | large immediates. Add dag combine logic to recover in case the large immediates doesn't fit in cmp immediate operand field. int foo(unsigned long l) { return (l>> 47) == 1; } we produce %shr.mask = and i64 %l, -140737488355328 %cmp = icmp eq i64 %shr.mask, 140737488355328 %conv = zext i1 %cmp to i32 ret i32 %conv which codegens to movq $0xffff800000000000,%rax andq %rdi,%rax movq $0x0000800000000000,%rcx cmpq %rcx,%rax sete %al movzbl %al,%eax ret TargetLowering::SimplifySetCC would transform (X & -256) == 256 -> (X >> 8) == 1 if the immediate fails the isLegalICmpImmediate() test. For x86, that's immediates which are not a signed 32-bit immediate. Based on a patch by Eli Friedman. PR10328 rdar://9758774 llvm-svn: 160346
* Reapply r160340. LSR: Limit CollectSubexprs.Andrew Trick2012-07-171-28/+52
| | | | | | Speculatively fix crashes by code inspection. Can't reproduce them yet. llvm-svn: 160344
* Revert "LSR: try not to blow up solving combinatorial problems brute force."Andrew Trick2012-07-171-51/+28
| | | | | | Some units tests crashed on a different platform. llvm-svn: 160341
* LSR: try not to blow up solving combinatorial problems brute force.Andrew Trick2012-07-171-28/+51
| | | | | | | | | | This places limits on CollectSubexprs to constrains the number of reassociation possibilities. It limits the recursion depth and skips over chains of nested recurrences outside the current loop. Fixes PR13361. Although underlying SCEV behavior is still potentially bad. llvm-svn: 160340
* TableGen: Allow conditional instruction pattern in multiclass.Jim Grosbach2012-07-172-2/+43
| | | | | | | | | | | | | | | | | | | Define a 'null_frag' SDPatternOperator node, which if referenced in an instruction Pattern, results in the pattern being collapsed to be as-if '[]' had been specified instead. This allows supporting a multiclass definition where some instaniations have ISel patterns associated and others do not. For example, multiclass myMulti<RegisterClass rc, SDPatternOperator OpNode = null_frag> { def _x : myI<(outs rc:), (ins rc:), []>; def _r : myI<(outs rc:), (ins rc:), [(set rc:, (OpNode rc:))]>; } defm foo : myMulti<GRa, not>; defm bar : myMulti<GRb>; llvm-svn: 160333
* Fix function select_cc_f32 in test/CodeGen/Mips/selectcc.ll.Akira Hatanaka2012-07-161-6/+8
| | | | llvm-svn: 160329
* Defer checking for registers in the MC AsmMatcher until the after ↵Owen Anderson2012-07-161-16/+16
| | | | | | user-defined match classes have been checked. This allows the creation of MatchClass's that are supersets of a register class. llvm-svn: 160327
* fix PR13339 (remove the predecessor from the unwind BB when removing an invoke)Nuno Lopes2012-07-162-0/+23
| | | | llvm-svn: 160325
* teach ConstantRange that zero times X is always zeroNuno Lopes2012-07-162-0/+14
| | | | llvm-svn: 160317
* For something likeEvan Cheng2012-07-163-2/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | uint32_t hi(uint64_t res) { uint_32t hi = res >> 32; return !hi; } llvm IR looks like this: define i32 @hi(i64 %res) nounwind uwtable ssp { entry: %lnot = icmp ult i64 %res, 4294967296 %lnot.ext = zext i1 %lnot to i32 ret i32 %lnot.ext } The optimizer has optimize away the right shift and truncate but the resulting constant is too large to fit in the 32-bit immediate field. The resulting x86 code is worse as a result: movabsq $4294967296, %rax ## imm = 0x100000000 cmpq %rax, %rdi sbbl %eax, %eax andl $1, %eax This patch teaches the x86 lowering code to handle ult against a large immediate with trailing zeros. It will issue a right shift and a truncate followed by a comparison against a shifted immediate. shrq $32, %rdi testl %edi, %edi sete %al movzbl %al, %eax It also handles a ugt comparison against a large immediate with trailing bits set. i.e. X > 0x0ffffffff -> (X >> 32) >= 1 rdar://11866926 llvm-svn: 160312
* Minor cleanup and docs.Nadav Rotem2012-07-161-1/+3
| | | | llvm-svn: 160311
* MIPS: Create two definitions for __builtin_mips_shll_qb builtin.Simon Atanasyan2012-07-161-1/+3
| | | | | | | The first variant accepts immediate number as the second argument. The second variant accepts register operand as the second argument. llvm-svn: 160307
* Make ComputeDemandedBits return a deterministic result when computing an ↵Nadav Rotem2012-07-162-0/+13
| | | | | | | | | | | AssertZext value. In the added testcase the constant 55 was behind an AssertZext of type i1, and ComputeDemandedBits reported that some of the bits were both known to be one and known to be zero. Together with Michael Kuperstein <michael.m.kuperstein@intel.com> llvm-svn: 160305
* Revert "AMDGPU: Add core backend files for R600/SI codegen v6"Tom Stellard2012-07-16114-28329/+0
| | | | | | This reverts commit 4ea70107c5e51230e9e60f0bf58a0f74aa4885ea. llvm-svn: 160303
* Revert "include/llvm: Add R600 Intrinsics v6"Tom Stellard2012-07-162-37/+0
| | | | | | This reverts commit 600f7a90f3eef4c5108179b43e27cfd9e5de7cdc. llvm-svn: 160302
* Revert "Build script changes for R600/SI Codegen v6"Tom Stellard2012-07-166-17/+11
| | | | | | This reverts commit e3013202259ed1e006c21817c63cf25d75982721. llvm-svn: 160301
* Revert "test/CodeGen/R600: Add some basic tests v6"Tom Stellard2012-07-1627-212/+0
| | | | | | This reverts commit 11d3457afcda7848448dd7f11b2ede6552ffb9ea. llvm-svn: 160300
* Revert "Target/AMDGPU/R600KernelParameters.cpp: Fix two includes, ↵Tom Stellard2012-07-161-2/+2
| | | | | | | | <llvm/IRBuilder.h> and <llvm/TypeBuilder.h>" This reverts commit 0258a6bdd30802f5cc0e8e57c8e768fde2aef590. llvm-svn: 160299
* Revert "Target/AMDGPU: [CMake] Fix dependencies. 1) Add intrinsics_gen. Add ↵Tom Stellard2012-07-162-3/+1
| | | | | | | | AMDGPUCommonTableGen." This reverts commit ebc934ba32ee71abbb8f0f2eb6a0fbaa613ba0d2. llvm-svn: 160298
* Revert "Target/AMDGPU/R600KernelParameters.cpp: Don't use "and", "or" as ↵Tom Stellard2012-07-161-8/+8
| | | | | | | | conditional operator..." This reverts commit 29f28bc14ad5a907f5dc849f004fafeec0aab33a. llvm-svn: 160297
* Revert "Target/AMDGPU/AMDILIntrinsicInfo.cpp: Use llvm_unreachable() in ↵Tom Stellard2012-07-161-1/+1
| | | | | | | | nonreturn function, instead of assert(0)." This reverts commit 4ba4acc1bc2561b944a571edbb6a2dc78e357dfe. llvm-svn: 160296
* Revert "Target/AMDGPU: Fix includes, or msvc build failed."Tom Stellard2012-07-162-2/+2
| | | | | | This reverts commit fef4aa1b16fcf7a472559abbbcf4c1adc9eb5ca6. llvm-svn: 160295
* make ConstantRange::getSetSize() properly compute the size of wrapped and ↵Nuno Lopes2012-07-162-13/+19
| | | | | | | | full sets. Make it always return APInts with the same bitwidth for the same ConstantRange bitwidth to simply clients llvm-svn: 160294
* With r160248 in place this code is no longer needed.Chad Rosier2012-07-162-17/+1
| | | | llvm-svn: 160293
* [asan] a bit more refactoring, addressed some of the style comments from ↵Kostya Serebryany2012-07-161-17/+39
| | | | | | chandlerc, partially implemented crash callback merging (under flag) llvm-svn: 160290
* MSVC's implementation of isalnum will assert on characters > 255, so we need ↵Aaron Ballman2012-07-161-1/+5
| | | | | | to use an unsigned char to ensure the integer promotion happens properly. This fixes an assert in debug builds with CodeGen\X86\utf8.ll llvm-svn: 160286
* [asan] refactor instrumentation to allow merging the crash callbacks (not ↵Kostya Serebryany2012-07-162-54/+101
| | | | | | fully implemented yet, no functionality change except the BB order) llvm-svn: 160284
* Target/AMDGPU: Fix includes, or msvc build failed.NAKAMURA Takumi2012-07-162-2/+2
| | | | llvm-svn: 160280
* Target/AMDGPU/AMDILIntrinsicInfo.cpp: Use llvm_unreachable() in nonreturn ↵NAKAMURA Takumi2012-07-161-1/+1
| | | | | | function, instead of assert(0). llvm-svn: 160279
* Target/AMDGPU/R600KernelParameters.cpp: Don't use "and", "or" as conditional ↵NAKAMURA Takumi2012-07-161-8/+8
| | | | | | operator... llvm-svn: 160278
* Doubleword Shift Left Logical Plus 32Jack Carter2012-07-165-1/+102
| | | | | | | | | | | | | | | | | | | | | Mips shift instructions DSLL, DSRL and DSRA are transformed into DSLL32, DSRL32 and DSRA32 respectively if the shift amount is between 32 and 63 Here is a description of DSLL: Purpose: Doubleword Shift Left Logical Plus 32 To execute a left-shift of a doubleword by a fixed amount--32 to 63 bits Description: GPR[rd] <- GPR[rt] << (sa+32) The 64-bit doubleword contents of GPR rt are shifted left, inserting zeros into the emptied bits; the result is placed in GPR rd. The bit-shift amount in the range 0 to 31 is specified by sa. This patch implements the direct object output of these instructions. llvm-svn: 160277
* Target/AMDGPU: [CMake] Fix dependencies. 1) Add intrinsics_gen. Add ↵NAKAMURA Takumi2012-07-162-1/+3
| | | | | | AMDGPUCommonTableGen. llvm-svn: 160276
* Target/AMDGPU/R600KernelParameters.cpp: Fix two includes, <llvm/IRBuilder.h> ↵NAKAMURA Takumi2012-07-161-2/+2
| | | | | | and <llvm/TypeBuilder.h> llvm-svn: 160275
* Fix tests that failed on i686-win32 after r160248:Alexey Samsonov2012-07-162-3/+4
| | | | | | | | 1. FileCheck-ize epilogue.ll and allow another asm instruction to restore %rsp. 2. Remove check in widen_arith-3.ll that was hitting instruction in epilogue instead of vector add. llvm-svn: 160274
* test/CodeGen/R600: Add some basic tests v6Tom Stellard2012-07-1627-0/+212
| | | | llvm-svn: 160273
* Build script changes for R600/SI Codegen v6Tom Stellard2012-07-166-11/+17
| | | | llvm-svn: 160272
* include/llvm: Add R600 Intrinsics v6Tom Stellard2012-07-162-0/+37
| | | | llvm-svn: 160271
* AMDGPU: Add core backend files for R600/SI codegen v6Tom Stellard2012-07-16114-0/+28329
| | | | llvm-svn: 160270
* [asan] initialize asan error callbacks in runOnModule instead of doing that ↵Kostya Serebryany2012-07-161-8/+20
| | | | | | on-demand llvm-svn: 160269
* Fix a bug in the 3-address conversion of LEA when one of the operands is anNadav Rotem2012-07-162-0/+23
| | | | | | | | | | | | undef virtual register. The problem is that ProcessImplicitDefs removes the definition of the register and marks all uses as undef. If we lose the undef marker then we get a register which has no def, is not marked as undef. The live interval analysis does not collect information for these virtual registers and we crash in later passes. Together with Michael Kuperstein <michael.m.kuperstein@intel.com> llvm-svn: 160260
* Revert r160254 temporarily.Chandler Carruth2012-07-162-26/+28
| | | | | | | | | | | | It turns out that ASan relied on the at-the-end block insertion order to (purely by happenstance) disable some LLVM optimizations, which in turn start firing when the ordering is made more "normal". These optimizations in turn merge many of the instrumentation reporting calls which breaks the return address based error reporting in ASan. We're looking at several different options for fixing this. llvm-svn: 160256
* Teach AddressSanitizer to create basic blocks in a more natural order.Chandler Carruth2012-07-162-28/+26
| | | | | | | | | This is particularly useful to the backend code generators which try to process things in the incoming function order. Also, cleanup some uses of IRBuilder to be a bit simpler and more clear. llvm-svn: 160254
* Add a basic test for AddressSanitizer. This is just a bare-bonesChandler Carruth2012-07-161-0/+70
| | | | | | | | | | | functionality test. In general, unless the functionality is substantially separated, we should lump more basic testing into this file. The test running infrastructure likes having a few test files with more comprehensive testing within them. llvm-svn: 160253
* Add support for attaching branch weight metadata directly from the IRBuilder.Chandler Carruth2012-07-162-4/+30
| | | | | | | | | Added a basic unit test for this with CreateCondBr. I didn't go all the way and test the switch side as the boilerplate for setting up the switch IRBuilder unit tests is a lot more. Fortunately, the two share all the interesting code paths. llvm-svn: 160251
* Add a boring bit of boilerplate to start testing IRBuilder::CreateCondBr.Chandler Carruth2012-07-161-1/+15
| | | | | | | This is in anticipation of changing CreateCondBr and wanting to test those changes. llvm-svn: 160250
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