summaryrefslogtreecommitdiffstats
path: root/llvm
Commit message (Collapse)AuthorAgeFilesLines
...
* WebAssembly: handle `ret void`.JF Bastien2015-07-314-3/+13
| | | | | | | | | | | | | | | Summary: Use -1 as numoperands for the return SDTypeProfile, denoting that return is variadic. Note that the patterns in InstrControl.td still need to match the inputs, so this ins't an "anything goes" variadic on ret! The next step will be to handle other local types (not just int32). Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11692 llvm-svn: 243783
* [libFuzzer] make sure that 2-byte arguments of switch() are handled properlyKostya Serebryany2015-07-313-13/+52
| | | | llvm-svn: 243781
* MIR Serialization: Serialize the floating point immediate machine operands.Alex Lorenz2015-07-318-2/+219
| | | | | Reviewers: Duncan P. N. Exon Smith llvm-svn: 243780
* IR: Add a broad bitcode compatibility testDuncan P. N. Exon Smith2015-07-314-2/+2482
| | | | | | | | | | | | | | | | Successive versions of LLVM should retain the ability to parse bitcode generated by old releases of the compiler. This adds a bitcode format compatibility test, which is intended to provide good (albeit not entirely exhaustive) coverage of the current LangRef. This also includes compatibility tests for LLVM 3.6. After every 3.X.0 release, the compatibility.ll file from the 3.X branch should be copied to compatibility-3.X.ll on trunk, and the 3.X.0 release used to generate a corresponding bitcode file. Patch by Vedant Kumar! llvm-svn: 243779
* [dwarfdump] Ignore scattered relocations for mach-o.Frederic Riss2015-07-314-3/+14
| | | | | | | | | | | | | | When encountering a scattered relocation, the code would assert trying to access an unexisting section. I couldn't find a way to expose the result of the processing of a scattered reloc, and I'm really unsure what the right thing to do is. This patch just skips them during the processing in DwarfContext and adds a mach-o file to the tests that exposed the asserting behavior. (This is a new failure that is being exposed by Rafael's recent work on the libObject interfaces. I think the wrong behavior has always happened, but now it's asserting) llvm-svn: 243778
* [dsymutil] Support multiple input files on the command lineFrederic Riss2015-07-313-23/+46
| | | | llvm-svn: 243777
* DI: Remove DW_TAG_arg_variable and DW_TAG_auto_variableDuncan P. N. Exon Smith2015-07-31297-1114/+1103
| | | | | | | | | | | | | | | | | | | | | | | | Remove the fake `DW_TAG_auto_variable` and `DW_TAG_arg_variable` tags, using `DW_TAG_variable` in their place Stop exposing the `tag:` field at all in the assembly format for `DILocalVariable`. Most of the testcase updates were generated by the following sed script: find test/ -name "*.ll" -o -name "*.mir" | xargs grep -l 'DILocalVariable' | xargs sed -i '' \ -e 's/tag: DW_TAG_arg_variable, //' \ -e 's/tag: DW_TAG_auto_variable, //' There were only a handful of tests in `test/Assembly` that I needed to update by hand. (Note: a follow-up could change `DILocalVariable::DILocalVariable()` to set the tag to `DW_TAG_formal_parameter` instead of `DW_TAG_variable` (as appropriate), instead of having that logic magically in the backend in `DbgVariable`. I've added a FIXME to that effect.) llvm-svn: 243774
* x86: check hasOpaqueSPAdjustment in canRealignStackJF Bastien2015-07-311-4/+6
| | | | | | | | | | | | | | | Summary: @rnk pointed out in [1] that x86's canRealignStack logic should match that in CantUseSP from hasBasePointer. [1]: http://reviews.llvm.org/D11160?id=29713#inline-89350 Reviewers: rnk Subscribers: rnk, llvm-commits Differential Revision: http://reviews.llvm.org/D11377 llvm-svn: 243772
* WebAssembly: handle unused function arguments.JF Bastien2015-07-312-4/+26
| | | | | | | | Subscribers: llvm-commits, sunfish, jfb Differential Revision: http://reviews.llvm.org/D11684 llvm-svn: 243770
* Attempt to appease the MSVC build botsDavid Majnemer2015-07-311-1/+1
| | | | | | | They don't seem to care for initializing an ArrayRef with a std::initializer_list. llvm-svn: 243769
* [libFuzzer] record traces from the switch statements only when told to do soKostya Serebryany2015-07-311-0/+1
| | | | llvm-svn: 243768
* New EH representation for MSVC compatibilityDavid Majnemer2015-07-3139-121/+2313
| | | | | | | | | | This introduces new instructions neccessary to implement MSVC-compatible exception handling support. Most of the middle-end and none of the back-end haven't been audited or updated to take them into account. Differential Revision: http://reviews.llvm.org/D11097 llvm-svn: 243766
* DI: Rewrite the DIBuilder local variable APIDuncan P. N. Exon Smith2015-07-316-34/+67
| | | | | | | | | | | | Replace the general `createLocalVariable()` with two more specific functions: `createParameterVariable()` and `createAutoVariable()`, and rewrite the documentation. Besides cleaning up the API, this avoids exposing the fake DWARF tags `DW_TAG_arg_variable` and `DW_TAG_auto_variable` to frontends, and is preparation for removing them completely. llvm-svn: 243764
* WebAssembly: print basic integer assembly.JF Bastien2015-07-318-12/+291
| | | | | | | | | | | | | | | | | | | Summary: This prints assembly for int32 integer operations defined in WebAssemblyInstrInteger.td only, with major caveats: - The operation names are currently incorrect. - Other integer and floating-point types will be added later. - The printer isn't factored out to handle recursive AST code yet, since it can't even handle control flow anyways. - The assembly format isn't full s-expressions yet either, this will be added later. - This currently disables PrologEpilogCodeInserter as well as MachineCopyPropagation becasue they don't like virtual registers, which WebAssembly likes quite a bit. This will be fixed by factoring out NVPTX's change (currently a fork of PrologEpilogCodeInserter). Reviewers: sunfish Subscribers: llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11671 llvm-svn: 243763
* [COFF] Consider the ImageBase when reporting section addressesDavid Majnemer2015-07-311-2/+10
| | | | | | This lets us reenable the lld test disabled in r243758. llvm-svn: 243761
* [libFuzzer] support switch interception in dfsan modeKostya Serebryany2015-07-314-4/+41
| | | | llvm-svn: 243760
* [CodeGenPrepare] Compress a pair. No functional change.Benjamin Kramer2015-07-311-7/+3
| | | | llvm-svn: 243759
* [x86] reassociate integer multiplies using machine combiner passSanjay Patel2015-07-312-10/+73
| | | | | | | | | | | | | Add i16, i32, i64 imul machine instructions to the list of reassociation candidates. A new bit of logic is needed to handle integer instructions: they have an implicit EFLAGS operand, so we have to make sure it's dead in order to do any reassociation with integer ops. Differential Revision: http://reviews.llvm.org/D11660 llvm-svn: 243756
* [COFF] Return symbol VAs instead of RVAs for PE filesReid Kleckner2015-07-314-0/+39
| | | | | | | | This makes llvm-nm consistent with binutils nm on executables and DLLs. For a vanilla hello world executable, the address of main should include the default image base of 0x400000. llvm-svn: 243755
* [AArch64] Favor extended reg patterns for subGeoff Berry2015-07-312-0/+148
| | | | | | | | | | | | | | Summary: Favor the extended reg patterns over the shifted reg patterns that match only the operand shift and not the full sign/zero extend and shift. Reviewers: jmolloy, t.p.northover Subscribers: mcrosier, aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D11569 llvm-svn: 243753
* don't repeat function names in comments; NFCSanjay Patel2015-07-311-34/+20
| | | | llvm-svn: 243751
* [CaptureTracker] Provide an ordered basic block to PointerMayBeCapturedBeforeBruno Cardoso Lopes2015-07-318-81/+205
| | | | | | | | | | | | | | | | | | This patch is a follow up from r240560 and is a step further into mitigating the compile time performance issues in CaptureTracker. By providing the CaptureTracker with a "cached ordered basic block" instead of computing it every time, MemDepAnalysis can use this cache throughout its calls to AA->callCapturesBefore, avoiding to recompute it for every scanned instruction. In the same testcase used in r240560, compile time is reduced from 2min to 30s. This also fixes PR22348. rdar://problem/19230319 Differential Revision: http://reviews.llvm.org/D11364 llvm-svn: 243750
* [regalloc] Make RegMask clobbers prevent merging vreg's into PhysRegs when ↵Daniel Sanders2015-07-311-0/+8
| | | | | | | | | | | | | | | | | | | | | hoisting def's upwards. Summary: This prevents vreg260 and D7 from being merged in: %vreg260<def> = LDC1 ... JAL <ga:@sin>, <regmask ... list not containing D7 ...> %D7<def> = COPY %vreg260; ... Doing so is not valid because the JAL clobbers the D7. This fixes the almabench regression in the LLVM 3.7.0 release branch. Reviewers: MatzeB Subscribers: MatzeB, qcolombet, hans, llvm-commits Differential Revision: http://reviews.llvm.org/D11649 llvm-svn: 243745
* Refactor: Simplify boolean conditional return statements in lib/Target/NVPTXJingyue Wu2015-07-313-37/+15
| | | | | | | | | | | | Summary: Use clang-tidy to simplify boolean conditional return statements Reviewers: rafael, echristo, chandlerc, bkramer, craig.topper, dexonsmith, chapuni, eliben, jingyue, jholewinski Subscribers: llvm-commits, jholewinski Differential Revision: http://reviews.llvm.org/D9983 llvm-svn: 243734
* AMDGPU: Fix v16i32 to v16i8 truncstoreMatt Arsenault2015-07-312-0/+49
| | | | llvm-svn: 243731
* [libFuzzer] trace switch statements and apply mutations based on the ↵Kostya Serebryany2015-07-316-4/+143
| | | | | | expected case values llvm-svn: 243726
* ELFYAML: Enable parsing of EM_AMDGPUTom Stellard2015-07-312-0/+13
| | | | | | | | Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11263 llvm-svn: 243724
* AMDGPU/SI: Set DwarfRegNumMatt Arsenault2015-07-311-6/+14
| | | | | | | This requires a fix in tablegen for the cast<int> from bits<16> to work in the list initializer. llvm-svn: 243723
* TableGen: Support folding casts from bits to intMatt Arsenault2015-07-312-0/+18
| | | | | | | | | | | | | | | This is to fix an incorrect error when trying to initialize DwarfNumbers with a !cast<int> of a bits initializer. getValuesAsListOfInts("DwarfNumbers") would not see an IntInit and instead the cast, so would give up. It seems likely that this could be generalized to attempt the convertInitializerTo for any type. I'm not really sure why the existing code seems to special case the string cast cases when convertInitializerTo seems like it should generally handle this sort of thing. llvm-svn: 243722
* docs: Add information about helper scripts to HowToReleaseLLVM pageTom Stellard2015-07-311-47/+10
| | | | | | Differential Revision: http://reviews.llvm.org/D10081 llvm-svn: 243720
* AMDGPU/SI: Remove unused pattern for f32 constant loadsTom Stellard2015-07-311-1/+0
| | | | | | | | | | Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11603 llvm-svn: 243719
* [ARM] Lower modulo operation to generate __aeabi_divmod on AndroidSumanth Gundapaneni2015-07-312-3/+6
| | | | | | | | | | | | | | For a modulo (reminder) operation, clang -target armv7-none-linux-gnueabi generates "__modsi3" clang -target armv7-none-eabi generates "__aeabi_idivmod" clang -target armv7-linux-androideabi generates "__modsi3" Android bionic libc doesn't provide a __modsi3, instead it provides a "__aeabi_idivmod". This patch fixes the LLVM ARMISelLowering to generate the correct call when ever there is a modulo operation. Differential Revision: http://reviews.llvm.org/D11661 llvm-svn: 243717
* MIR Parser: Report an error when a constant pool item is redefined.Alex Lorenz2015-07-303-4/+34
| | | | llvm-svn: 243696
* MIR Parser: Report an error when a virtual register is redefined.Alex Lorenz2015-07-303-4/+34
| | | | llvm-svn: 243695
* fix memcpy/memset/memmove lowering when optimizing for sizeSanjay Patel2015-07-304-61/+24
| | | | | | | | | | | | | | | | | | | | Fixing MinSize attribute handling was discussed in D11363. This is a prerequisite patch to doing that. The handling of OptSize when lowering mem* functions was broken on Darwin because it wants to ignore -Os for these cases, but the existing logic also made it ignore -Oz (MinSize). The Linux change demonstrates a widespread problem. The backend doesn't usually recognize the MinSize attribute by itself; it assumes that if the MinSize attribute exists, then the OptSize attribute must also exist. Fixing this more generally will be a follow-on patch or two. Differential Revision: http://reviews.llvm.org/D11568 llvm-svn: 243693
* [libFuzzer] fix the strncmp interceptor -- it should respect short strings. Kostya Serebryany2015-07-303-3/+31
| | | | llvm-svn: 243691
* Fix TableGen code generation for ReadNone attribute.Eric Christopher2015-07-301-1/+1
| | | | | | Patch by Pete Abred! llvm-svn: 243689
* enable fast-math-flag propagation to DAG nodesSanjay Patel2015-07-301-1/+1
| | | | | | | | | | | This uncovered latent bugs previously: http://reviews.llvm.org/D10403 ...but it's time to try again because internal tests aren't finding more. If time passes and no other bugs are reported, we can remove this cl::opt. llvm-svn: 243687
* Enable dfsan for aarch64Adhemerval Zanella2015-07-301-0/+4
| | | | | | This patch enable DFSan memory transformation for aarch64 (39-bit VMA). llvm-svn: 243684
* Add a TargetMachine hook that verifies DataLayout compatibilityMehdi Amini2015-07-302-0/+13
| | | | | | | | | | | | | Summary: Also provide the associated assertion when CodeGen starts. Reviewers: echristo Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11654 From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 243682
* [SLP vectorizer]: Choose the best consecutive candidate to pair with a store ↵Wei Mi2015-07-302-7/+56
| | | | | | | | | | | | | instruction. The patch changes the SLPVectorizer::vectorizeStores to choose the immediate succeeding or preceding candidate for a store instruction when it has multiple consecutive candidates. In this way it has better chance to find more slp vectorization opportunities. Differential Revision: http://reviews.llvm.org/D10445 llvm-svn: 243666
* Fix lli with OrcLazyJIT: the default DataLayout was used.Mehdi Amini2015-07-301-0/+1
| | | | | | | Set the correct one using the TargetMachine instead. From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 243664
* AMDGPU: Set SubRegIndex size and offsetMatt Arsenault2015-07-301-2/+1
| | | | | | | | I'm not sure what reasons the comment here could have had for not setting these. Without these set, there is an assertion hit during DWARF emission. llvm-svn: 243661
* AMDGPU: Fix unreachable when emitting binary debug infoMatt Arsenault2015-07-301-1/+33
| | | | | | | | | | | Copy implementation of applyFixup from AArch64 with AArch64 bits ripped out. Tests will be included with a later commit. Several other problems must be fixed before binary debug info emission will work. llvm-svn: 243660
* MIR Serialization: Serialize the machine basic block's successor weights.Alex Lorenz2015-07-307-2/+193
| | | | | Reviewers: Duncan P. N. Exon Smith llvm-svn: 243659
* [COFF] Add IMAGE_SCN_TYPE_NOLOAD to SectionCharacteristicsDavid Majnemer2015-07-303-0/+3
| | | | llvm-svn: 243658
* AMDGPU/SI: Simplify moveSMRDToVALU()Tom Stellard2015-07-301-11/+9
| | | | | | | | | | | | | | | Summary: Replace the switch on instruction opcode with a switch on register size. This way we don't need to update the switch statement when we add new SMRD variants. Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11601 llvm-svn: 243652
* AMDGPU/SI: Remove isTriviallyReMaterializable() function from SIInstrInfoTom Stellard2015-07-302-15/+0
| | | | | | | | | | | | | | Summary: This function is never called. isReallyTriviallyReMaterializable() is the function that should be implemented instead. Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11620 llvm-svn: 243651
* [mips] Fix out-of-date debug information in test file.Vasileios Kalintiris2015-07-301-6/+8
| | | | | | | | Update the debug info in the check-lines because the change in r243638 introduced a constant initialization before the prologue's end as part of a register spill. llvm-svn: 243640
* MCJITTests/MCJITCAPITest.cpp: Try to appease i686-win32.NAKAMURA Takumi2015-07-301-0/+1
| | | | llvm-svn: 243639
OpenPOWER on IntegriCloud