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* [libFuzzer] mention more trophies and improve the link formattingKostya Serebryany2015-10-121-5/+8
| | | | llvm-svn: 250076
* combine predicates; NFCISanjay Patel2015-10-121-4/+1
| | | | llvm-svn: 250075
* Turn const/const& into value type for BlockFrequency in functions of this ↵Cong Hou2015-10-122-15/+13
| | | | | | class. Also fix a naming issue. NFC. llvm-svn: 250074
* [llvm-symbolizer] Reverting r250067Colin LeMahieu2015-10-125-33/+3
| | | | llvm-svn: 250072
* AMDGPU: Register some more passes so -print-before worksMatt Arsenault2015-10-121-0/+2
| | | | llvm-svn: 250071
* Enable verifier after PeepholeOptimizerMatt Arsenault2015-10-121-1/+1
| | | | | | | No tests fail with this enabled so I assume it was an accident that it isn't enabled now. llvm-svn: 250070
* Don't call PrepareEHLandingPad on non EH padsReid Kleckner2015-10-121-2/+3
| | | | | | | | This was a minor bug in r249492. Calling PrepareEHLandingPad on a non-landingpad was a no-op, but it attempted to get the generic pointer register class, which apparently doesn't exist for some targets. llvm-svn: 250068
* [llvm-symbolizer] Add -print-address optionHemant Kulkarni2015-10-124-0/+30
| | | | | | Differential Revision http://reviews.llvm.org/D13518 llvm-svn: 250067
* [WinEH] Remove CatchObjRecoverIdxDavid Majnemer2015-10-124-16/+5
| | | | | | | CatchObjRecoverIdx was used for the old scheme, it is no longer relevant. llvm-svn: 250065
* fix typos; NFCSanjay Patel2015-10-121-3/+2
| | | | llvm-svn: 250059
* [mips][micromips] Initial support for micrmomips DSP instructions and ↵Zoran Jovanovic2015-10-1212-6/+94
| | | | | | | | addu.qb implementation Differential Revision: http://reviews.llvm.org/D12798 llvm-svn: 250058
* [Debug] Look through bitcasts to find argument registersOliver Stannard2015-10-122-19/+58
| | | | | | | | | | On targets where f32 is not legal, we have to look through a BITCAST SDNode to find the register that an argument is stored in when emitting debug info, or we will not be able to emit a DW_AT_location for it. Differential Revision: http://reviews.llvm.org/D13005 llvm-svn: 250056
* [mips][FastISel] Clang-format switch statement. NFC.Vasileios Kalintiris2015-10-121-10/+10
| | | | llvm-svn: 250053
* [AArch64]Fix bug in function names in test caseJun Bum Lim2015-10-121-4/+4
| | | | | | | Functions in this test case need to be renamed as its names are the same as the instructions we are comparing with. llvm-svn: 250052
* fix capitalization; NFCSanjay Patel2015-10-121-2/+2
| | | | llvm-svn: 250049
* Fix rename() sometimes failing if another process uses openFileForRead()Greg Bedwell2015-10-123-10/+142
| | | | | | | | | | | | | | | | | | | On Windows, fs::rename() could fail is another process was reading the file at the same time using fs::openFileForRead(). In most cases the user wouldn't notice as fs::rename() will continue to retry for 2000ms. Typically this is enough for the read to complete and a retry to succeed, but if the disk is being it too hard then the response time might be longer than the retry time and the rename would fail with a permission error. Add FILE_SHARE_DELETE to the sharing flags for CreateFileW() in fs::openFileForRead() and try ReplaceFileW() prior to MoveFileExW() in fs::rename(). Based on an initial patch by Edd Dawson! Differential Revision: http://reviews.llvm.org/D13647 llvm-svn: 250046
* [mips][ias] Implement macro expansion when bcc has an immediate where a ↵Daniel Sanders2015-10-124-2/+207
| | | | | | | | | | | | | | register belongs. Summary: Fixes PR24915. Reviewers: vkalintiris Subscribers: emaste, seanbruno, llvm-commits Differential Revision: http://reviews.llvm.org/D13533 llvm-svn: 250042
* [mips] Whitespace cleanup in MIPS16 tests to reduce noise in following ↵Daniel Sanders2015-10-123-267/+267
| | | | | | | | changes. NFC. Mostly tabs -> spaces and double spacing. llvm-svn: 250041
* [mips] Clean up most macro expansions to use the emit*() functions.Daniel Sanders2015-10-121-287/+163
| | | | | | | | | | Reviewers: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D13591 llvm-svn: 250040
* [mips] Handle undef when extracting subregs from FP64 registers.Daniel Sanders2015-10-122-4/+26
| | | | | | | | | | | | | | | Summary: This removes unnecessary instructions when extracting from an undefined register and also fixes a crash for O32 when passing undef to a double argument in held in integer registers. Reviewers: vkalintiris Subscribers: llvm-commits, zoran.jovanovic, petarj Differential Revision: http://reviews.llvm.org/D13467 llvm-svn: 250039
* GlobalOpt does not treat externally_initialized globals correctlyOliver Stannard2015-10-123-1/+42
| | | | | | | | GlobalOpt currently merges stores into the initialisers of internal, externally_initialized globals, but should not do so as the value of the global may change between the initialiser and any code in the module being run. llvm-svn: 250035
* [ARM] Mark Swift MISched model as incompleteJames Molloy2015-10-121-0/+1
| | | | | | | | | | | The Swift Machine Scheduler Model is incomplete. There are instructions missing which can trigger the "incomplete machine model" abort. This was observed when a downstream SchedMachineModel was added to the ARM target. Patch by Christof Douma! llvm-svn: 250033
* [LoopVectorize] Shrink integer operations into the smallest type possibleJames Molloy2015-10-124-11/+595
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | C semantics force sub-int-sized values (e.g. i8, i16) to be promoted to int type (e.g. i32) whenever arithmetic is performed on them. For targets with native i8 or i16 operations, usually InstCombine can shrink the arithmetic type down again. However InstCombine refuses to create illegal types, so for targets without i8 or i16 registers, the lengthening and shrinking remains. Most SIMD ISAs (e.g. NEON) however support vectors of i8 or i16 even when their scalar equivalents do not, so during vectorization it is important to remove these lengthens and truncates when deciding the profitability of vectorization. The algorithm this uses starts at truncs and icmps, trawling their use-def chains until they terminate or instructions outside the loop are found (or unsafe instructions like inttoptr casts are found). If the use-def chains starting from different root instructions (truncs/icmps) meet, they are unioned. The demanded bits of each node in the graph are ORed together to form an overall mask of the demanded bits in the entire graph. The minimum bitwidth that graph can be truncated to is the bitwidth minus the number of leading zeroes in the overall mask. The intention is that this algorithm should "first do no harm", so it will never insert extra cast instructions. This is why the use-def graphs are unioned, so that subgraphs with different minimum bitwidths do not need casts inserted between them. This algorithm works hard to reduce compile time impact. DemandedBits are only queried if there are extends of illegal types and if a truncate to an illegal type is seen. In the general case, this results in a simple linear scan of the instructions in the loop. No non-noise compile time impact was seen on a clang bootstrap build. llvm-svn: 250032
* [X86] Add XSAVE intrinsic familyAmjad Aboud2015-10-1215-23/+311
| | | | | | | | | | | | Add intrinsics for the XSAVE instructions (XSAVE/XSAVE64/XRSTOR/XRSTOR64) XSAVEOPT instructions (XSAVEOPT/XSAVEOPT64) XSAVEC instructions (XSAVEC/XSAVEC64) XSAVES instructions (XSAVES/XSAVES64/XRSTORS/XRSTORS64) Differential Revision: http://reviews.llvm.org/D13012 llvm-svn: 250029
* [x86] PR24562: fix incorrect folding of PSHUFB nodes with a mask where all ↵Andrea Di Biagio2015-10-122-3/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | indices have the most significant bit set. This patch fixes a problem in function 'combineX86ShuffleChain' that causes a chain of shuffles to be wrongly folded away when the combined shuffle mask has only one element. We may end up with a combined shuffle mask of one element as a result of multiple calls to function 'canWidenShuffleElements()'. Function canWidenShuffleElements attempts to simplify a shuffle mask by widening the size of the elements being shuffled. For every pair of shuffle indices, function canWidenShuffleElements checks if indices refer to adjacent elements. If all pairs refer to "adjacent" elements then the shuffle mask is safely widened. As a consequence of widening, we end up with a new shuffle mask which is half the size of the original shuffle mask. The byte shuffle (pshufb) from test pr24562.ll has a mask of all SM_SentinelZero indices. Function canWidenShuffleElements would combine each pair of SM_SentinelZero indices into a single SM_SentinelZero index. So, in a logarithmic number of steps (4 in this case), the pshufb mask is simplified to a mask with only one index which is equal to SM_SentinelZero. Before this patch, function combineX86ShuffleChain wrongly assumed that a mask of size one is always equivalent to an identity mask. So, the entire shuffle chain was just folded away as the combined shuffle mask was treated as a no-op mask. With this patch we know check if the only element of a combined shuffle mask is SM_SentinelZero. In case, we propagate a zero vector. Differential Revision: http://reviews.llvm.org/D13364 llvm-svn: 250027
* Test commitZlatko Buljan2015-10-121-1/+0
| | | | llvm-svn: 250026
* cmake: Avoid leading space in LLVM_DEFINITIONS.Pawel Bylica2015-10-121-1/+5
| | | | | | | | | | Summary: Unnecessary space at the beginning of LLVM_DEFINITIONS in cmake shared files can break projects that use the variable. Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D13432 llvm-svn: 250025
* [SystemZ] testcase MC/SystemZ/insn-good-z13.s extended.Jonas Paulsson2015-10-121-7/+59
| | | | | | | | | New instructions using floating point registers have been added, to check that AsmParser can deal with fp regs in vector instructions. This tests r249810. llvm-svn: 250023
* [MISched] Python script to check coverage of misched infoJames Molloy2015-10-121-0/+77
| | | | | | | | | | | | This script prints a CSV of all misched models of a target when given the output of the debug output of subtarget using: llvm-tblgen --gen-subtarget --debug-only=subtarget-emitter ... With thanks to Dave Estes for mentioning the idea at the 2014 LLVM Developers' Meeting. Patch by Christof Douma! llvm-svn: 250020
* SCEV: Allow simple AddRec * Parameter products in delinearizationTobias Grosser2015-10-123-11/+141
| | | | | | | | | This patch also allows the -delinearize pass to delinearize expressions that do not have an outermost SCEVAddRec expression. The SCEV::delinearize infrastructure allowed this since r240952, but the -delinearize pass was not updated yet. llvm-svn: 250018
* [X86] Use u8imm for the immediate type for all shift and rotate ↵Craig Topper2015-10-121-70/+70
| | | | | | instructions. This way the assembler will perform range checking. Believe this matches gas behavior. llvm-svn: 250016
* [X86] Add support to assembler and MCInst lowering to use the other vmovq ↵Craig Topper2015-10-122-24/+28
| | | | | | %xmmX, %xmmX encoding if it would be a shorter VEX encoding. llvm-svn: 250014
* [X86] Cleanup formatting a bit. NFCCraig Topper2015-10-121-14/+14
| | | | llvm-svn: 250013
* [X86] Change the immediate for IN/OUT instructions to u8imm so the assembly ↵Craig Topper2015-10-123-12/+22
| | | | | | parser will check the size. llvm-svn: 250012
* [X86] Add some instruction aliases to get the assembly parser table to favor ↵Craig Topper2015-10-122-63/+31
| | | | | | | | arithmetic instructions with 8-bit immediates over the forms that implicitly use the ax/eax/rax. This allows us to remove the explicit code for working around the existing priority llvm-svn: 250011
* [llvm-rtdyld] General modernization/cleanup in preparation for (bigger) changes.Davide Italiano2015-10-121-19/+14
| | | | llvm-svn: 250004
* [Bugpoint] Get rid of dead code. No functional change.Davide Italiano2015-10-111-19/+0
| | | | llvm-svn: 249999
* [X86] Fix CMP and TEST with al/ax/eax/rax to not mark EFLAGS as a use or ↵Craig Topper2015-10-111-27/+34
| | | | | | al/ax/eax/rax as a def. Probably doesn't have a functional affect since these aren't used in isel. llvm-svn: 249994
* [DAGCombiner] Improved FMA combine support for vectorsSimon Pilgrim2015-10-112-184/+221
| | | | | | | | Enabled constant canonicalization for all constants. Improved combining of constant vectors. llvm-svn: 249993
* [X86] Completed SHL cost model testsSimon Pilgrim2015-10-111-1/+399
| | | | | | As discussed in D8690. llvm-svn: 249990
* [X86] Remove special validation for INT immediate operand from AsmParser. ↵Craig Topper2015-10-115-27/+15
| | | | | | | | Instead mark its operand type as u8imm which will cause it to fail to match. This is more consistent with other instruction behavior. This also fixes a bug where negative immediates below -128 were not being reported as errors. llvm-svn: 249989
* [X86] Renamed SHL cost model testsSimon Pilgrim2015-10-111-0/+0
| | | | | | | | Matches naming conventions for ASHR/LSHR cost tests As discussed in D8690. llvm-svn: 249984
* [X86] Added LSHR cost model testsSimon Pilgrim2015-10-111-0/+400
| | | | | | | | There are several dodgy costings due to AVX1 legalizing 256-bit integer vectors that need fixing. As discussed in D8690. llvm-svn: 249983
* [X86] Added ASHR cost model testsSimon Pilgrim2015-10-111-0/+392
| | | | | | | | There are several dodgy costings due to AVX1 legalizing 256-bit integer vectors that need fixing. As discussed in D8690. llvm-svn: 249981
* [TableGen] Add a space between type and '*' in front of a variable name in ↵Craig Topper2015-10-111-1/+1
| | | | | | output file. While there replace type with 'auto' since there's a cast on the right side of the assignment. NFC llvm-svn: 249980
* [X86] Simplify immediate range checking code.Craig Topper2015-10-112-18/+13
| | | | llvm-svn: 249979
* [DAGCombiner] Tidyup FMINNUM/FMAXNUM constant foldingSimon Pilgrim2015-10-111-14/+14
| | | | | | | | Enable constant folding for vector splats as well as scalars. Enable constant canonicalization for all scalar and vector constants. llvm-svn: 249978
* [InstCombine][X86][XOP] Combine XOP integer vector comparisons to native IRSimon Pilgrim2015-10-112-0/+262
| | | | | | We now have lowering support for XOP PCOM/PCOMU instructions. llvm-svn: 249977
* [X86][XOP] Added support for the lowering of 128-bit vector integer ↵Simon Pilgrim2015-10-117-154/+116
| | | | | | | | comparisons to XOP PCOM/PCOMU instructions. The XOP vector integer comparisons can deal with all signed/unsigned comparison cases directly and can be easily commuted as well (D7646). llvm-svn: 249976
* [ProfileData] Test commit for slingnNathan Slingerland2015-10-111-0/+1
| | | | | | This is a test of the LLVM commit system. In the event of a real commit there would be some useful code changes. llvm-svn: 249972
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