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* [X86] FileCheckize one of the rotate tests.Craig Topper2017-02-201-2/+4
| | | | llvm-svn: 295681
* [IndVars] Add an assertSanjoy Das2017-02-201-0/+3
| | | | | | | We've already checked that the loop is in simplify form before, but a little paranoia never hurt anyone. llvm-svn: 295680
* [IR/Verifier] List the CU we weren't able to find in `llvm.dbg.cu`.Davide Italiano2017-02-203-6/+5
| | | | llvm-svn: 295678
* MemorySSA: Add support for renaming uses in the updater.Daniel Berlin2017-02-205-31/+102
| | | | | | | | | | | | | | Summary: This lets one add aliasing stores to the updater. (i'm next going to move the creation/etc functions to the updater) Reviewers: george.burgess.iv Subscribers: llvm-commits, Prazek Differential Revision: https://reviews.llvm.org/D30154 llvm-svn: 295677
* [X86] FileCheckize one of the rotate tests.Craig Topper2017-02-201-7/+23
| | | | llvm-svn: 295676
* Fix use-after-free found by ASANSteven Wu2017-02-201-1/+1
| | | | | | | DenseMap::lookup returns copy of the value in the map. Returning the address of the temporary return value will cause use-after-free. llvm-svn: 295675
* [AVX-512] Add a few more patterns for selecting masked vpternlog with ↵Craig Topper2017-02-202-0/+88
| | | | | | broadcast loads where the passthru operand is not operand 0. llvm-svn: 295673
* [X86] Tidyup combineExtractVectorElt. NFCI.Simon Pilgrim2017-02-201-8/+9
| | | | | | | | Pull out repeated code for extraction index operand and source vector value type. Use isNullConstant helper to check for zero extraction index. llvm-svn: 295670
* [X86][SSE] Regenerate extracted bitcasted constant tests and add 32-bit test ↵Simon Pilgrim2017-02-201-6/+31
| | | | | | target llvm-svn: 295669
* [globalisel] OperandPredicateMatcher's shouldn't need to generate the ↵Daniel Sanders2017-02-202-21/+22
| | | | | | | | | | | | | | | | | | | | | | | | MachineOperand expr. NFC Summary: Each OperandPredicateMatcher shouldn't need to know how to generate the expression to reference a MachineOperand. The OperandMatcher should provide it. In addition to separating responsibilities, this also lays some groundwork for decoupling source patterns from destination patterns to allow invented operands or operands provided by GlobalISel's equivalent to the ComplexPattern<> class. Depends on D29709 Reviewers: t.p.northover, ab, rovka, qcolombet, aditya_nandakumar Reviewed By: ab Subscribers: dberris, kristof.beyls, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D29710 llvm-svn: 295668
* [X86][SSE] Regenerate re-materialized store tests and add 64-bit test targetSimon Pilgrim2017-02-201-11/+57
| | | | llvm-svn: 295666
* [X86][SSE] Regenerate vselect widening tests and add 32-bit test targetSimon Pilgrim2017-02-201-18/+91
| | | | llvm-svn: 295665
* [ARM] GlobalISel: Don't select atomic loadsDiana Picus2017-02-201-0/+6
| | | | | | | | | | | | | | | There used to be a check in the IRTranslator that prevented us from having to deal with atomic loads/stores. That check has been removed in r294993 and the AArch64 backend was updated accordingly. This commit does the same thing for the ARM backend. In general, in the ARM backend we introduce fences during the atomic expand pass, so we don't have to worry about atomics, *except* for the 32-bit ARMv8 target, which handles atomics more like AArch64. Since we don't want to worry about that yet, just bail out of instruction selection if we find any atomic loads. llvm-svn: 295662
* [globalisel] Separate the SelectionDAG importer from the emitter. NFCDaniel Sanders2017-02-201-5/+11
| | | | | | | | | | | | | | | | Summary: In the near future the rules will be sorted between these two steps to ensure that more important rules are not prevented by less important ones. Reviewers: t.p.northover, ab, rovka, qcolombet, aditya_nandakumar Reviewed By: ab Subscribers: dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D29709 llvm-svn: 295661
* [X86] Fix EXTRACT_VECTOR_ELT with variable index from v32i16 and v64i8 vector.Igor Breger2017-02-208-228/+512
| | | | | | | | | | | | Its more profitable to go through memory (1 cycles throughput) than using VMOVD + VPERMV/PSHUFB sequence ( 2/3 cycles throughput) to implement EXTRACT_VECTOR_ELT with variable index. IACA tool was used to get performace estimation (https://software.intel.com/en-us/articles/intel-architecture-code-analyzer) For example for var_shuffle_v16i8_v16i8_xxxxxxxxxxxxxxxx_i8 test from vector-shuffle-variable-128.ll I get 26 cycles vs 79 cycles. Removing the VINSERT node, we don't need it any more. Differential Revision: https://reviews.llvm.org/D29690 llvm-svn: 295660
* [SLP] Additional test for vectorization of cal/invoke args vectorizationAlexey Bataev2017-02-201-0/+95
| | | | llvm-svn: 295657
* [X86][AVX512] Add support for ASHR v2i64/v4i64 support without VLXSimon Pilgrim2017-02-207-27/+44
| | | | | | | | Use v8i64 ASHR instructions if we don't have VLX. Differential Revision: https://reviews.llvm.org/D28537 llvm-svn: 295656
* [ARM] Add a div regression test for Cortex-M23Sanne Wouda2017-02-201-0/+67
| | | | | | | | | | | | | | | | Summary: This file was missed in the commit for Cortex-M23 and Cortex-M33 support. See https://reviews.llvm.org/D29073?id=85814 . Reviewers: rengolin, javed.absar, samparker Reviewed By: samparker Subscribers: llvm-commits, aemerson Differential Revision: https://reviews.llvm.org/D30162 llvm-svn: 295655
* Strip trailing whitespace.Simon Pilgrim2017-02-201-1/+1
| | | | llvm-svn: 295653
* [SelectionDAG] Add scalarization support for ISD::*_EXTEND_VECTOR_INREG opcodes.Simon Pilgrim2017-02-203-0/+154
| | | | | | Thanks to Mikael Holmén for the initial test case llvm-svn: 295652
* AArch64AsmParser: tablegen the isBranchTarget helper functionsSjoerd Meijer2017-02-202-37/+18
| | | | | | | | | Use tablegen to autogenerate isBranchtarget helper functions. This is a cleanup that removes almost identical functions that differ only in a few constants. Differential Revision: https://reviews.llvm.org/D30160 llvm-svn: 295649
* [mips] Add test for mul macro variantsSimon Dardis2017-02-201-0/+154
| | | | llvm-svn: 295648
* llvm/examples/Kaleidoscope/BuildingAJIT: More fixup corresponding to r295636.NAKAMURA Takumi2017-02-205-10/+10
| | | | | | I missed updating them since I just ran check-llvm (with examples) in r295645. llvm-svn: 295646
* llvm/examples/Kaleidoscope/include/KaleidoscopeJIT.h: Fixup corresponding to ↵NAKAMURA Takumi2017-02-201-2/+2
| | | | | | r295636. llvm-svn: 295645
* [X86][AVX] Extend hasVEX_WPrefix bit to accept WIG value (W Ignore) + update ↵Ayman Musa2017-02-204-315/+321
| | | | | | | | | | | all AVX instructions with the new value. Add WIG value to all of AVX instructions which ignore the W-bit in their encoding, instead of giving them the default value of 0. This patch is needed for a follow up work on EVEX2VEX pass (replacing EVEX encoded instructions with their corresponding VEX version when possible). Differential Revision: https://reviews.llvm.org/D29876 llvm-svn: 295643
* [SLP] nullptr'ize initial value in `findBuildAggregate()`, NFC.Alexey Bataev2017-02-201-1/+1
| | | | | | Initial value of V is sett nullptr, as it is not used. llvm-svn: 295642
* [SLP] Rework `findBuildAggregate()` from ercursive form to iterative, NFC.Alexey Bataev2017-02-201-9/+12
| | | | | | | | | | Reviewers: mkuper Subscribers: llvm-commits, mzolotukhin Differential Revision: https://reviews.llvm.org/D30103 llvm-svn: 295641
* [AVX-512] Add more patterns to fold masked VPTERNLOG with load when the ↵Craig Topper2017-02-202-8/+54
| | | | | | passthru isn't operand 0. llvm-svn: 295640
* [AVX-512] Add tests for missed opportunities to fold masked VPTERNLOG with ↵Craig Topper2017-02-201-0/+59
| | | | | | load when the passthru op isn't operand 0. llvm-svn: 295639
* [AVX-512] Fix mistake in the immediate swizzle for some of the VPTERNLOG ↵Craig Topper2017-02-202-3/+3
| | | | | | patterns. llvm-svn: 295638
* [AVX-512] Use a better immediate in the VPTERNLOG commuting tests so its ↵Craig Topper2017-02-201-160/+160
| | | | | | easier to spot bad swizzling. llvm-svn: 295637
* [Orc] Rename ObjectLinkingLayer -> RTDyldObjectLinkingLayer.Lang Hames2017-02-207-30/+30
| | | | | | | | | | The current ObjectLinkingLayer (now RTDyldObjectLinkingLayer) links objects in-process using MCJIT's RuntimeDyld class. In the near future I hope to add new object linking layers (e.g. a remote linking layer that links objects in the JIT target process, rather than the client), so I'm renaming this class to be more descriptive. llvm-svn: 295636
* [AVX-512] Add more VPTERNLOG patterns to enable folding of broadcast loads ↵Craig Topper2017-02-202-38/+57
| | | | | | that aren't in operand 2. llvm-svn: 295634
* [X86] Use memory form of shift right by 1 when the rotl immediate is one ↵Craig Topper2017-02-202-11/+11
| | | | | | | | less than the operation size. An earlier commit already did this for the register form. llvm-svn: 295626
* [X86] Add test cases showing missed opportunities to use rotate right by 1 ↵Craig Topper2017-02-201-0/+83
| | | | | | instructions when operation reads/writes memory. llvm-svn: 295625
* s/REQUIRES: Asserts/REQUIRES: asserts/Daniel Jasper2017-02-191-1/+1
| | | | | | Other than this, we consistently use lower case. llvm-svn: 295623
* [AVX-512] Remove AddedComplexity from masked operations. The size of the ↵Craig Topper2017-02-191-32/+16
| | | | | | patterns already increases their priority. llvm-svn: 295619
* [X86] Use peekThroughOneUseBitcasts helper. NFCI.Simon Pilgrim2017-02-191-10/+5
| | | | llvm-svn: 295618
* [X86] Prefer static_cast<> to C-style cast. NFCI.Davide Italiano2017-02-191-3/+5
| | | | llvm-svn: 295617
* [AVX-512] Disable peephole optimizations on the VPTERNLOG commute test. Add ↵Craig Topper2017-02-192-1/+51
| | | | | | new patterns to enable isel to fold the loads on it own. llvm-svn: 295616
* [AArch64] Prefer static_cast<> to C-style cast. NFCI.Davide Italiano2017-02-191-2/+4
| | | | llvm-svn: 295615
* [X86][SSE] Use getTargetConstantBitsFromNode to find zeroable shuffle elements.Simon Pilgrim2017-02-192-39/+33
| | | | | | | | Replaces existing approach that could only search BUILD_VECTOR nodes. Requires getTargetConstantBitsFromNode to discriminate cases with all/partial UNDEF bits in each element - this should also be useful when we get around to supporting getTargetShuffleMaskIndices with UNDEF elements. llvm-svn: 295613
* [AVX-512] Add patterns to recognize masked vpternlog when the passthrough ↵Craig Topper2017-02-192-4/+43
| | | | | | | | operand is not operand 0. This uses a SDNodeXForm to swizzle the appropriate immediate bits to allow this to be matched. llvm-svn: 295612
* [AVX-512] Add test cases that show failure to select masked VPTERNLOG when a ↵Craig Topper2017-02-191-0/+26
| | | | | | select is used to force the passthru operand to be not operand 0. llvm-svn: 295611
* [X86][SSE] Enable initial support for domain crossing at high shuffle ↵Simon Pilgrim2017-02-192-14/+14
| | | | | | | | | | combine depths. As discussed on D27692, this permits another domain to be used to combine a shuffle at high depths. We currently set the required depth at 4 or more combined shuffles, this is probably too high for most targets but is a good starting point and already helps avoid a number of costly variable shuffles. llvm-svn: 295608
* Remove redundant call to GluedNodes.back() [NFC]Artyom Skrobov2017-02-191-2/+1
| | | | llvm-svn: 295607
* [X86][SSE] Generalize INSERTPS/SHUFPS/SHUFPD combines across domains.Simon Pilgrim2017-02-191-14/+23
| | | | | | Relax the INSERTPS/SHUFPS/SHUFPD combines to support integer inputs if permitted. llvm-svn: 295606
* [llvm-cov] Respect Windows line endings when parsing demangled symbols.Igor Kudrin2017-02-191-1/+3
| | | | | | Differential Revision: https://reviews.llvm.org/D30096 llvm-svn: 295605
* [X86][SSE] Add domain crossing support for target shuffle combines.Simon Pilgrim2017-02-191-36/+48
| | | | | | | | Add the infrastructure to flag whether float and/or int domains are permitable. A future patch will enable domain crossing based off shuffle depth and the value types of the source vectors. llvm-svn: 295604
* Removed extra ';'Simon Pilgrim2017-02-191-1/+1
| | | | llvm-svn: 295603
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