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* InstCombine: fix extraction when performing vector/array punningEugene Leviant2017-02-172-1/+17
| | | | | | Differential revision: https://reviews.llvm.org/D29491 llvm-svn: 295429
* [IR][X86] Simplify some AutoUpgrade code slightly. NFCCraig Topper2017-02-171-3/+2
| | | | llvm-svn: 295426
* [IR][X86] Rename an AutoUpgrade helper function to more accurately match ↵Craig Topper2017-02-171-6/+6
| | | | | | what intrinsics it handles. NFC llvm-svn: 295425
* [IR][X86] Move X86 specific portions of UpgradeIntrinsicFunction1 to a ↵Craig Topper2017-02-171-233/+248
| | | | | | | | couple helper functions. NFC This enables some early outs to avoid repeatedly using IsX86 check to qualify. I hope to continue to improve this to shorten the lengths of some of the string comparisons. llvm-svn: 295424
* Go binding: Add methods for missing PassManagerBuilder C APIsAndrew Wilkins2017-02-171-0/+20
| | | | | | | | Patch by Ryuichi Hayashida! Differential Revision: http://reviews.llvm.org/D30042 llvm-svn: 295420
* [JumpThreading] Re-enable JumpThreading for guardsSanjoy Das2017-02-176-15/+440
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: JumpThreading for guards feature has been reverted at https://reviews.llvm.org/rL295200 due to the following problem: the feature used the following algorithm for detection of diamond patters: 1. Find a block with 2 predecessors; 2. Check that these blocks have a common single parent; 3. Check that the parent's terminator is a branch instruction. The problem is that these checks are insufficient. They may pass for a non-diamond construction in case if those two predecessors are actually the same block. This may happen if parent's terminator is a br (either conditional or unconditional) to a block that ends with "switch" instruction with exactly two branches going to one block. This patch re-enables the JumpThreading for guards and fixes this issue by adding the check that those found predecessors are actually different blocks. This guarantees that parent's terminator is a conditional branch with exactly 2 different successors, which is now ensured by assertions. It also adds two more tests for this situation (with parent's terminator being a conditional and an unconditional branch). Patch by Max Kazantsev! Reviewers: anna, sanjoy, reames Reviewed By: sanjoy Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D30036 llvm-svn: 295410
* Revert "[Hexagon] Start using regmasks on calls"Rafael Espindola2017-02-1720-272/+118
| | | | | | | | | | This reverts commit r295371. It broke windows bots: http://bb.pgr.jp/builders/ninja-clang-i686-msc19-R/builds/11402/steps/test-llvm/logs/stdio llvm-svn: 295402
* [XRAY] [x86_64] Adding a Flight Data filetype reader to the llvm-xray Trace ↵Dean Michael Berris2017-02-176-23/+334
| | | | | | | | | | | | | | | | | | | | | | | | implementation. Summary: The file type packs function trace data onto disk from potentially multiple threads that are aggregated and flushed during the course of an instrumented program's runtime. It is named FDR mode or Flight Data recorder as an analogy to plane blackboxes, which instrument a running system without access to IO. The writer code is defined in compiler-rt in xray_fdr_logging.h/cc Reviewers: rSerge, kcc, dberris Reviewed By: dberris Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29697 llvm-svn: 295397
* Move test to X86 subdirectory for bot failuresTeresa Johnson2017-02-171-0/+0
| | | | | | Second attempt at fixing bot failures from r295384. llvm-svn: 295395
* [x86] Give this test a triple so that we don't have to cope with twoChandler Carruth2017-02-171-1/+3
| | | | | | different asm comment syntaxes. llvm-svn: 295394
* [CMake] Add variable IOS to iOS toolchainChris Bieneman2017-02-171-0/+1
| | | | | | This is useful for some edge cases where detecting things gets tricky. Specifically LLDB needs this to support iOS because CMake doesn't support running tests using obj-c code. llvm-svn: 295392
* Attempt to fix bot failures by adding -mtriple to llc invocationTeresa Johnson2017-02-171-1/+1
| | | | | | | Failures on hexagon from test added with r295384, e.g.: http://lab.llvm.org:8011/builders/llvm-hexagon-elf/builds/3793 llvm-svn: 295389
* Bug 31948: Fix assertion when bitcasting constantexpr pointersMatt Arsenault2017-02-174-0/+32
| | | | llvm-svn: 295387
* FileCheck-ize some tests in test/CodeGen/X86/Chandler Carruth2017-02-176-32/+55
| | | | | | | | Patch by Jorge Gorbe! Differential Revision: https://reviews.llvm.org/D29807 llvm-svn: 295386
* Handle link of NoDebug CU with a CU that has debug emission enabledTeresa Johnson2017-02-173-1/+95
| | | | | | | | | | | | | | | | | | | | | | | | Summary: This is an issue both with regular and Thin LTO. When we link together a DICompileUnit that is marked NoDebug (e.g when compiling with -g0 but applying an AutoFDO profile, which requires location tracking in the compiler) and a DICompileUnit with debug emission enabled, we can have failures during dwarf debug generation. Specifically, when we have inlined from the NoDebug compile unit into the debug compile unit, we can fail during construction of the abstract and inlined scope DIEs. This is because the SPMap does not include NoDebug CUs (they are skipped in the debug_compile_units_iterator). This patch fixes the failures by skipping locations from NoDebug CUs when extracting lexical scopes. Reviewers: dblaikie, aprantl Subscribers: mehdi_amini, llvm-commits Differential Revision: https://reviews.llvm.org/D29765 llvm-svn: 295384
* [IR] Fix some Clang-tidy modernize and Include What You Use warnings; other ↵Eugene Zelenko2017-02-1715-151/+228
| | | | | | minor fixes (NFC). llvm-svn: 295383
* [pdb] Add the ability to resolve TypeServer PDBs.Zachary Turner2017-02-1623-16/+502
| | | | | | | | | | | | | | Some PDBs or object files can contain references to other PDBs where the real type information lives. When this happens, all type indices in the original PDB are meaningless because their records are not there. With this patch we add the ability to pull type info from those secondary PDBs. Differential Revision: https://reviews.llvm.org/D29973 llvm-svn: 295382
* [LSR] Prevent formula with SCEVAddRecExpr type of Reg from Sibling loopsWei Mi2017-02-162-0/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In rL294814, we allow formula with SCEVAddRecExpr type of Reg from loops other than current loop. This is good for the case when induction variable of outerloop being used in expr in innerloop. But it is very bad to allow such Reg from sibling loop because we may need to add lsr.iv in other sibling loops when scev expanding those SCEVAddRecExpr type exprs. For the testcase below, one loop can be inserted with a bunch of lsr.iv because of LSR for other loops. // The induction variable j from a loop in the middle will have initial // value generated from previous sibling loop and exit value used by its // next sibling loop. void goo(long i, long j); long cond; void foo(long N) { long i = 0; long j = 0; i = 0; do { goo(i, j); i++; j++; } while (cond); i = 0; do { goo(i, j); i++; j++; } while (cond); i = 0; do { goo(i, j); i++; j++; } while (cond); i = 0; do { goo(i, j); i++; j++; } while (cond); i = 0; do { goo(i, j); i++; j++; } while (cond); i = 0; do { goo(i, j); i++; j++; } while (cond); } The fix is to only allow formula with SCEVAddRecExpr type of Reg from current loop or its parents. Differential Revision: https://reviews.llvm.org/D30021 llvm-svn: 295378
* Fix -Wunused-lambda-capture by removing some unused lambda capturesDavid Blaikie2017-02-161-2/+2
| | | | llvm-svn: 295373
* [MachinePipeliner] Remove redundant destructor. NFC.Benjamin Kramer2017-02-161-8/+1
| | | | llvm-svn: 295372
* [Hexagon] Start using regmasks on callsKrzysztof Parzyszek2017-02-1620-118/+272
| | | | | | All the cool targets are doing it... llvm-svn: 295371
* Change default TimerGroup singleton to use magic staticsErich Keane2017-02-161-16/+3
| | | | | | | | | | | TimerGroup was showing up on a leak in valigrind, and used some pretty complex code to implement a singleton. This patch replaces the implementation with a vastly simpler one. Differential Revision: https://reviews.llvm.org/D28367 llvm-svn: 295370
* [RDF] Aggregate shadow phi uses into one cluster when propagating live infoKrzysztof Parzyszek2017-02-162-70/+68
| | | | llvm-svn: 295366
* [X86][SSE] Add PR31309 test case (load-extend i32 to i128).Simon Pilgrim2017-02-161-0/+40
| | | | llvm-svn: 295363
* AMDGPU: Remove llvm.AMDGPU.cube intrinsicMatt Arsenault2017-02-168-49/+27
| | | | llvm-svn: 295359
* AMDGPU: Remove llvm.AMDGPU.rsq intrinsicMatt Arsenault2017-02-163-15/+0
| | | | llvm-svn: 295358
* Re-apply r282920 "X86: Allow conditional tail calls in Win64 "leaf" ↵Hans Wennborg2017-02-163-8/+31
| | | | | | | | | | functions (PR26302)" The original commit was reverted in r283329 due to a miscompile in Chromium. That turned out to be the same issue as PR31257, which was fixed in r295262. llvm-svn: 295357
* [RDF] Differentiate between defining and clobbering nodesKrzysztof Parzyszek2017-02-164-13/+88
| | | | | | | | | | Defining nodes should not alias with one another, while clobbering nodes can. When pushing defs on stacks, push clobbers first, link non-clobbering defs, then push the defs. The data flow in a statement is now: uses -> clobbers -> defs. llvm-svn: 295356
* Refactor DebugHandlerBase a bit to common non-debug-having-function filteringDavid Blaikie2017-02-167-55/+61
| | | | llvm-svn: 295354
* InstCombine: Canonicalize fast fmuladd to fmul + faddMatt Arsenault2017-02-162-4/+20
| | | | llvm-svn: 295353
* [RDF] Move normalize(RegisterRef) to PhysicalRegisterInfoKrzysztof Parzyszek2017-02-166-45/+36
| | | | | | Remove the duplicate from DFG and make some members of PRI private. llvm-svn: 295351
* x86 interrupt calling convention: only save xmm registers if the target ↵Andrea Di Biagio2017-02-163-2/+27
| | | | | | | | | | | | | | | | | | supports SSE The existing code always saves the xmm registers for 64-bit targets even if the target doesn't support SSE (which is common for kernels). Thus, the compiler inserts movaps instructions which lead to CPU exceptions when an interrupt handler is invoked. This commit fixes this bug by returning a register set without xmm registers from getCalleeSavedRegs and getCallPreservedMask for such targets. Patch by Philipp Oppermann. Differential Revision: https://reviews.llvm.org/D29959 llvm-svn: 295347
* [x86] add more tests of select of constants; NFCSanjay Patel2017-02-161-10/+168
| | | | llvm-svn: 295346
* [DAGCombiner] Support {a|s}ext, {a|z|s}ext load nodes in load combineArtur Pilipenko2017-02-169-166/+57
| | | | | | | | | | | | Resubmit -r295314 with PowerPC and AMDGPU tests updated. Support {a|s}ext, {a|z|s}ext load nodes as a part of load combine patters. Reviewed By: filcab Differential Revision: https://reviews.llvm.org/D29591 llvm-svn: 295336
* [AArch64] AArch64AsmParser clean up of isImmediate functions. NFCSjoerd Meijer2017-02-163-151/+18
| | | | | | | | | | | Regression test neon-diagnostics.s needed changing because it now produces a more specific diagnostic about the immediate ranges. One change in the expected error message is not obvious, but there multiple candidate and it happens to pick the immediate diagnostic. Differential Revision: https://reviews.llvm.org/D29939 llvm-svn: 295331
* [WebAssembly] Add a cast to void to fix an unused private member warning, ↵Dan Gohman2017-02-161-1/+3
| | | | | | for now. llvm-svn: 295327
* [X86] Remove local areOnlyUsersOf helper and use SDNode::areOnlyUsersOf instead.Simon Pilgrim2017-02-161-9/+1
| | | | llvm-svn: 295326
* Remove uses of deprecated std::random_shuffle in the LLVM code base. ↵Marshall Clow2017-02-164-14/+16
| | | | | | Reviewed as https://reviews.llvm.org/D29780. llvm-svn: 295325
* [ARM] GlobalISel: Select floating point loadsDiana Picus2017-02-162-10/+87
| | | | llvm-svn: 295321
* Rever -r295314 "[DAGCombiner] Support {a|s}ext, {a|z|s}ext load nodes in ↵Artur Pilipenko2017-02-167-40/+147
| | | | | | | | load combine" This change causes some of AMDGPU and PowerPC tests to fail. llvm-svn: 295316
* [DAGCombiner] Support {a|s}ext, {a|z|s}ext load nodes in load combineArtur Pilipenko2017-02-167-147/+40
| | | | | | | | | | Support {a|s}ext, {a|z|s}ext load nodes as a part of load combine patters. Reviewed By: filcab Differential Revision: https://reviews.llvm.org/D29591 llvm-svn: 295314
* [ARM] GlobalISel: Select G_SEQUENCE and G_EXTRACTDiana Picus2017-02-162-0/+123
| | | | | | | | Since they're only used for passing around double precision floating point values into the general purpose registers, we'll lower them to VMOVDRR and VMOVRRD. llvm-svn: 295310
* [ARM] GlobalISel: Select double G_FADD and copiesDiana Picus2017-02-162-6/+63
| | | | | | Just use VADDD if available, bail out if not. llvm-svn: 295309
* [ARM] GlobalISel: Assert that we don't use the FPR bank if we don't have VFPDiana Picus2017-02-162-4/+18
| | | | llvm-svn: 295308
* [ARM] GlobalISel: Add reg bank mappings for G_SEQUENCE and G_EXTRACTDiana Picus2017-02-162-0/+58
| | | | | | | Support G_SEQUENCE and G_EXTRACT as needed for passing double precision floating point values in the soft-fp float mode. llvm-svn: 295306
* [ARM] GlobalISel: Make the FPR bank 64-bit wideDiana Picus2017-02-163-7/+56
| | | | | | | Also add mappings for single and double precision FP, and use them for G_FADD and G_LOAD. llvm-svn: 295302
* [ARM] GlobalISel: Legalize 64-bit G_FADD and G_LOADDiana Picus2017-02-162-0/+36
| | | | | | | | For now we just mark them as legal all the time and let the other passes bail out if they can't handle it. In the future, we'll want to move more of the brains into the legalizer. llvm-svn: 295300
* RWMutex.h: Use llvm-config.h instead of config.h in installed headers.NAKAMURA Takumi2017-02-161-1/+1
| | | | llvm-svn: 295297
* [ARM] GlobalISel: Lower double precision FP argsDiana Picus2017-02-164-9/+212
| | | | | | | | | | | | | | For the hard float calling convention, we just use the D registers. For the soft-fp calling convention, we use the R registers and move values to/from the D registers by means of G_SEQUENCE/G_EXTRACT. While doing so, we make sure to honor the endianness of the target, since the CCAssignFn doesn't do that for us. For pure soft float targets, we still bail out because we don't support the libcalls yet. llvm-svn: 295295
* [AVX-512][InstCombine] Teach InstCombine to optimize 512-bit packss/packus ↵Craig Topper2017-02-163-8/+132
| | | | | | intrinsics like it does 128/256-bit. llvm-svn: 295294
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