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* Segmented stacks: omit __morestack call when there's no frame.Tim Northover2014-05-225-18/+77
| | | | | | Patch by Florian Zeitz llvm-svn: 209436
* ARM64: these work tooTim Northover2014-05-221-2/+0
| | | | llvm-svn: 209430
* Yes they doTim Northover2014-05-221-1/+0
| | | | llvm-svn: 209429
* ARM64: model pre/post-indexed operations properly.Tim Northover2014-05-229-336/+241
| | | | | | | | | | We should be keeping track of the writeback on these instructions, otherwise we're relying on LLVM's stupidity for correct code. Fortunately, the MC layer can now handle all required constraints, which means we can get rid of the CodeGen only PseudoInsts too. llvm-svn: 209426
* ARM64: separate load/store operands to simplify assemblerTim Northover2014-05-2215-2702/+2537
| | | | | | | | | | | | | | | | | | | This changes ARM64 to use separate operands for each component of an address, and look for separate '[', '$Rn, ..., ']' tokens when parsing. This allows us to do away with quite a bit of special C++ code to handle monolithic "addressing modes" in the MC components. The more incremental matching of the assembler operands also allows for better diagnostics when LLVM is presented with invalid input. Most of the complexity here is with the register-offset instructions, which were extremely dodgy beforehand: even when the instruction used wM, LLVM's model had xM as an operand. We papered over this discrepancy before, but that approach doesn't work now so I split them into separate X and W variants. llvm-svn: 209425
* [mips] Make unalignedload.ll test stricter and easier to modify for ↵Daniel Sanders2014-05-221-12/+29
| | | | | | | | | | | | | | | | | | | | | | MIPS32r6/MIPS64r6 Summary: * Split into two functions, one to test each struct. * R0 and R2 must be defined by an lw with a %got reference to the correct symbol. * Test for $4 (first argument) where appropriate instead of accepting any register. * Test that the two lbu's are correctly combined into $4 Depends on D3844 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3845 llvm-svn: 209424
* [mips] Change lwl and lwr in inlineasm_constraint.ll to lwDaniel Sanders2014-05-221-3/+3
| | | | | | | | | | | | | | | | | Summary: lwl and lwr are not available in MIPS32r6/MIPS64r6. The purpose of the test is to check that the '$1' expands to '0($x)' rather than to test something related to the lwl or lwr instructions so we can simply switch to lw. Depends on D3842 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3844 llvm-svn: 209423
* [mips] Use addiu in inline assembly tests since addi is not available in all ↵Daniel Sanders2014-05-2210-42/+42
| | | | | | | | | | | | | | | | | | | | | ISA's Summary: This patch is necessary so that they do not fail on MIPS32r6/MIPS64r6 when -integrated-as is enabled by default and we correctly detect the host CPU. No functional change since these tests are testing the behaviour of the constraint used for the third operand rather than the mnemonic. Depends on D3842 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3843 llvm-svn: 209421
* Extend sys::getHostCPUFeatures to work on AArch64 platformsBradley Smith2014-05-221-1/+37
| | | | llvm-svn: 209420
* [mips][mips64r6] addi is not available on MIPS32r6/MIPS64r6Daniel Sanders2014-05-224-2/+30
| | | | | | | | | | | | Summary: Depends on D3787. Tablegen will raise an assertion without it. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3842 llvm-svn: 209419
* [mips][mips64r6] Test that paired single instructions are invalidDaniel Sanders2014-05-222-1/+44
| | | | | | | | | | | | | | Summary: These emit the 'unknown instruction' instead of the correct error because they have not been implemented in LLVM for any MIPS ISA. Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3841 llvm-svn: 209418
* [mips][mips64r6] Add b[on]vcDaniel Sanders2014-05-2210-53/+683
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
* ARM64: assert if we see i64 -> i64 extend in the DAG.Tim Northover2014-05-221-4/+2
| | | | | | | | Should be no change in behaviour, but it makes the intended functionality a bit clearer and means we only have to reason about real extend operations. llvm-svn: 209409
* AArch64/ARM64: enable more AArch64 tests.Tim Northover2014-05-223-6/+9
| | | | llvm-svn: 209408
* MC: initialise MCAsmParser variableSaleem Abdulrasool2014-05-221-2/+2
| | | | | | | Properly initialise HadError to false during construction. Detected as use-of-uninitialised variable by MSan! llvm-svn: 209393
* Remove unused variable.Eric Christopher2014-05-221-1/+0
| | | | llvm-svn: 209391
* ARM: introduce llvm.arm.undefined intrinsicSaleem Abdulrasool2014-05-225-5/+24
| | | | | | | | | | | | This intrinsic permits the emission of platform specific undefined sequences. ARM has reserved the 0xde opcode which takes a single integer parameter (ignored by the CPU). This permits the operating system to implement custom behaviour on this trap. The llvm.arm.undefined intrinsic is meant to provide a means for generating the target specific behaviour from the frontend. This is particularly useful for Windows on ARM which has made use of a series of these special opcodes. llvm-svn: 209390
* R600/SI: Match fp_to_uint / uint_to_fp for f64Matt Arsenault2014-05-223-2/+25
| | | | llvm-svn: 209388
* MC: formalise some assertions into proper errorsSaleem Abdulrasool2014-05-228-8/+61
| | | | | | | | | Now that clang can be used as an assembler via the IAS, invalid assembler inputs would cause the assertions to trigger. Although we cannot recover from the errors here, nor provide caret diagnostics, attempt to handle them slightly more gracefully by reporting a fatal error. llvm-svn: 209387
* Override runOnMachineFunction for ARMISelDAGToDAG so that we canEric Christopher2014-05-221-0/+7
| | | | | | reset the subtarget on each function. llvm-svn: 209386
* Override runOnMachineFunction for X86ISelDAGToDAG so that we canEric Christopher2014-05-221-0/+7
| | | | | | reset the subtarget on each function. llvm-svn: 209384
* Avoid using subtarget features when adding X86 specific passes toEric Christopher2014-05-225-14/+17
| | | | | | the pass pipeline. llvm-svn: 209382
* Remove extra local variable.Eric Christopher2014-05-221-2/+1
| | | | llvm-svn: 209381
* Rename createGlobalBaseRegPass -> createX86GlobalBaseRegPass to makeEric Christopher2014-05-223-4/+4
| | | | | | it obvious that it's a target specific pass. llvm-svn: 209380
* Fix typo.Eric Christopher2014-05-225-5/+5
| | | | llvm-svn: 209377
* Avoid using subtarget features when initializing the pass pipelineEric Christopher2014-05-222-12/+17
| | | | | | on PPC. llvm-svn: 209376
* Reset the subtarget for DAGToDAG on every iteration of runOnMachineFunction.Eric Christopher2014-05-225-47/+47
| | | | | | | This required updating the generated functions and TD file accordingly to be pointers rather than const references. llvm-svn: 209375
* Reset the subtarget for DAGToDAG on every iteration of runOnMachineFunction.Eric Christopher2014-05-221-1/+2
| | | | llvm-svn: 209374
* Sort includes.Eric Christopher2014-05-221-1/+1
| | | | llvm-svn: 209373
* DebugInfo: Simplify dead variable collection slightly.David Blaikie2014-05-221-3/+1
| | | | | | | | constructSubprogramDIE was already called for every subprogram in every CU when the module was started - there's no need to call it again at module finalization. llvm-svn: 209372
* Fix a bug in SCEV's backedge taken count computation from my prior fix in Jan.Andrew Trick2014-05-222-8/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This has to do with the trip count computation for loops with multiple exits, which is quite subtle. Most passes just ask for a single trip count number, so we must be conservative assuming any exit could be taken. Normally, we rely on the "exact" trip count, which was correctly given as "unknown". However, SCEV also gives a "max" back-edge taken count. The loops max BE taken count is conservatively a maximum over the max of each exit's non-exiting iterations count. Note that some exit tests can be skipped so the max loop back-edge taken count can actually exceed the max non-exiting iterations for some exits. However, when we know the loop *latch* cannot be skipped, we can directly use its max taken count disregarding other exits. I previously took the minimum here without checking whether the other exit could be skipped. The correct, and simpler thing to do here is just to directly use the loop latch's max non-exiting iterations as the loops max back-edge count. In the problematic test case, the first loop exit had a max of zero non-exiting iterations, but could be skipped. The loop latch was known not to be skipped but had max of one non-exiting iteration. We incorrectly claimed the loop back-edge could be taken zero times, when it is actually taken one time. Fixes Loop %for.body.i: <multiple exits> Unpredictable backedge-taken count. Loop %for.body.i: max backedge-taken count is 1. llvm-svn: 209358
* Similar to bitcast, treat addrspacecast as a foldable operand.Eli Bendersky2014-05-222-0/+39
| | | | | | | | Added a test sink-addrspacecast.ll to verify this change. Patch by Jingyue Wu. llvm-svn: 209343
* Fix compilation issues.Eric Christopher2014-05-213-4/+7
| | | | llvm-svn: 209342
* Make early if conversion dependent upon the subtarget and addEric Christopher2014-05-2110-23/+38
| | | | | | | a subtarget hook to enable. Unconditionally add to the pass pipeline for targets that might want to use it. No functional change. llvm-svn: 209340
* Group the scheduling functions together.Eric Christopher2014-05-211-4/+5
| | | | llvm-svn: 209339
* Revert "DebugInfo: Don't put fission type units in comdat sections."David Blaikie2014-05-216-48/+20
| | | | | | | | | This reverts commit r208930, r208933, and r208975. It seems not all fission consumers are ready to handle this behavior. Reverting until tools are brought up to spec. llvm-svn: 209338
* MC: correct IMAGE_REL_ARM_MOV32T relocation emissionSaleem Abdulrasool2014-05-213-6/+44
| | | | | | | | | | | | This corrects the emission of IMAGE_REL_ARM_MOV32T relocations. Previously, we were avoiding the high portion of the relocation too early. If there was a section-relative relocation with an offset greater than 16-bits (65535), you would end up truncating the high order bits of the offset. Allow the current relocation representation to flow through out the MC layer to the object writer. Use the new ability to restrict recorded relocations to avoid emitting the relocation into the final object. llvm-svn: 209337
* MC: introduce ability to restrict recorded relocationsSaleem Abdulrasool2014-05-212-1/+3
| | | | | | | | | Add support to allow a target specific COFF object writer to restrict the recorded resolutions in the emitted object files. This is motivated by the need in Windows on ARM, where an intermediate relocation needs to be prevented from being emitted in the object file. llvm-svn: 209336
* DebugInfo: Use the SPMap to find the parent CU of inlined functions as they ↵David Blaikie2014-05-213-14/+136
| | | | | | | | | | | | | | | | may not be in the current CU Committed in r209178 then reverted in r209251 due to LTO breakage, here's a proper fix for the case of the missing subprogram DIE. The DIEs were there, just in other compile units. Using the SPMap we can find the right compile unit to search for and produce cross-unit references to describe this kind of inlining. One existing test case needed to be updated because it had a function that wasn't in the CU's subprogram list, so it didn't appear in the SPMap. llvm-svn: 209335
* R600: Add comment describing problems with LowerConstantInitializerMatt Arsenault2014-05-211-0/+10
| | | | llvm-svn: 209333
* R600: Partially fix constant initializers for structs and vectors.Matt Arsenault2014-05-213-6/+88
| | | | | | | This should extend the current workaround to work with structs that only contain legal, scalar types. llvm-svn: 209331
* R600: Add failing testcases for constant initializers.Matt Arsenault2014-05-212-13/+47
| | | | | | | | Constant initializers involving illegal types hit an assertion. Patch by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 209330
* Remove getTargetLowering from TargetPassConfig as the target loweringEric Christopher2014-05-213-11/+10
| | | | | | can change depending upon subtarget/subtarget features for a function. llvm-svn: 209329
* Remove unused member variable from hexagon pass.Eric Christopher2014-05-211-4/+3
| | | | llvm-svn: 209328
* DebugInfo: Ensure concrete out of line variables from inlined functions ↵David Blaikie2014-05-213-21/+30
| | | | | | reference their abstract origins. llvm-svn: 209327
* [X86] Fix a bug in the lowering of BLENDI introduced in r209043.Quentin Colombet2014-05-213-12/+48
| | | | | | | | | | | | | | | | | | | ISD::VSELECT mask uses 1 to identify the first argument and 0 to identify the second argument. On the other hand, BLENDI uses 0 to identify the first argument and 1 to identify the second argument. Fix the generation of the blend mask to account for this difference. The bug did not show up with r209043, because we were not checking for the actual arguments of the blend instruction! This commit also fixes the test cases. Note: The same mask works for the BLENDr variant because the arguments are swapped during instruction selection (see the BLENDXXrr patterns). <rdar://problem/16975435> llvm-svn: 209324
* Move MCOptions that aren't shared between programs into their specificEric Christopher2014-05-215-27/+20
| | | | | | program and have them initialize the MCOptions struct explicitly. llvm-svn: 209321
* Make a couple of command lines static and remove an unnecessaryEric Christopher2014-05-211-6/+4
| | | | | | initialization. llvm-svn: 209320
* DebugInfo: Simplify subprogram declaration creation/references and ↵David Blaikie2014-05-215-38/+36
| | | | | | | | accidentally refix PR11300. Also simplifies the linkage name handling a little too. llvm-svn: 209311
* Use cast<> instead of unchecked dyn_castMatt Arsenault2014-05-211-1/+1
| | | | llvm-svn: 209310
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