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* Replace MachineInstr* with MachineInstr& in TargetInstrInfo, NFCKrzysztof Parzyszek2016-08-017-44/+44
| | | | | | There were a few cases introduced with the modulo scheduler. llvm-svn: 277358
* [Hexagon] Check for offset overflow when reserving scavenging slotsKrzysztof Parzyszek2016-08-013-2/+179
| | | | | | | | | Scavenging slots were only reserved when pseudo-instruction expansion in frame lowering created new virtual registers. It is possible to still need a scavenging slot even if no virtual registers were created, in cases where the stack is large enough to overflow instruction offsets. llvm-svn: 277355
* Add removed inline-assembly-comment test from r277146Nirav Dave2016-08-011-0/+22
| | | | llvm-svn: 277349
* [mips][fastisel] Correct argument lowering for (f64, f64, i32) and similar.Daniel Sanders2016-08-012-29/+84
| | | | | | | | | | | | | | | Summary: Allocating an AFGR64 shadows two GPR32's instead of just one. This fixes an LNT regression detected by our internal buildbots. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: https://reviews.llvm.org/D23012 llvm-svn: 277348
* [AMDGPU] refactor DS instruction definitions. NFC.Valery Pykhtin2016-08-019-626/+906
| | | | | | Differential revision: https://reviews.llvm.org/D22522 llvm-svn: 277344
* [X86] Use implicit masking of SHLD/SHRD shift double instructionsSimon Pilgrim2016-08-012-16/+20
| | | | | | Similar to the regular shift instructions, SHLD/SHRD only use the bottom bits of the shift value llvm-svn: 277341
* Fixed test check ordering issue on windows buildbotsSimon Pilgrim2016-08-011-20/+20
| | | | llvm-svn: 277337
* Fixed MSVC out of range shift warningSimon Pilgrim2016-08-011-1/+1
| | | | llvm-svn: 277333
* [SimplifyCFG] Fix nasty RAUW bug from r277325James Molloy2016-08-012-4/+31
| | | | | | | | | | | | | | | Using RAUW was wrong here; if we have a switch transform such as: 18 -> 6 then 6 -> 0 If we use RAUW, while performing the second transform the *transformed* 6 from the first will be also replaced, so we end up with: 18 -> 0 6 -> 0 Found by clang stage2 bootstrap; testcase added. llvm-svn: 277332
* [AArch64] Return the correct size for TLSDESC_CALLSEQDiana Picus2016-08-012-0/+87
| | | | | | | | | | | | | | The branch relaxation pass is computing the wrong offsets because it assumes TLSDESC_CALLSEQ eats up 4 bytes, when in fact it is lowered to an instruction sequence taking up 16 bytes. This can become a problem in huge files with lots of TLS accesses, as it may slowly move branch targets out of the range computed by the branch relaxation pass. Fixes PR24234 https://llvm.org/bugs/show_bug.cgi?id=24234 Differential Revision: https://reviews.llvm.org/D22870 llvm-svn: 277331
* [AVX-512] Fix a test missed in r277327.Craig Topper2016-08-011-1/+1
| | | | llvm-svn: 277330
* [SimplifyCFG] Try and pacify buildbots after r277325James Molloy2016-08-011-8/+8
| | | | | | It looks like the two independent parts of the rotate operation (a lshr and shl) are being reordered on some bots. Add CHECK-DAGs to account for this. llvm-svn: 277329
* [AVX-512] Fix duplicate column in AVX512 execution dependency table that was ↵Craig Topper2016-08-0118-600/+260
| | | | | | preventing VMOVDQU32/VMOVDQA32 from being recognized. Fix a bug in the code that stops execution dependency fix from turning operations on 32-bit integer element types into operations on 64-bit integer element types. llvm-svn: 277327
* [X86] Regenerate a test to pick up shuffle comments that were added at some ↵Craig Topper2016-08-011-2/+2
| | | | | | point. llvm-svn: 277326
* [SimplifyCFG] Range reduce switchesJames Molloy2016-08-012-0/+301
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a switch is sparse and all the cases (once sorted) are in arithmetic progression, we can extract the common factor out of the switch and create a dense switch. For example: switch (i) { case 5: ... case 9: ... case 13: ... case 17: ... } can become: if ( (i - 5) % 4 ) goto default; switch ((i - 5) / 4) { case 0: ... case 1: ... case 2: ... case 3: ... } or even better: switch ( ROTR(i - 5, 2) { case 0: ... case 1: ... case 2: ... case 3: ... } The division and remainder operations could be costly so we only do this if the factor is a power of two, and emit a right-rotate instead of a divide/remainder sequence. Dense switches can be lowered significantly better than sparse switches and can even be transformed into lookup tables. llvm-svn: 277325
* [mips] Clang generates unaligned offset for MSA instruction st.dHrvoje Varga2016-08-017-49/+537
| | | | | | Differential Revision: https://reviews.llvm.org/D19475 llvm-svn: 277323
* [AArch64] Register passes so they can be run by llcDiana Picus2016-08-0167-196/+213
| | | | | | | | | | | | | | Initialize all AArch64-specific passes in the TargetMachine so they can be run by llc. This can lead to conflicts in opt with some command line options that share the same name as the pass, so I took this opportunity to do some cleanups: * rename all relevant command line options from "aarch64-blah" to "aarch64-enable-blah" and update the tests accordingly * run clang-format on their declarations * move all these declarations to a common place (the TargetMachine) as opposed to having them scattered around (AArch64BranchRelaxation and AArch64AddressTypePromotion were the only offenders) llvm-svn: 277322
* [AVX-512] Teach X86InstrInfo::getLargestLegalSuperClass to inflate to ↵Craig Topper2016-08-012-40/+62
| | | | | | | | FR32X/FR64X if AVX512 is supported and VR128X/VR256X if VLX is supported. Had to update a stack folding test to clobber the other 16 registers since this now made them get used instead of spilling. llvm-svn: 277321
* [AVX512] Replace scalar fp arithmetic intrinsics with native IR in an AVX512 ↵Craig Topper2016-08-011-24/+40
| | | | | | | | test. The intrinsics aren't lowered to AVX512 instructions. The intrinsics really should be removed and autoupgraded. llvm-svn: 277320
* [AVX-512] Use FR32X/FR64X/VR128X/VR256X register classes in addRegisterClass ↵Craig Topper2016-08-011-15/+30
| | | | | | if AVX512(for FR32X/FR64) or VLX(for VR128X/VR256) is supported. This is a minimal requirement to be able to allocate all 32 registers. llvm-svn: 277319
* [X86] Move mask register handling into the main switch of ↵Craig Topper2016-08-011-22/+6
| | | | | | getLoadStoreRegOpcode. No functional change intended. llvm-svn: 277318
* Revert r277313 and r277314.Sean Silva2016-08-0111-262/+27
| | | | | | | | | | | | | | | They seem to trigger an LSan failure: http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/15140/steps/check-llvm%20asan/logs/stdio Revert "Add the tests for r277313" This reverts commit r277314. Revert "CodeExtractor : Add ability to preserve profile data." This reverts commit r277313. llvm-svn: 277317
* Move this test to x86-specific directory.Sean Silva2016-08-012-0/+3
| | | | | | | | | No bots have yelled yet, but this test references an x86 intrinsic. Also, it invokes llc on x86 IR. Fixup to r277315. llvm-svn: 277316
* Fix - CodeExtractor : Inherit Target Dependent Attributes from the parent ↵Sean Silva2016-08-012-1/+56
| | | | | | | | | | | | | | | | | | | function. When extracting a set of blocks make sure to inherit all of the target dependent attributes to make sure that the function will be valid for lowering. One example is the "target-features" attribute for x86, if the extracted region has functionality that relies on a specific feature it will fail to be lowered. This also allows for extracted functions to be valid for inlining, at least back into the parent function, as the target attributes are tested when inlining for compatibility. Patch by River Riddle! Differential Revision: https://reviews.llvm.org/D22713 llvm-svn: 277315
* Add the tests for r277313Sean Silva2016-08-012-0/+67
| | | | | | Forgot to `git add` them. llvm-svn: 277314
* CodeExtractor : Add ability to preserve profile data.Sean Silva2016-08-019-27/+195
| | | | | | | | | | | Added ability to estimate the entry count of the extracted function and the branch probabilities of the exit branches. Patch by River Riddle! Differential Revision: https://reviews.llvm.org/D22744 llvm-svn: 277313
* [X86][SSE] Regenerate frem testsSimon Pilgrim2016-07-311-22/+21
| | | | llvm-svn: 277311
* [X86][SSE] Regenerate fpext testsSimon Pilgrim2016-07-311-31/+73
| | | | llvm-svn: 277310
* Fix the MemorySSA updating API to enable people to create memory accesses ↵Daniel Berlin2016-07-313-4/+46
| | | | | | before removing old ones llvm-svn: 277309
* Comment fixes to MemorySSA.hDaniel Berlin2016-07-312-2/+4
| | | | llvm-svn: 277308
* [X86] Simplify code for determing GR or FR reg classes by querying for super ↵Craig Topper2016-07-311-49/+10
| | | | | | classes instead of manually listing individual classes. llvm-svn: 277306
* [AVX512] Always use EVEX encodings for 128/256-bit move instructions in ↵Craig Topper2016-07-313-163/+155
| | | | | | getLoadStoreRegOpcode if VLX is supported. llvm-svn: 277305
* [AVX512] Add VLX packed move instructions to the execution dependency fix ↵Craig Topper2016-07-3113-262/+252
| | | | | | pass and update tests. llvm-svn: 277304
* [AVX512] Move FR32X/FR64X handling in getLoadStoreRegOpcode into the main ↵Craig Topper2016-07-311-15/+11
| | | | | | switch. No functional change intended. llvm-svn: 277303
* [AVX512] Stop treating VR512 specially in getLoadStoreRegOpcode and use the ↵Craig Topper2016-07-312-7/+5
| | | | | | regular switch which already tried to handle it, but was unreachable. This has the added benefit of enabling aligned loads/stores if the stack is aligned. llvm-svn: 277302
* [AVX512] Add X86::VR512RegClassID to X86RegisterInfo::getLargestLegalSuperClass.Craig Topper2016-07-312-11/+12
| | | | llvm-svn: 277301
* [X86] Improve 64-bit shifts on 32-bit targets (PR14593)Simon Pilgrim2016-07-314-127/+72
| | | | | | | | As discussed on PR14593, this patch adds support for lowering to SHLD/SHRD from the patterns generated by DAGTypeLegalizer::ExpandShiftWithKnownAmountBit. Differential Revision: https://reviews.llvm.org/D23000 llvm-svn: 277299
* [COFF] Expose iterators for ImportAddressTableRVADavid Majnemer2016-07-312-2/+21
| | | | | | Patch by Bandzi Michal! llvm-svn: 277298
* [COFF] Remove a duplicate import_directory_table_entry definitionDavid Majnemer2016-07-313-18/+14
| | | | | | | | We had import_directory_table_entry and coff_import_directory_table_entry, remove one. Also, factor out the logic which determins if a descriptor is a terminator. llvm-svn: 277296
* [bugpoint] Add a -Os optionDavid Majnemer2016-07-311-2/+6
| | | | llvm-svn: 277295
* [X86] Add tests for the lowering SHLD/SHRD from manual pattern similar to ↵Simon Pilgrim2016-07-312-0/+136
| | | | | | | | those generated by ExpandShiftWithKnownAmountBit Test for add(v,v) as well as shl(v,1) llvm-svn: 277293
* [AVX-512] Don't let ExeDependencyFix pass convert VPANDD/Q to VPANDPS/PD ↵Craig Topper2016-07-317-35/+77
| | | | | | | | unless DQI instructions are supported. Same for ANDN, OR, and XOR. Thanks to Igor Breger for pointing out my mistake. llvm-svn: 277292
* [X86] Add tests for the lowering SHLD/SHRD from manual patternsSimon Pilgrim2016-07-312-0/+132
| | | | | | As discussed on D23000 llvm-svn: 277291
* Fixed "copy-paste" mistake from revision 255245.Amjad Aboud2016-07-311-1/+1
| | | | llvm-svn: 277290
* AVX-512: Removed AssertZext node before TRUNCATEElena Demikhovsky2016-07-312-42/+38
| | | | | | | | Removed AssertZext node, which was inserted between X86ISD::SETCC and "truncate to i1". Differential Revision: https://reviews.llvm.org/D22850 llvm-svn: 277289
* [ADT] Add 'consume_front' and 'consume_back' methods to StringRef whichChandler Carruth2016-07-312-0/+56
| | | | | | | | | | | are very handy when parsing text. They are essentially a combination of startswith and a self-modifying drop_front, or endswith and drop_back respectively. Differential Revision: https://reviews.llvm.org/D22723 llvm-svn: 277288
* [HexagonConstPropagation] Remove dead code.Davide Italiano2016-07-301-22/+0
| | | | llvm-svn: 277285
* [HexagonBitSimplify] Remove dead code.Davide Italiano2016-07-301-18/+0
| | | | llvm-svn: 277284
* [ARMConstantIslandPass] Remove dead code.Davide Italiano2016-07-301-20/+0
| | | | llvm-svn: 277283
* [Support] Add doxygen @code tags to example code in Error comments.Lang Hames2016-07-301-5/+11
| | | | llvm-svn: 277282
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