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* Add a test case for r156840, a fix to llvm-objdump when disassembling usingKevin Enderby2012-05-151-0/+20
| | | | | | -macho to disassemble the last symbol to the end of the section. llvm-svn: 156850
* reuse the result of some expensive computations in getSignExtendExpr() and ↵Nuno Lopes2012-05-151-18/+20
| | | | | | | | getZeroExtendExpr() this gives a speedup of > 80 in a debug build in the test case of PR12825 (php_sha512_crypt_r) llvm-svn: 156849
* Extend the CoalescerPair interface to handle symmetric sub-register copies.Jakob Stoklund Olesen2012-05-152-44/+51
| | | | | | | | | | Now both SrcReg and DstReg can be sub-registers of the final coalesced register. CoalescerPair::setRegisters still rejects such copies because RegisterCoalescer doesn't yet handle them. llvm-svn: 156848
* Update MIPS' section in the release notes. Patch by Simon Atanasyan.Akira Hatanaka2012-05-151-0/+2
| | | | llvm-svn: 156847
* Add -enable-aa-sched-mi, off by default, for AliasAnalysis inside ↵Andrew Trick2012-05-151-22/+243
| | | | | | | | | | | | | | | MachineScheduler. This feature avoids creating edges in the scheduler's dependence graph for non-aliasing memory operations according to whichever alias analysis is available. It has been fully tested in Hexagon. Before making this default, it needs to be extended to handle multiple MachineMemOperands, compile time needs more evaluation, and benchmarking on X86 and ARM is needed. Patch by Sergei Larin! llvm-svn: 156842
* Fixed a bug in llvm-objdump when disassembling using -macho option for a binaryKevin Enderby2012-05-151-1/+1
| | | | | | | that has more than one symbol. The last symbol was not being disassembled to the end of the section. llvm-svn: 156840
* llvm-build: Add support for non-installed libraries (e.g., gtest).Daniel Dunbar2012-05-155-15/+47
| | | | | | | - These libraries are only reported by llvm-config when run from a development tree. llvm-svn: 156838
* llvm-build: Don't emit library information for disabled targets.Daniel Dunbar2012-05-152-1/+21
| | | | llvm-svn: 156837
* [utils] Fix Get{RepositoryPath,SourceVersion} to have a more robust is-git-svnDaniel Dunbar2012-05-152-2/+2
| | | | | | check. llvm-svn: 156836
* TableGen'erate mapping physical registers to encoding values.Jim Grosbach2012-05-153-5/+42
| | | | | | | | | | | Many targets always use the same bitwise encoding value for physical registers in all (or most) instructions. Add this mapping to the .td files and TableGen'erate the information and expose an accessor in MCRegisterInfo. patch by Tom Stellard. llvm-svn: 156829
* Allow MCCodeEmitter access to the target MCRegisterInfo.Jim Grosbach2012-05-1513-8/+30
| | | | | | | | Add the MCRegisterInfo to the factories and constructors. Patch by Tom Stellard <Tom.Stellard@amd.com>. llvm-svn: 156828
* Enable all Hexagon tests.Sirish Pande2012-05-1511-28/+18
| | | | llvm-svn: 156824
* minor simplification to code: Ty is already a SCEV type; don't need to run ↵Nuno Lopes2012-05-151-6/+3
| | | | | | getEffectiveSCEVType() twice llvm-svn: 156823
* Add some release notes about compiler-rt and libc++David Chisnall2012-05-151-0/+15
| | | | llvm-svn: 156819
* Teach SimplifyLibCalls about stpcpy.David Majnemer2012-05-152-7/+97
| | | | llvm-svn: 156815
* Remove warning about testing unsigned int with int.Bill Wendling2012-05-151-1/+1
| | | | llvm-svn: 156812
* Fixed one small stupid, but critical bug.Stepan Dyatkovskiy2012-05-152-2/+17
| | | | llvm-svn: 156810
* Rejected r156804 due to buildbots failures.Stepan Dyatkovskiy2012-05-151-35/+46
| | | | llvm-svn: 156808
* SelectionDAGBuilder::Clusterify : main functinality was replaced with ↵Stepan Dyatkovskiy2012-05-151-46/+35
| | | | | | CRSBuilder::optimize, so big part of Clusterify's code was reduced. llvm-svn: 156804
* Temporarily disable anti-dependence breaking for Mips until bug 12829 isAkira Hatanaka2012-05-151-1/+1
| | | | | | resolved. llvm-svn: 156801
* Create a struct representing register units in TableGen.Jakob Stoklund Olesen2012-05-152-35/+50
| | | | | | | | | | | | Besides the weight, we also want to store up to two root registers per unit. Most units will have a single root, the leaf register they represent. Units created for ad hoc aliasing get two roots: The two aliasing registers. The root registers can be used to compute the set of overlapping registers. llvm-svn: 156792
* Remove extraneous ';'.Bill Wendling2012-05-151-1/+1
| | | | llvm-svn: 156791
* Add a command line option to skip the delay slot filler pass entirely for Mips.Akira Hatanaka2012-05-141-0/+10
| | | | | | | | | | The purpose of this option is to silence error messages issued by machine verifier passes and enable them to run to the end. If this option is not provided, -verify-machineinstrs complains when it discovers there is a non-terminator instruction (an instruction that is in a delay slot) after the first terminator in a basic block. llvm-svn: 156790
* [Support/YAMLParser] Use rtrim on plain scalars.Michael J. Spencer2012-05-141-3/+1
| | | | llvm-svn: 156787
* [Support/COFF] Make the order of members in symbol match the standard.Michael J. Spencer2012-05-141-1/+1
| | | | llvm-svn: 156785
* Fix use of uninitialized variable.David Blaikie2012-05-141-1/+1
| | | | | | Found by GCC's maybe-uninitialized. llvm-svn: 156780
* Don't access MO reference after invalidating operand list.Jakob Stoklund Olesen2012-05-141-2/+3
| | | | | | This should unbreak llvm-x86_64-linux. llvm-svn: 156778
* Fix PR12821.Jakob Stoklund Olesen2012-05-142-1/+39
| | | | | | | RAFast must add an <imp-def> operand when it is rewriting a sub-register def that isn't a read-modify-write. llvm-svn: 156777
* Move the capture analysis from MemoryDependencyAnalysis to a more general placeChad Rosier2012-05-146-89/+128
| | | | | | | | | so that it can be reused in MemCpyOptimizer. This analysis is needed to remove an unnecessary memcpy when returning a struct into a local variable. rdar://11341081 PR12686 llvm-svn: 156776
* Revert 156634 upon request until code improvement changes are made.Brendon Cahoon2012-05-1417-3763/+343
| | | | llvm-svn: 156775
* Rename @llvm.debugger to @llvm.debugtrap.Dan Gohman2012-05-148-16/+16
| | | | llvm-svn: 156774
* Release notes for MIPS backend.Akira Hatanaka2012-05-141-4/+10
| | | | llvm-svn: 156772
* Remove a stale forward declaration.Andrew Trick2012-05-141-1/+0
| | | | llvm-svn: 156770
* Remove the expensive BitVector::operator~().Jakob Stoklund Olesen2012-05-142-8/+4
| | | | | | | Returning a temporary BitVector is very expensive. If you must, create the temporary explicitly: Use BitVector(A).flip() instead of ~A. llvm-svn: 156768
* Remove BitVector binops.Jakob Stoklund Olesen2012-05-141-18/+0
| | | | | | | | | | | These operators were crazy slow, calling malloc to return a temporary result. At the same time, they look very innocent when used in code. If you need temporary BitVectors to compute your thing, create them explicitly, and use the inplace logical operators. This makes the high cost explicit in the code. llvm-svn: 156767
* Consider ad hoc aliasing when building RegUnits.Jakob Stoklund Olesen2012-05-141-12/+41
| | | | | | | | | | | | | | | | | | | | | | | Register units can be used to compute if two registers overlap: A overlaps B iff units(A) intersects units(B). With this change, the above holds true even on targets that use ad hoc aliasing (currently only ARM). This means that register units can be used to implement regsOverlap() more efficiently, and the register allocator can use the concept to model interference. When there is no ad hoc aliasing, the register units correspond to the maximal cliques in the register overlap graph. This is optimal, no other register unit assignment can have fewer units. With ad hoc aliasing, weird things are possible, and we don't try too hard to compute the maximal cliques. The current approach is always correct, and it works very well (probably optimally) as long as the ad hoc aliasing doesn't have cliques larger than pairs. It seems unlikely that any target would need more. llvm-svn: 156763
* Record the ad hoc aliasing graph in CodeGenRegister.Jakob Stoklund Olesen2012-05-142-5/+21
| | | | | | | | | | | | | The ad hoc aliasing specified in the 'Aliases' list in .td files is currently only used by computeOverlaps(). It will soon be needed to build accurate register units as well, so build the undirected graph in CodeGenRegister::buildObjectGraph() instead. Aliasing is a symmetric relationship with only one direction specified in the .td files. Make sure both directions are represented in getExplicitAliases(). llvm-svn: 156762
* Compute topological signatures of registers.Jakob Stoklund Olesen2012-05-142-8/+76
| | | | | | | | | | | | | | | TableGen creates new register classes and sub-register indices based on the sub-register structure present in the register bank. So far, it has been doing that on a per-register basis, but that is not very efficient. This patch teaches TableGen to compute topological signatures for registers, and use that to reduce the amount of redundant computation. Registers get the same TopoSig if they have identical sub-register structure. TopoSigs are not currently exposed outside TableGen. llvm-svn: 156761
* Add BitVector::anyCommon().Jakob Stoklund Olesen2012-05-142-1/+39
| | | | | | The existing operation (A & B).any() is very slow. llvm-svn: 156760
* SwitchInst cosmetics: renamed "Hash" method to "hash"Stepan Dyatkovskiy2012-05-143-3/+3
| | | | llvm-svn: 156757
* Formatting changes. Remove the '...' placeholders.Bill Wendling2012-05-141-67/+44
| | | | llvm-svn: 156756
* Use ArrayRef instead of an explicit vector type.Bill Wendling2012-05-142-3/+3
| | | | llvm-svn: 156755
* Add blurb about Julia.Bill Wendling2012-05-141-0/+16
| | | | llvm-svn: 156754
* ReleaseNotes: Add info on PTX back-endJustin Holewinski2012-05-131-0/+15
| | | | llvm-svn: 156745
* Hexagon: Initialize TBB to 0.Benjamin Kramer2012-05-131-0/+1
| | | | | | Found by valgrind. llvm-svn: 156744
* Fix Xcode case (Upper X, lower c)Jean-Daniel Dupas2012-05-132-2/+2
| | | | llvm-svn: 156743
* ReleaseNotes: Add a note about zero_undef on llvm.cttz/ctlz. Extend x86 ↵Benjamin Kramer2012-05-131-3/+12
| | | | | | section. Add a bullet for dwarf access tables. llvm-svn: 156740
* ReleaseNotes: Add a blurb about llvm-mc -g and move inliner changes into the ↵Benjamin Kramer2012-05-131-6/+11
| | | | | | optimizer sections. Verbosify some bullets. llvm-svn: 156739
* ReleaseNotes: Document that LLVM was rewritten in python.Benjamin Kramer2012-05-131-0/+2
| | | | | | | ^~~~ llvm-build llvm-svn: 156738
* ReleaseNotes: Add bullets for removed targets. Extend the note about llvm-ld ↵Benjamin Kramer2012-05-131-13/+10
| | | | | | removal. llvm-svn: 156737
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