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* [MC] Set defaults based on section names and support name suffixesPetr Hosek2017-04-042-6/+62
| | | | | | | | | | | | | Set correct default flags and section type based on its name for .text, .data, .bss, .init_array, .fini_array, .preinit_array, .tdata, and .tbss and support section name suffixes for .data.*, .rodata.*, .text.*, .bss.*, .tdata.* and .tbss.* which matches the behavior of GAS. Fixes PR31888. Differential Revision: https://reviews.llvm.org/D30229 llvm-svn: 299484
* [AArch64] Avoid partial register deps on insertelt of load into lane 0.Ahmed Bougacha2017-04-042-16/+10
| | | | | | | | | | | | | | | This improves upon r246462: that prevented FMOVs from being emitted for the cross-class INSERT_SUBREGs by disabling the formation of INSERT_SUBREGs of LOAD. But the ld1.s that we started selecting caused us to introduce partial dependencies on the vector register. Avoid that by using SCALAR_TO_VECTOR: it's a first-class citizen that is folded away by many patterns, including the scalar LDRS that we want in this case. Credit goes to Adam for finding the issue! llvm-svn: 299482
* Change section flag character for SHF_LINK_ORDER to "o".Evgeniy Stepanov2017-04-049-23/+23
| | | | | | | | GAS uses "m" as a compatibility alias for "M" (SHF_MERGE). "o" is free, except on ia64, where it already means SHF_LINK_ORDER. llvm-svn: 299479
* [InstCombine] Add test cases for various add/subtracts of constants(scalar, ↵Craig Topper2017-04-042-0/+196
| | | | | | splat, and vector) with phis and selects. Improvements coming in a future commit. llvm-svn: 299476
* [lit] Add a minimum export implementation.Rafael Espindola2017-04-041-9/+21
| | | | llvm-svn: 299475
* [InstCombine] rename variable for easier reading; NFCSanjay Patel2017-04-041-7/+8
| | | | | | We usually give constants a 'C' somewhere in the name... llvm-svn: 299474
* [InstCombine] Turn subtract of vectors of i1 into xor like we do for scalar ↵Craig Topper2017-04-042-1/+10
| | | | | | i1. Matches what we already do for add. llvm-svn: 299472
* [AArch64] Add missing schedinfo, check completeness for Falkor.Balaram Makam2017-04-041-10/+17
| | | | llvm-svn: 299468
* [ExecutionDepsFix] Don't revisit true dependenciesKeno Fischer2017-04-042-7/+14
| | | | | | | | | | | | | | | If an instruction has a true dependency, it makes sense for to use that register for any undef read operands in the same instruction (we'll have to wait for that register to become available anyway). This logic was already implemented. However, the code would then still try to revisit that instruction and break the dependency (and always fail, since by definition a true dependency has to be live before the instruction). Avoid revisiting such instructions as a performance optimization. No functional change. Differential Revision: https://reviews.llvm.org/D30173 llvm-svn: 299467
* [InstCombine] Support folding and/or/xor with a constant vector RHS into ↵Craig Topper2017-04-044-31/+23
| | | | | | | | | | selects and phis Currently we only fold with ConstantInt RHS. This generalizes to any Constant RHS. Differential Revision: https://reviews.llvm.org/D31610 llvm-svn: 299466
* [AArch64][Fuchsia] Allow -mcmodel=kernel for --target=aarch64-fuchsiaPetr Hosek2017-04-049-19/+51
| | | | | | | | | | | This mode is just like -mcmodel=small except that it moves the thread pointer from TPIDR_EL0 to TPIDR_EL1. Patch by Roland McGrath. Differential Revision: https://reviews.llvm.org/D31624 llvm-svn: 299462
* [InstCombine] Add test cases for missing combines of phis with and/or/xor ↵Craig Topper2017-04-043-0/+204
| | | | | | with constant argument. NFC llvm-svn: 299460
* Implement host CPU detection for AArch64Yi Kong2017-04-042-4/+67
| | | | | | | | | | | | | | | | | | This shares detection logic with ARM(32), since AArch64 capable CPUs may also run in 32-bit system mode. We observe weird /proc/cpuinfo output for MSM8992 and MSM8994, where they report all CPU cores as one single model, depending on which CPU core the kernel is running on. As a workaround, we hardcode the known CPU part name for these SoCs. For big.LITTLE systems, this patch would only return the part name of the first core (usually the little core). Proper support will be added in a follow-up change. Differential Revision: D31675 llvm-svn: 299458
* Verifier: Check some amdgpu calling convention restrictionsMatt Arsenault2017-04-043-2/+70
| | | | llvm-svn: 299457
* [AArch64] Refine Falkor Machine Model - Part 2Balaram Makam2017-04-043-92/+454
| | | | llvm-svn: 299456
* [X86][inline-asm] Add support for MS 'EVEN' directiveCoby Tayree2017-04-041-1/+1
| | | | | | | | | | | | MS assembly syntax provide us with the 'EVEN' directive as a synonymous to at&t '.even'. This patch include the (small, simple) changes need to allow it. Test is provided at the following (clang-side) review: https://reviews.llvm.org/D27418 Differential Revision: https://reviews.llvm.org/D27417 llvm-svn: 299453
* [InstCombine] Add more test cases for missing combines of selects with ↵Craig Topper2017-04-043-0/+53
| | | | | | and/or/xor with constant argument. NFC llvm-svn: 299450
* [RuntimeDyld] Make RuntimeDyld honor the ProcessAllSections flag.Lang Hames2017-04-044-8/+26
| | | | | | | | | | | | | | | When the ProcessAllSections flag (introduced in r204398) is set RuntimeDyld is supposed to make a call to the client's memory manager for every section in each object that is loaded. Due to some missing checks, this was not happening in all cases. This patch adds the missing cases, and fixes the Orc unit test that verifies correct behavior for ProcessAllSections (The unit test had been silently bailing out due to an ordering issue: a change in the test order meant that this unit-test was running before the native target was registered. This issue has also been fixed in this patch). This fixes <rdar://problem/22789965> llvm-svn: 299449
* [x86] remove dead select-of-constants transform; NFCISanjay Patel2017-04-041-12/+0
| | | | | | | | https://reviews.llvm.org/D30537 / https://reviews.llvm.org/rL296977 added these transforms and other related transforms to the generic DAGCombiner (with a hook that x86 sets to true), so these patterns should not exist by the time we reach the target-specific combiner hook. llvm-svn: 299448
* [PGO] Memory intrinsic calls optimization based on profiled sizeRong Xu2017-04-0414-61/+528
| | | | | | | | | | | | | | | | | | | | | | | | This patch optimizes two memory intrinsic operations: memset and memcpy based on the profiled size of the operation. The high level transformation is like: mem_op(..., size) ==> switch (size) { case s1: mem_op(..., s1); goto merge_bb; case s2: mem_op(..., s2); goto merge_bb; ... default: mem_op(..., size); goto merge_bb; } merge_bb: Differential Revision: http://reviews.llvm.org/D28966 llvm-svn: 299446
* AMDGPU: Remove legacy export intrinsicMatt Arsenault2017-04-044-276/+4
| | | | llvm-svn: 299444
* AMDGPU: Remove legacy image intrinsicsMatt Arsenault2017-04-049-1550/+6
| | | | llvm-svn: 299443
* [X86][MS-compatability]Allow named synonymous for MS-assembly operatorsCoby Tayree2017-04-042-7/+68
| | | | | | | | | | This patch enhances X86AsmParser's immediate expression parsing abilities, to include a named synonymous for selected binary/unary bitwise operators: {and,shl,shr,or,xor,not}, ultimately achieving better MS-compatability MASM reference: https://msdn.microsoft.com/en-us/library/94b6khh4.aspx Differential Revision: D31277 llvm-svn: 299439
* Strip trailing whitespaceSimon Pilgrim2017-04-041-4/+4
| | | | llvm-svn: 299438
* [globalisel][tablegen] Fix non-determinism introduced in r299430.Daniel Sanders2017-04-041-2/+7
| | | | | | This should fix the last issue on llvm-clang-x86_64-expensive-checks-win. llvm-svn: 299436
* [globalisel][tablegen] Try to make MSVC happy with r299430Daniel Sanders2017-04-041-5/+5
| | | | | | | | Fix other cases of 'const StringRef' creeping back in at the same time. This should fix the llvm-clang-x86_64-expensive-checks-win buildbot. llvm-svn: 299433
* [X86][LLVM] Converting __mm{|256|512}_movm_epi{8|16|32|64} LLVMIR call into ↵Michael Zuckerman2017-04-0411-198/+169
| | | | | | | | | | | generic intrinsics. This patch is a part one of two reviews, one for the clang and the other for LLVM. The patch deletes the back-end intrinsics and adds support for them in the auto upgrade. Differential Revision: https://reviews.llvm.org/D31393 llvm-svn: 299432
* [tablegen][globalisel] Add support for nested instruction matching.Daniel Sanders2017-04-048-77/+408
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Lift the restrictions that prevented the tree walking introduced in the previous change and add support for patterns like: (G_ADD (G_MUL (G_SEXT $src1), (G_SEXT $src2)), $src3) -> SMADDWrrr $dst, $src1, $src2, $src3 Also adds support for G_SEXT and G_ZEXT to support these cases. One particular aspect of this that I should draw attention to is that I've tried to be overly conservative in determining the safety of matches that involve non-adjacent instructions and multiple basic blocks. This is intended to be used as a cheap initial check and we may add a more expensive check in the future. The current rules are: * Reject if any instruction may load/store (we'd need to check for intervening memory operations. * Reject if any instruction has implicit operands. * Reject if any instruction has unmodelled side-effects. See isObviouslySafeToFold(). Reviewers: t.p.northover, javed.absar, qcolombet, aditya_nandakumar, ab, rovka Reviewed By: ab Subscribers: igorb, dberris, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30539 llvm-svn: 299430
* [mips] Deal with empty blocks in the mips hazard schedulerSimon Dardis2017-04-042-11/+106
| | | | | | | | | | | | This patch teaches the hazard scheduler how to handle empty blocks when search for the next real instruction when dealing with forbidden slots. Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D31293 llvm-svn: 299427
* [X86] Add 64 bit pattern matching for PSADBWOren Ben Simhon2017-04-042-13/+388
| | | | | | | | | PSADBW pattern currently supports the 32 bit IR pattern and only GLT (greather than) comparison. The patch extends the pattern to catch also 64 bit IR pattern and includes all other comparison types (not only GLT). Differential Revision: https://reviews.llvm.org/D31577 llvm-svn: 299425
* Align all scalar numbers to LLVM_YAML_IS_FLOW_SEQUENCE_VECTORJonas Hahnfeld2017-04-0411-56/+21
| | | | | | | | | Otherwise, yamlize in YAMLTraits.h might be wrongly defined. This makes some AMDGPU tests fail when LLVM_LINK_LLVM_DYLIB is set. Differential Revision: https://reviews.llvm.org/D30508 llvm-svn: 299415
* [InstCombine] Use setAllBits in place of getAllOnesValue since we know the ↵Craig Topper2017-04-041-1/+1
| | | | | | bitwidths are the same. NFCI llvm-svn: 299413
* InstCombine: Use the InstSimplify hook for shufflevectorZvi Rackover2017-04-041-5/+4
| | | | | | | | | | | | | | Summary: Start using the recently added InstSimplify hook for shuffles in the respective InstCombine visitor. Reviewers: spatel, RKSimon, craig.topper, majnemer Reviewed By: majnemer Subscribers: majnemer, llvm-commits Differential Revision: https://reviews.llvm.org/D31526 llvm-svn: 299412
* [PDB] Save one type record copyReid Kleckner2017-04-043-21/+25
| | | | | | | | | | | | | | | | | | Summary: The TypeTableBuilder provides stable storage for type records. We don't need to copy all of the bytes into a flat vector before adding it to the TpiStreamBuilder. This makes addTypeRecord take an ArrayRef<uint8_t> and a hash code to go with it, which seems like a simplification. Reviewers: ruiu, zturner, inglorion Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D31634 llvm-svn: 299406
* [codeview] Cope with unsorted streams in type mergingReid Kleckner2017-04-037-44/+175
| | | | | | | | | | | | | | | Summary: MASM can produce type streams that are not topologically sorted. It can even produce type streams with circular references, but those are not common in practice. Reviewers: inglorion, ruiu Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D31629 llvm-svn: 299403
* [Fuzzer] Flush std::cout before aborting in CxxStringEqTestReid Kleckner2017-04-031-0/+1
| | | | | | | On Windows, abort() does not appear to flush std::cout. Should fix red sanitizer-windows bot. llvm-svn: 299398
* add/move codegen tests for and/or of setcc; NFCSanjay Patel2017-04-035-73/+173
| | | | llvm-svn: 299396
* Update stale doxygen links in ProgrammersManual.rstTim Northover2017-04-031-17/+17
| | | | | | Patch by Wei-Ren Chen. llvm-svn: 299395
* InstSimplify: Add a hook for shufflevectorZvi Rackover2017-04-034-6/+85
| | | | | | | | | | | | | | | | | | Summary: Add a hook for simplification of shufflevector's with the following rules: - Constant folding - NFC, as it was already being done by the default handler. - If only one of the operands is constant, constant fold the shuffle if the mask does not select elements from the variable operand - to show the hook is firing and affecting the test-cases. Reviewers: RKSimon, craig.topper, spatel, sanjoy, nlopes, majnemer Reviewed By: spatel Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D31525 llvm-svn: 299393
* Reland r298901 with modifications (reverted in r298932)Weiming Zhao2017-04-0318-37/+180
| | | | | | | | | | | | | | | | | | | Dont emit Mapping symbols for sections that contain only data. Summary: Dont emit mapping symbols for sections that contain only data. Reviewers: rengolin, weimingz, kparzysz, t.p.northover, peter.smith Reviewed By: t.p.northover Patched by Shankar Easwaran <shankare@codeaurora.org> Subscribers: alekseyshl, t.p.northover, llvm-commits Differential Revision: https://reviews.llvm.org/D30724 llvm-svn: 299392
* AMDGPU: Remove llvm.SI.vs.load.inputMatt Arsenault2017-04-039-32/+20
| | | | llvm-svn: 299391
* DAG: Fix missing legalization for any_extend_vector_inreg operandsMatt Arsenault2017-04-033-0/+75
| | | | llvm-svn: 299389
* [codeview] Add support for label type recordsReid Kleckner2017-04-0310-1/+66
| | | | | | MASM can produce these type records. llvm-svn: 299388
* [X86][SSE]] Lower BUILD_VECTOR with repeated elts as BUILD_VECTOR + ↵Simon Pilgrim2017-04-0312-103/+142
| | | | | | | | | | | | | | | | VECTOR_SHUFFLE It can be costly to transfer from the gprs to the xmm registers and can prevent loads merging. This patch splits vXi16/vXi32/vXi64 BUILD_VECTORS that use the same operand in multiple elements into a BUILD_VECTOR with only a single insertion of each of those elements and then performs an unary shuffle to duplicate the values. There are a couple of minor regressions this patch unearths due to some missing MOVDDUP/BROADCAST folds that I will address in a future patch. Note: Now that vector shuffle lowering and combining is pretty good we should be reusing that instead of duplicating so much in LowerBUILD_VECTOR - this is the first of several patches to address this. Differential Revision: https://reviews.llvm.org/D31373 llvm-svn: 299387
* [InstCombine] Remove canonicalization for (X & C1) | C2 --> (X | C2) & ↵Craig Topper2017-04-031-11/+0
| | | | | | | | | | (C1|C2) when C1 & C2 have common bits. It turns out that SimplifyDemandedInstructionBits will get called earlier and remove bits from C1 first. Effectively doing (X & (C1&C2)) | C2. So by the time it got to this check there could be no common bits. I think the DAGCombiner has the same check but its check can be executed because it handles demanded bits later. I'll look at it next. llvm-svn: 299384
* x86 interrupt calling convention: re-align stack pointer on 64-bit if an ↵Amjad Aboud2017-04-034-10/+30
| | | | | | | | | | | | | | | | error code was pushed The x86_64 ABI requires that the stack is 16 byte aligned on function calls. Thus, the 8-byte error code, which is pushed by the CPU for certain exceptions, leads to a misaligned stack. This results in bugs such as Bug 26413, where misaligned movaps instructions are generated. This commit fixes the misalignment by adjusting the stack pointer in these cases. The adjustment is done at the beginning of the prologue generation by subtracting another 8 bytes from the stack pointer. These additional bytes are popped again in the function epilogue. Fixes Bug 26413 Patch by Philipp Oppermann. Differential Revision: https://reviews.llvm.org/D30049 llvm-svn: 299383
* [CodeGenPrep] move aarch64-type-promotion to CGPJun Bum Lim2017-04-039-58/+374
| | | | | | | | | | | | | | | | | Summary: Move the aarch64-type-promotion pass within the existing type promotion framework in CGP. This change also support forking sexts when a new sext is required for promotion. Note that change is based on D27853 and I am submitting this out early to provide a better idea on D27853. Reviewers: jmolloy, mcrosier, javed.absar, qcolombet Reviewed By: qcolombet Subscribers: llvm-commits, aemerson, rengolin, mcrosier Differential Revision: https://reviews.llvm.org/D28680 llvm-svn: 299379
* [DAGCombine][InstCombine] Fix inverted if condition in equivalent comments ↵Craig Topper2017-04-032-2/+2
| | | | | | in DAGCombine and InstCombine. NFC llvm-svn: 299378
* Fix LLVMBuild.txt typo. NFCJoel Jones2017-04-031-1/+1
| | | | llvm-svn: 299373
* AMDGPU: Remove legacy bfe intrinsicsMatt Arsenault2017-04-0310-1252/+159
| | | | llvm-svn: 299372
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