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* Reduce malloc thrashing.Benjamin Kramer2010-10-281-1/+1
| | | | llvm-svn: 117572
* PLD, PLDW, PLI encodings, plus refactor their use of addrmode2.Jim Grosbach2010-10-284-20/+44
| | | | llvm-svn: 117571
* Aliases defined with .symver should copy the binding of the symbols they alias.Rafael Espindola2010-10-282-9/+47
| | | | | | | Move the existing patching for undefined symbols so that all the patching is done in the same function. llvm-svn: 117570
* Technically DIFile scope should also be handled here.Devang Patel2010-10-281-0/+4
| | | | llvm-svn: 117563
* rearrange ParseRegisterList.Chris Lattner2010-10-281-16/+30
| | | | llvm-svn: 117560
* refactor some code to simplify it, eliminating some owningptr's.Chris Lattner2010-10-281-65/+60
| | | | llvm-svn: 117559
* Teach the DAG combiner to fold a splat of a splat. Radar 8597790.Bob Wilson2010-10-282-24/+44
| | | | | | Also do some minor refactoring to reduce indentation. llvm-svn: 117558
* Use the IDVal directly as there's no need to convert to std::string.Roman Divacky2010-10-281-2/+2
| | | | | | Pointed out by Chris! llvm-svn: 117557
* Implement .equ directive as a synonym to .set.Roman Divacky2010-10-282-6/+11
| | | | llvm-svn: 117553
* Testcase for PR8494 (invalid bitcode crashing the bitcode reader).Duncan Sands2010-10-282-0/+2
| | | | llvm-svn: 117552
* Fix PR8494: when reading invalid bitcode, getTypeByID may returnDuncan Sands2010-10-281-2/+7
| | | | | | a null pointer. llvm-svn: 117551
* Implement R_X86_64_DTPOFF32.Rafael Espindola2010-10-282-0/+10
| | | | llvm-svn: 117548
* Implement TLSLD.Rafael Espindola2010-10-284-0/+14
| | | | llvm-svn: 117547
* Implement DTPOFF.Rafael Espindola2010-10-284-0/+16
| | | | llvm-svn: 117546
* Document LLVM_BUILD_TESTS, LLVM_INCLUDE_TESTS. New convenience targetOscar Fuentes2010-10-282-0/+17
| | | | | | UnitTests for building all the unit tests. llvm-svn: 117545
* Implement TLSLDM.Rafael Espindola2010-10-284-0/+14
| | | | llvm-svn: 117544
* Implement VK_GOTNTPOFF and switch RelocNeedsGOT to use VariantKind.Rafael Espindola2010-10-284-15/+28
| | | | llvm-svn: 117543
* Reindent.Mikhail Glushenkov2010-10-281-71/+71
| | | | llvm-svn: 117538
* Re-commit 117518 and 117519 now that ARM MC test failures are out of the way.Evan Cheng2010-10-2812-31/+96
| | | | llvm-svn: 117531
* Disable most of the ARM vfp / NEON MC tests. These are too fragile to be useful.Evan Cheng2010-10-2816-0/+30
| | | | | | | I'll work with Jim, Owen, and Bill on an alternative testing strategy until the assembly parser is available. llvm-svn: 117530
* test/Transforms/SimplifyLibCalls/floor.ll: Mark as XFAIL:win32 due to lack ↵NAKAMURA Takumi2010-10-281-0/+2
| | | | | | of nearbyintf on MSVC. [PR8466] llvm-svn: 117529
* tools/llvm-shlib/Makefile: Support for FreeBSD and OpenBSD.NAKAMURA Takumi2010-10-281-1/+4
| | | | | | | | Thanks to Yuri Gribov and Vladimir Kirillov! *BSD(s) have environ(7) in CRT startup and cannot resolve "environ" at linking llvm.so. environ(7) is used inlib/System/Unix/Program.inc. llvm-svn: 117528
* clarify that not having the ".o file writing" featureChris Lattner2010-10-281-0/+4
| | | | | | | doesn't mean that you can't get a .o file. Apparently this is confusing :) llvm-svn: 117523
* Revert 117518 and 117519 for now. They changed scheduling and cause MC tests ↵Evan Cheng2010-10-2812-96/+31
| | | | | | to fail. Ugh. llvm-svn: 117520
* - Assign load / store with shifter op address modes the right itinerary classes.Evan Cheng2010-10-2811-31/+93
| | | | | | | | | | - For now, loads of [r, r] addressing mode is the same as the [r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should identify the former case and reduce the output latency by 1. - Also identify [r, r << 2] case. This special form of shifter addressing mode is "free". llvm-svn: 117519
* Fix a major bug in operand latency computation. The use index must be adjustedEvan Cheng2010-10-281-0/+3
| | | | | | by the number of defs first for it to match the instruction itinerary. llvm-svn: 117518
* Fix pastos in handling of AVX cvttsd2si, PR8491.Dale Johannesen2010-10-283-6/+6
| | | | | | | Bruno, please review, but I'm pretty sure this is right. Patch by Alex Mac! llvm-svn: 117514
* Add correct NEON encodings for vtbl and vtbx.Owen Anderson2010-10-282-29/+131
| | | | llvm-svn: 117513
* Add correct NEON encodings for vext, vtrn, vuzp, and vzip.Owen Anderson2010-10-272-2/+221
| | | | llvm-svn: 117512
* Fix compiler warnings about signed/unsigned comparisons.Bob Wilson2010-10-271-2/+2
| | | | llvm-svn: 117511
* Teach InstCombine not to use Add and Neg on FP. PR 8490.Dale Johannesen2010-10-272-1/+28
| | | | llvm-svn: 117510
* Shifter ops are not always free. Do not fold them (especially to formEvan Cheng2010-10-274-25/+183
| | | | | | | complex load / store addressing mode) when they have higher cost and when they have more than one use. llvm-svn: 117509
* Putting r117193 back except for the compile time cost. Rather than assuming ↵Evan Cheng2010-10-271-3/+10
| | | | | | fallthroughs uses all registers, just gather the union of all successor liveins. llvm-svn: 117506
* Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, likeJim Grosbach2010-10-279-101/+94
| | | | | | | | the LDR instructions have. This makes the literal/register forms of the instructions explicit and allows us to assign scheduling itineraries appropriately. rdar://8477752 llvm-svn: 117505
* Tests for NEON encoding of vrev.Owen Anderson2010-10-271-0/+85
| | | | llvm-svn: 117502
* Provide correct encodings for NEON vcvt, which has its own special immediate ↵Owen Anderson2010-10-276-6/+139
| | | | | | | | encoding for specifying fractional bits for fixed point conversions. llvm-svn: 117501
* Trailing whitespaceJim Grosbach2010-10-271-17/+17
| | | | llvm-svn: 117496
* Provide correct encodings for the get_lane and set_lane variants of vmov.Owen Anderson2010-10-273-42/+189
| | | | llvm-svn: 117495
* Add support for R_386_TLS_GD, R_386_TLS_LE_32, R_386_TLS_IE and R_386_TLS_LE.Rafael Espindola2010-10-273-1/+75
| | | | llvm-svn: 117494
* Added the x86 instruction ud2b (2nd official undefined instruction).Kevin Enderby2010-10-273-2/+7
| | | | llvm-svn: 117485
* JIT imm12 encoding for constant pool entry references.Jim Grosbach2010-10-271-0/+4
| | | | llvm-svn: 117483
* SelectionDAG shuffle nodes do not allow operands with different numbers ofBob Wilson2010-10-272-0/+73
| | | | | | | | | | | | | | | | | | | elements than the result vector type. So, when an instruction like: %8 = shufflevector <2 x float> %4, <2 x float> %7, <4 x i32> <i32 1, i32 0, i32 3, i32 2> is translated to a DAG, each operand is changed to a concat_vectors node that appends 2 undef elements. That is: shuffle [a,b], [c,d] is changed to: shuffle [a,b,u,u], [c,d,u,u] That's probably the right thing for x86 but for NEON, we'd much rather have: shuffle [a,b,c,d], undef Teach the DAG combiner how to do that transformation for ARM. Radar 8597007. llvm-svn: 117482
* Implement R_X86_64_GOTTPOFF, R_X86_64_TLSGD and R_X86_64_TPOFF32.Rafael Espindola2010-10-272-7/+40
| | | | llvm-svn: 117481
* ARM JIT fix for LDRi12 and company.Jim Grosbach2010-10-272-4/+18
| | | | llvm-svn: 117478
* Replace pointer arithmetic with StringRef::substr.Benjamin Kramer2010-10-271-6/+5
| | | | llvm-svn: 117477
* Provide correct NEON encodings for vdup.Owen Anderson2010-10-273-8/+157
| | | | llvm-svn: 117475
* x86-Win32: Switch ftol2 calling convention from stdcall to C.Michael J. Spencer2010-10-271-2/+2
| | | | llvm-svn: 117474
* COFF: Add IMAGE_SCN_MEM_READ to text sections.Michael J. Spencer2010-10-271-0/+1
| | | | | | | | There are currently 100 references to COFF::IMAGE_SCN in 6 files and 11 different functions. Section to attribute mapping really needs to happen in one place to avoid problems like this. llvm-svn: 117473
* Fix whitespace.Michael J. Spencer2010-10-271-15/+15
| | | | llvm-svn: 117472
* Set default type and flags for .init and .fini.Rafael Espindola2010-10-272-1/+37
| | | | llvm-svn: 117471
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