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* [PATCH] [HEXAGON] Add a test program to verify calling conventionSundeep Kushwaha2015-05-121-0/+13
| | | | | | | | for large struct return by value. Differential Revision: http://reviews.llvm.org/D9709 llvm-svn: 237170
* Convert PHI getIncomingValue() to foreach over incoming_values(). NFC.Pete Cooper2015-05-1217-49/+40
| | | | | | | | We already had a method to iterate over all the incoming values of a PHI. This just changes all eligible code to use it. Ineligible code included anything which cared about the index, or was also trying to get the i'th incoming BB. llvm-svn: 237169
* Add a const method to iterator over PHI incoming values.Pete Cooper2015-05-121-0/+2
| | | | | | This will be used in the next commit which converts code to use incoming_values(). llvm-svn: 237168
* Constify method. NFCPete Cooper2015-05-121-1/+1
| | | | llvm-svn: 237167
* [Statepoints] Split the calling convention and statepoint flags operand to ↵Pat Gavlin2015-05-125-29/+54
| | | | | | | | STATEPOINT into two separate operands. Differential Revision: http://reviews.llvm.org/D9623 llvm-svn: 237166
* Strip trailing whitespace. NFCDouglas Katzman2015-05-124-5/+5
| | | | llvm-svn: 237165
* R600/SI: Fix bug in VGPR spillingTom Stellard2015-05-125-76/+69
| | | | | | | | | | | | AMDGPU::SI_SPILL_V96_RESTORE was missing from a switch statement, which caused the srsrc and soffset register to not be set correctly. This commit replaces the switch statement with a SITargetInfo query to make sure all spill instructions are covered. Differential Revision: http://reviews.llvm.org/D9582 llvm-svn: 237164
* [lib/Fuzzer] guess the right number of workers if -jobs=N is given but ↵Kostya Serebryany2015-05-125-7/+22
| | | | | | -workers=M is not. Update the docs. llvm-svn: 237163
* Revert r237157, "YAML: Fix typos. NFC".Alex Lorenz2015-05-121-2/+2
| | | | | | 'Iff' isn't a typo, it's a shorthand for 'if and only if'. llvm-svn: 237160
* [mips][microMIPSr6] Implement SELEQZ and SELNEZ instructionsJozef Kolek2015-05-125-3/+42
| | | | | | | | This patch implements SELEQZ and SELNEZ instructions using mapping. Differential Revision: http://reviews.llvm.org/D8497 llvm-svn: 237158
* YAML: Fix typos. NFC.Alex Lorenz2015-05-121-2/+2
| | | | llvm-svn: 237157
* Reimplement heuristic for estimating complete-unroll optimization effects.Michael Zolotukhin2015-05-123-250/+336
| | | | | | | | | | | | | | | | | | | | Summary: This patch reimplements heuristic that tries to estimate optimization beneftis from complete loop unrolling. In this patch I kept the minimal changes - e.g. I removed code handling branches and folding compares. That's a promising area, but now there are too many questions to discuss before we can enable it. Test Plan: Tests are included in the patch. Reviewers: hfinkel, chandlerc Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8816 llvm-svn: 237156
* [Mips] Return false for isFPCloseToIncomingSP()Petar Jovanovic2015-05-122-0/+34
| | | | | | | | | | | | | On Mips, frame pointer points to the same side of the frame as the stack pointer. This function is used to decide where to put register scavenging spill slot. So far, it was put on the wrong side of the frame, and thus it was too far away from $fp when frame was larger than 2^15 bytes. Patch by Vladimir Radosavljevic. http://reviews.llvm.org/D8895 llvm-svn: 237153
* R600/SI: add pass to mark CF live ranges as non-spillableTom Stellard2015-05-125-0/+611
| | | | | | | | | | | | | | | | | | | | | | Spilling can insert instructions almost anywhere, and this can mess up control flow lowering in a multitude of ways, due to instruction reordering. Let's sort this out the easy way: never spill registers involved with control flow, i.e. saved EXEC masks. Unfortunately, this does not work at all with optimizations disabled, as the register allocator ignores spill weights. This should be addressed in a future commit. The test was reduced from the "stacks" shader of [1]. Some issues trigger the machine verifier while another one is checked manually. [1] http://madebyevan.com/webgl-path-tracing/ v2: only insert pass with optimizations enabled, merge test runs. Patch by: Grigori Goronzy llvm-svn: 237152
* Changed renaming of local symbols by inserting a dot vefore the numeric suffix.Sunil Srivastava2015-05-1229-121/+121
| | | | | | | One code change and several test changes to match that details in http://reviews.llvm.org/D9481 llvm-svn: 237150
* Delete dead code. NFCJonathan Roelofs2015-05-121-1/+0
| | | | llvm-svn: 237148
* Comment disambiguation.Douglas Katzman2015-05-121-2/+2
| | | | llvm-svn: 237146
* [DWARF] Add CIE header fields address_size and segment_size when generating ↵Keith Walker2015-05-125-13/+56
| | | | | | | | | | | | | dwarf-4 The DWARF-4 specification added 2 new fields in the CIE header called address_size and segment_size. Create these 2 new fields when generating dwarf-4 CIE entries, print out the new fields when dumping the CIE and update tests Differential Revision: http://reviews.llvm.org/D9558 llvm-svn: 237145
* use 'auto' to improve readability; NFCSanjay Patel2015-05-121-2/+1
| | | | llvm-svn: 237144
* R600/SI: Update tablegen defs to avoid restoring spilled sgprs to m0Tom Stellard2015-05-122-9/+4
| | | | | | | | We had code to do this in SIRegisterInfo::eliminateFrameIndex(), but it is easier to just change the definition of SI_SPILL_S32_RESTORE to only allow numbered sgprs. llvm-svn: 237143
* R600/SI: Remove M0Reg register classTom Stellard2015-05-124-5/+2
| | | | | | It is no longer used. llvm-svn: 237142
* R600/SI: Remove explicit m0 operand from DS instructionsTom Stellard2015-05-128-120/+261
| | | | | | | Instead add m0 as an implicit operand. This helps avoid spills of the m0 register in some cases. llvm-svn: 237141
* R600/SI: Remove explicit m0 operand from v_interp instructionsTom Stellard2015-05-126-33/+59
| | | | | | | Instead add m0 as an implicit operand. This helps avoid spills of the m0 register in some cases. llvm-svn: 237140
* fix typos, grammar; NFCSanjay Patel2015-05-121-2/+2
| | | | llvm-svn: 237139
* R600/SI: Make sendmsg test more strictTom Stellard2015-05-121-0/+2
| | | | | | We want to make sure that the m0 copies are being cse'd. llvm-svn: 237134
* R600/SI: Remove explicit m0 operand from s_sendmsgTom Stellard2015-05-126-8/+36
| | | | | | | | | | | | | | | Instead add m0 as an implicit operand. This allows us to avoid using the M0Reg register class and eliminates a number of unnecessary spills when using s_sendmsg instructions. This impacts one shader in the shader-db: SGPRS: 48 -> 40 (-16.67 %) VGPRS: 112 -> 108 (-3.57 %) Code Size: 40132 -> 38796 (-3.33 %) bytes LDS: 0 -> 0 (0.00 %) blocks Scratch: 2048 -> 0 (-100.00 %) bytes per wave llvm-svn: 237133
* R600/SI: Replace TRI->getRegClass(Reg) with TRI->getPhysRegClass(Reg)Tom Stellard2015-05-123-7/+11
| | | | | | | TRI->getRegClass() takes a register class ID, not a register. We were using this incorrectly in a few places. llvm-svn: 237132
* AVX-512, X86: Added lowering for shift operations for SKX.Elena Demikhovsky2015-05-122-101/+94
| | | | | | | | The other changes in the LowerShift() are not functional, just to make the code more convenient. So, the functional changes for SKX only. llvm-svn: 237129
* [ARM] Use AEABI aligned function variantsJohn Brawn2015-05-123-82/+223
| | | | | | | | | | | AEABI defines aligned variants of memcpy etc. that can be faster than the default version due to not having to do alignment checks. When emitting target code for these functions make use of these aligned variants if possible. Also convert memset to memclr if possible. Differential Revision: http://reviews.llvm.org/D8060 llvm-svn: 237127
* Reverse ordering of base and derived pointer during safepoint lowering.Igor Laevsky2015-05-123-31/+148
| | | | | | | | According to the documentation in StackMap section for the safepoint we should have: "The first Location in each pair describes the base pointer for the object. The second is the derived pointer actually being relocated." But before this change we emitted them in reverse order - derived pointer first, base pointer second. llvm-svn: 237126
* [X86] Remove useless target specific combine on TRUNCATE dag nodes.Andrea Di Biagio2015-05-121-11/+0
| | | | | | | | | | | | | Before revision 171146, function 'PerformTruncateCombine' used to perform a premature lowering of TRUNCATE dag nodes. Revision 171146 then moved all the logic implemented by PerformTruncateCombine to a custom lowering hook. However, that revision forgot to delete function PerformTruncateCombine from the code. This patch removes function 'PerformTruncateCombine' since it has no effect on the SelectionDAG. No functional change intended. llvm-svn: 237122
* [mips][FastISel] Handle calls with non legal types i8 and i16.Vasileios Kalintiris2015-05-122-1/+187
| | | | | | | | | | | | | | | | | | Summary: Allow calls with non legal integer types based on i8 and i16 to be processed by mips fast-isel. Based on a patch by Reed Kotler. Test Plan: "Make check" test forthcoming. Test-suite passes at O0/O2 and with mips32 r1/r2 Reviewers: rkotler, dsanders Subscribers: llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D6770 llvm-svn: 237121
* [mips][FastISel] Simplify callabi.ll by using multiple check prefixes.Vasileios Kalintiris2015-05-121-397/+274
| | | | | | | | | | Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9635 llvm-svn: 237119
* [mips][FastISel] Allow computation of addresses from constant expressions.Vasileios Kalintiris2015-05-122-2/+22
| | | | | | | | | | | | | | | | | | | Summary: Try to compute addresses when the offset from a memory location is a constant expression. Based on a patch by Reed Kotler. Test Plan: Passes test-suite for -O0/O2 and mips 32 r1/r2 Reviewers: rkotler, dsanders Subscribers: llvm-commits, aemerson, rfuhler Differential Revision: http://reviews.llvm.org/D6767 llvm-svn: 237117
* Change TargetParser enum names to avoid macro conflicts (llvm)Renato Golin2015-05-125-173/+173
| | | | | | | | | sys/time.h on Solaris (and possibly other systems) defines "SEC" as "1" using a cpp macro. The result is that this fails to compile. Fixes https://llvm.org/PR23482 llvm-svn: 237112
* AVX-512: asm parser errors checkElena Demikhovsky2015-05-121-0/+6
| | | | | | | I reverted the error check that was removed in 236416. I put the it in a separate file. llvm-svn: 237107
* AVX-512: select operation for i1 vectorsElena Demikhovsky2015-05-123-0/+100
| | | | | | | | like: select i1 %cond, <16 x i1> %a, <16 x i1> %b. I added pseudo-CMOV patterns to resolve the "select". Added tests for KNL and SKX. llvm-svn: 237106
* [X86] DAGCombine should not assume arbitrary vector types are simpleMichael Kuperstein2015-05-122-1/+12
| | | | | | | | | The X86-specific DAGCombine for stores should not assume vector types are always simple. This fixes PR23476. Differential Revision: http://reviews.llvm.org/D9659 llvm-svn: 237097
* Remove unnecessary forward declaration.Craig Topper2015-05-121-1/+0
| | | | llvm-svn: 237093
* Remove unnecessary variables by folding calls into for loop header. NFC.Craig Topper2015-05-121-4/+2
| | | | llvm-svn: 237090
* [lib/Fuzzer] remove the -dfsan=1 flag, just use -use_traces=1 (w/ or w/o dfsan)Kostya Serebryany2015-05-125-8/+4
| | | | llvm-svn: 237083
* [lib/Fuzzer] detach the pulse thread instad of joining itKostya Serebryany2015-05-121-1/+1
| | | | llvm-svn: 237082
* Migrate existing backends that care about software floating pointEric Christopher2015-05-1228-78/+99
| | | | | | | | | | | | | | | | | | | | to use the information in the module rather than TargetOptions. We've had and clang has used the use-soft-float attribute for some time now so have the backends set a subtarget feature based on a particular function now that subtargets are created based on functions and function attributes. For the one middle end soft float check go ahead and create an overloadable TargetLowering::useSoftFloat function that just checks the TargetSubtargetInfo in all cases. Also remove the command line option that hard codes whether or not soft-float is set by using the attribute for all of the target specific test cases - for the generic just go ahead and add the attribute in the one case that showed up. llvm-svn: 237079
* Fixing memory leakAndrew Kaylor2015-05-121-0/+2
| | | | llvm-svn: 237072
* Refactoring gc_relocate related code in CodeGenPrepare.cppSanjoy Das2015-05-111-7/+4
| | | | | | | | | | | | | | | | | | | | Summary: The original code inserted new instructions by following a Create->Remove->ReInsert flow. This patch removes the unnecessary Remove->ReInsert part by setting up the InsertPoint correctly at the very beginning. This change does not introduce any functionality change. Patch by Chen Li! Reviewers: reames, AndyAyers, sanjoy Reviewed By: sanjoy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9687 llvm-svn: 237070
* Rename variables in gc_relocate related functions to follow LLVM's naming ↵Sanjoy Das2015-05-112-47/+47
| | | | | | | | | | | | | | | | | | | | conventions. Summary: This patch is to rename some variables to CamelCase in gc_relocate related functions. There is no functionality change. Patch by Chen Li! Reviewers: reames, AndyAyers, sanjoy Reviewed By: sanjoy Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9681 llvm-svn: 237069
* [lib/Fuzzer] don't record traces when trace collection is offKostya Serebryany2015-05-111-1/+2
| | | | llvm-svn: 237067
* [MemCpyOpt] Look at any dependency -not just source- for memset+memcpy.Ahmed Bougacha2015-05-112-6/+25
| | | | | | | | | | This fixes another miscompile introduced by r235232: when there was a dependency on the memcpy destination other than the memset, we would ignore it, because we only looked at the source dependency. It was a mistake to use SrcDepInfo. Instead, just use DepInfo. llvm-svn: 237066
* Simplify a return expression and an access to an alloca's allocated typeDavid Blaikie2015-05-111-3/+3
| | | | llvm-svn: 237065
* [WinEH] Handle nested landing pads that return directly to the parent function.Andrew Kaylor2015-05-116-15/+323
| | | | | | Differential Revision: http://reviews.llvm.org/D9684 llvm-svn: 237063
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