| Commit message (Collapse) | Author | Age | Files | Lines |
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Implement the same interface as already available for dominators.
llvm-svn: 93194
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overlap, then select as an ADD instead.
llvm-svn: 93191
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llvm-svn: 93189
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llvm-svn: 93187
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llvm-svn: 93185
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BRCOND was constant folded.
This fixes PR5980.
llvm-svn: 93184
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llvm-svn: 93183
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llvm-svn: 93182
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then a load if the
loads are not in the default address space because the transformation discards src value info.
llvm-svn: 93180
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llvm-svn: 93174
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llvm-svn: 93172
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documentation.
Patch by Dustin Laurence!
llvm-svn: 93170
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convention.
llvm-svn: 93167
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llvm-svn: 93165
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have a fix.
llvm-svn: 93163
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- getToken is modeled after StringRef::split but it can split on multiple
separator chars and skips leading seperators.
- SplitString is a StringRef::split variant for more than 2 elements with the
same behaviour as getToken.
llvm-svn: 93161
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has an immediate with at least 32 bits of leading zeros, to avoid needing to
materialize that immediate in a register first.
FileCheckize, tidy, and extend a testcase to cover this case.
This fixes rdar://7527390.
llvm-svn: 93160
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new AsmPrinter. This is perhaps less elegant than describing them
in terms of MOV32r0 and subreg operations, but it allows the
current register to rematerialize them.
llvm-svn: 93158
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llvm-svn: 93157
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llvm-svn: 93156
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single user. The _su forms are intended for non-top-level nodes.
llvm-svn: 93155
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llvm-svn: 93154
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allow the instruction to be 3address-fied if needed.
llvm-svn: 93152
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ignore alignment requirements for SIMD memory operands. This
is useful on architectures like the AMD 10h that do not trap on
unaligned references if a status bit is twiddled at startup time.
llvm-svn: 93151
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Make InsertDbgValueIntrinsic() and get Offset take and recieve a uint64_t.
Get constness correct for getVariable() and getValue().
llvm-svn: 93149
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good code on PR4216:
_test_bitfield: ## @test_bitfield
orl $32962, %edi
movl $4294941946, %eax
andq %rdi, %rax
ret
instead of:
_test_bitfield:
movl $4294941696, %ecx
movl %edi, %eax
orl $194, %edi
orl $32768, %eax
andq $250, %rdi
andq %rax, %rcx
movq %rdi, %rax
orq %rcx, %rax
ret
Evan is looking into the remaining andq+imm -> andl optimization.
llvm-svn: 93147
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BitsToClear case. This allows it to promote expressions which have an
and/or/xor after the lshr, promoting cases like test2 (from PR4216)
and test3 (random extample extracted from a spec benchmark).
clang now compiles the code in PR4216 into:
_test_bitfield: ## @test_bitfield
movl %edi, %eax
orl $194, %eax
movl $4294902010, %ecx
andq %rax, %rcx
orl $32768, %edi
andq $39936, %rdi
movq %rdi, %rax
orq %rcx, %rax
ret
instead of:
_test_bitfield: ## @test_bitfield
movl %edi, %eax
orl $194, %eax
movl $4294902010, %ecx
andq %rax, %rcx
shrl $8, %edi
orl $128, %edi
shlq $8, %rdi
andq $39936, %rdi
movq %rdi, %rax
orq %rcx, %rax
ret
which is still not great, but is progress.
llvm-svn: 93145
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new BitsToClear result which allows us to start promoting
expressions that end with a lshr-by-constant. This is
conservatively correct and better than what we had before
(see testcases) but still needs to be extended further.
llvm-svn: 93144
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llvm-svn: 93143
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the dest of the sext.
llvm-svn: 93128
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the zext dest type. This allows us to handle test52/53 in cast.ll,
and allows llvm-gcc to generate much better code for PR4216 in -m64
mode:
_test_bitfield: ## @test_bitfield
orl $32962, %edi
movl %edi, %eax
andl $-25350, %eax
ret
This also fixes a bug handling vector extends, ensuring that the
mask produced is a vector constant, not an integer constant.
llvm-svn: 93127
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integer vectors as well as just integers.
llvm-svn: 93126
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warning: suggest parentheses around ‘&&’ within ‘||’.
llvm-svn: 93121
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simpler profitability predicate.
llvm-svn: 93111
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llvm-svn: 93110
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elimination of a sign extend to be a win, which simplifies
the client of CanEvaluateSExtd, and allows us to eliminate
more casts (examples taken from real code).
llvm-svn: 93109
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getWhenValsUnresolved().
Document PFS argument to ParseValID() and ConvertGlobalOrMetadataValIDToValue().
llvm-svn: 93108
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lshr+ashr instead of trunc+sext. We want to avoid type
conversions whenever possible, it is easier to codegen expressions
without truncates and extensions.
llvm-svn: 93107
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llvm-svn: 93106
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llvm-svn: 93105
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bits known clear in the result and don't care about the # casts
eliminated. TD is also dead but keeping it for now.
llvm-svn: 93098
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1) don't try to optimize a sext or zext that is only used by a trunc, let
the trunc get optimized first. This avoids some pointless effort in
some common cases since instcombine scans down a block in the first pass.
2) Change the cost model for zext elimination to consider an 'and' cheaper
than a zext. This allows us to do it more aggressively, and for the next
patch to simplify the code quite a bit.
llvm-svn: 93097
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more expressions to be promoted and casts eliminated.
llvm-svn: 93096
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llvm-svn: 93095
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llvm-svn: 93093
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llvm-svn: 93092
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llvm-svn: 93091
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commonIntCastTransforms into the callers, eliminating a switch,
and allowing the static predicate methods to be moved down to
live next to the corresponding function. No functionality
change.
llvm-svn: 93089
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llvm-svn: 93082
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llvm-svn: 93080
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