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* [ARM] Dynamic stack alignment for 16-bit ThumbMomchil Velikov2017-10-226-24/+53
| | | | | | | | | | | This patch implements dynamic stack (re-)alignment for 16-bit Thumb. When targeting processors, which support only the 16-bit Thumb instruction set the compiler ignores the alignment attributes of automatic variables and may silently generate incorrect code. Differential revision: https://reviews.llvm.org/D38143 llvm-svn: 316289
* [X86] Add a pass to convert instruction chains between domains.Guy Blank2017-10-2212-666/+3277
| | | | | | | | | | | | | | | | | The pass scans the function to find instruction chains that define registers in the same domain (closures). It then calculates the cost of converting the closure to another domain. If found profitable, the instructions are converted to instructions in the other domain and the register classes are changed accordingly. This commit adds the pass infrastructure and a simple conversion from the GPR domain to the Mask domain. Differential Revision: https://reviews.llvm.org/D37251 Change-Id: Ic2cf1d76598110401168326d411128ae2580a604 llvm-svn: 316288
* [mips] Adds support for R_MIPS_26, HIGHER, HIGHEST relocations in RuntimeDyld.Nitesh Jain2017-10-226-16/+122
| | | | | | | | | | Reviewers: sdardis Subscribers: jaydeep, bhushan, llvm-commits Differential Revision: https://reviews.llvm.org/D38314 llvm-svn: 316287
* [X86] Teach the disassembler that some instructions use VEX.W==0 without a ↵Craig Topper2017-10-224-16/+32
| | | | | | | | corresponding VEX.W==1 instruction and we shouldn't treat them as if VEX.W is ignored. Fixes PR11304. llvm-svn: 316285
* [X86] Add VEX_WIG to applicable AVX512 instructions.Craig Topper2017-10-221-41/+43
| | | | | | This should be NFC. Will be used in future patches to fix disassembler bugs. llvm-svn: 316284
* [X86] Add VEX_WIG to VROUNDSSrr/VROUNDSSrm/VROUNDSDrr/VROUNDSDrmCraig Topper2017-10-221-1/+1
| | | | llvm-svn: 316283
* [X86] Don't allow gather/scatter to disassembler if memory operand does not ↵Craig Topper2017-10-222-0/+8
| | | | | | | | use a SIB byte. Fixes PR34998. llvm-svn: 316282
* Strip trailing whitespace. NFCI.Simon Pilgrim2017-10-211-4/+4
| | | | llvm-svn: 316277
* Reverting r316270 due to failing build bots.Aaron Ballman2017-10-212-24/+22
| | | | | | | http://lab.llvm.org:8011/builders/clang-x86_64-linux-selfhost-modules-2/builds/12899 http://lab.llvm.org:8011/builders/clang-x86-windows-msvc2015/builds/7951 llvm-svn: 316276
* [X86][SSE] Add extractps/pextrd equivalence to domain tablesSimon Pilgrim2017-10-2114-91/+87
| | | | | | Differential Revision: https://reviews.llvm.org/D39135 llvm-svn: 316274
* [X86] Fix disassembling of EVEX instructions to stop accidentally decoding ↵Craig Topper2017-10-216-143/+61
| | | | | | | | | | | | the SIB index register as an XMM/YMM/ZMM register. This introduces a new operand type to encode the whether the index register should be XMM/YMM/ZMM. And new code to fixup the results created by readSIB. This has the nice effect of removing a bunch of code that hard coded the name of every GATHER and SCATTER instruction to map the index type. This fixes PR32807. llvm-svn: 316273
* Fix MSVC 'result of 32-bit shift implicitly converted to 64 bits' warning. NFCI.Simon Pilgrim2017-10-211-2/+2
| | | | llvm-svn: 316271
* [PPC CodeGen] Fix the bitreverse.i64 intrinsic.Fangrui Song2017-10-212-22/+24
| | | | | | | | | | Summary: The two 32-bit words were swapped. Subscribers: nemanjai, kbarton Differential Revision: https://reviews.llvm.org/D38705 llvm-svn: 316270
* [ValueTracking] Remove unnecessary temporary APInt from ↵Craig Topper2017-10-211-5/+1
| | | | | | | | computeNumSignBitsVectorConstant. We can just use getNumSignBits instead of inverting negative numbers. llvm-svn: 316266
* [ValueTracking] Simplify the known bits code for constant vectors a little.Craig Topper2017-10-211-4/+2
| | | | | | Neither of these cases really require a temporary APInt outside the loop. For the ConstantDataSequential case the APInt will never be larger than 64-bits so its fine to just call getElementAsAPInt. For ConstantVector we can get the APInt by reference and only make a copy where the inversion is needed. llvm-svn: 316265
* [X86][SSE] Add missing extractps scheduling testSimon Pilgrim2017-10-211-0/+62
| | | | llvm-svn: 316262
* [LoopInterchange] Fix phi node ordering miscompile.David Green2017-10-212-1/+96
| | | | | | | | | | | The way that splitInnerLoopHeader splits blocks requires that the induction PHI will be the first PHI in the inner loop header. This makes sure that is actually the case when there are both IV and reduction phis. Differential Revision: https://reviews.llvm.org/D38682 llvm-svn: 316261
* [SelectionDAG] Use dyn_cast without cast.Florian Hahn2017-10-211-2/+2
| | | | llvm-svn: 316258
* [SelectionDAG] Use isa to silence unused variable warning (NFC).Florian Hahn2017-10-211-1/+1
| | | | llvm-svn: 316257
* [SelectionDAG] Don't subject ConstantSDNodes to the depth limit in ↵Craig Topper2017-10-211-10/+13
| | | | | | | | computeKnownBits and ComputeNumSignBits. We don't need to do any additional recursion, we just need to analyze the APInt stored in the node. This matches what the ValueTracking versions do for IR. llvm-svn: 316256
* [SelectionDAG] Don't subject ISD:Constant to the depth limit in ↵Craig Topper2017-10-211-5/+7
| | | | | | | | | | | | | | | | | | | TargetLowering::SimplifyDemandedBits. Summary: We shouldn't recurse any further but it doesn't mean we shouldn't be able to give the known bits for a constant. The caller would probably like that we always return the right answer for a constant RHS. This matches what InstCombine does in this case. I don't have a test case because this showed up while trying to revive D31724. Reviewers: RKSimon, spatel Reviewed By: RKSimon Subscribers: arsenm, llvm-commits Differential Revision: https://reviews.llvm.org/D38967 llvm-svn: 316255
* [X86] Do not generate __multi3 for mul i128 on X86Craig Topper2017-10-217-4989/+8382
| | | | | | | | | | | | | | | | Summary: __multi3 is not available on x86 (32-bit). Setting lib call name for MULI_128 to nullptr forces DAGTypeLegalizer::ExpandIntRes_MUL to generate instructions for 128-bit multiply instead of a call to an undefined function. This fixes PR20871 though it may be worth looking at why licm and indvars combine to generate 65-bit multiplies in that test. Patch by Riyaz V Puthiyapurayil Reviewers: craig.topper, schweitz Reviewed By: craig.topper, schweitz Subscribers: RKSimon, llvm-commits Differential Revision: https://reviews.llvm.org/D38668 llvm-svn: 316254
* [Transforms] Fix some Clang-tidy modernize and Include What You Use ↵Eugene Zelenko2017-10-216-176/+315
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 316253
* [Packetizer] Add function to check for aliasing between instructionsKrzysztof Parzyszek2017-10-204-1/+81
| | | | llvm-svn: 316243
* [utils, x86] add regex for retl/retq to reduce duplicated FileChecking (PR35003)Sanjay Patel2017-10-201-0/+3
| | | | llvm-svn: 316242
* [Transforms] Fix some Clang-tidy modernize and Include What You Use ↵Eugene Zelenko2017-10-206-148/+303
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 316241
* [WebAssembly] MC: Fix crash when -g specified.Sam Clegg2017-10-209-59/+99
| | | | | | | | | At this point we don't output any debug sections or thier relocations. Differential Revision: https://reviews.llvm.org/D39076 llvm-svn: 316240
* [globalisel][tablegen] Fix small spelling nits. NFCDaniel Sanders2017-10-205-25/+25
| | | | | | | ComplexRendererFn -> ComplexRendererFns Corrected a couple lingering references to tied operands that were missed. llvm-svn: 316237
* [Hexagon] Report error instead of crashing on wrong inline-asm constraintsKrzysztof Parzyszek2017-10-202-13/+30
| | | | llvm-svn: 316236
* COFF: Add type server pdb files to linkrepro tar file.Peter Collingbourne2017-10-203-11/+12
| | | | | | Differential Revision: https://reviews.llvm.org/D38977 llvm-svn: 316233
* [Hexagon] Reorganize and update instruction patternsKrzysztof Parzyszek2017-10-2025-2707/+2496
| | | | llvm-svn: 316228
* [X86][SSE] Add missing _mm_extract_ps fast-isel testSimon Pilgrim2017-10-201-1/+16
| | | | llvm-svn: 316226
* [x86] avoid FileCheck assert duplication with retl/retq regex; NFCSanjay Patel2017-10-201-118/+58
| | | | | | | | | | | This was suggested in PR35003: https://bugs.llvm.org/show_bug.cgi?id=35003 32-bit checks may be identical to 64-bit (if we avoid those pesky scalar params!). I'll check in the script change shortly assuming this doesn't anger any bots. llvm-svn: 316223
* [X86][SSE] getTargetShuffleMask - check shuffle input value types. NFCI.Simon Pilgrim2017-10-201-0/+46
| | | | | | To help identify shuffle combine issues llvm-svn: 316222
* [WebAssembly] MC: Handle (ignore) MCSA_Protected symbol attributeSam Clegg2017-10-201-0/+1
| | | | llvm-svn: 316220
* Make x86 __ehhandler comdat if parent function isDave Lee2017-10-202-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This change comes from using lld for i686-windows-msvc. Before this change, lld emits an error of: error: relocation against symbol in discarded section: .xdata It's possible that this could be addressed in lld, but I think this change is reasonable on its own. At a high level, this is being generated: A (.text comdat) -> B (.text) -> C (.xdata comdat) Where A is a C++ inline function, which references B, an exception handler thunk, which references C, the exception handling info. With this structure, lld will error when applying relocations to B if the C it references has been discarded (some other C has been selected). This change checks if A is comdat, and if so places the exception registration thunk (B) in the comdata group of A (and B). It appears that MSVC makes the __ehhandler function comdat. Is it possible that duplicate thunks are being emitted into the final binary with other linkers, or are they stripping the unused thunks? Reviewers: rnk, majnemer, compnerd, smeenai Reviewed By: rnk, compnerd Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38940 llvm-svn: 316219
* [Hexagon] Allow redefinition with immediates for hw loop conversionKrzysztof Parzyszek2017-10-203-7/+76
| | | | | | | | | | | Normally, if the registers holding the induction variable's bounds are redefined inside of the loop's body, the loop cannot be converted to a hardware loop. However, if the redefining instruction is actually loading an immediate value into the register, this conversion is both possible and legal (since the immediate itself will be used in the loop setup in the preheader). llvm-svn: 316218
* [X86] Check all CPU target names. Simon Pilgrim2017-10-201-0/+46
| | | | | | We ignore the 32-bit/64-bit triple but I've tried to use i686 triples for CPUs that don't support x86_64 llvm-svn: 316217
* X86 Tests: Add tests for vector permutes with variable indices. NFC.Zvi Rackover2017-10-203-0/+2584
| | | | | | Basic tests which are the equivalent of single-source shufflevector with variable mask. llvm-svn: 316216
* Revert "[mips] Reordering callseq* nodes to be linear"Aleksandar Beserminji2017-10-208-38/+36
| | | | | | | This reverts commit r314507, because the original patch is causing test failures. llvm-svn: 316215
* [ARM] Use post-RA MI scheduler when +use-misched is setEugene Leviant2017-10-202-1/+11
| | | | | | Differential revision: https://reviews.llvm.org/D39100 llvm-svn: 316214
* [X86][AVX512] Regenerate regcall tests.Simon Pilgrim2017-10-202-571/+1860
| | | | | | As part of tracking down machine verifier issues (PR27481) llvm-svn: 316213
* [ValueTracking] Enabling ValueTracking patch by default Nikolai Bozhenov2017-10-202-10/+1
| | | | | | | | | | | | | | | | | (recommit #2 after checking for timeout issue). The original patch was an improvement to IR ValueTracking on non-negative integers. It has been checked in to trunk (D18777, r284022). But was disabled by default due to performance regressions. Perf impact has improved. The patch would be enabled by default. Reviewers: reames, hfinkel Differential Revision: https://reviews.llvm.org/D34101 Patch by: Olga Chupina <olga.chupina@intel.com> llvm-svn: 316208
* Add test case for LoopSink passMax Kazantsev2017-10-201-0/+64
| | | | | | | | | | | This test checks that load from constant memory will be sunk regardless of aliasing stores in the loop. Patch by Daniil Suchkov! Differential Revision: https://reviews.llvm.org/D39113 llvm-svn: 316207
* [AVR] Fix the select-mbb-placement-bug.llDylan McKay2017-10-201-3/+3
| | | | llvm-svn: 316205
* [ExecutionEngine] Temporarily remove the ExecutionEngine tls tests.Lang Hames2017-10-202-20/+0
| | | | | | | Will re-enable once I figure out why the necessary runtime functions are missing on some bots. llvm-svn: 316203
* [ExecutionEngine] After a heroic dev-meeting hack session, the JIT supports TLS.Lang Hames2017-10-204-1/+27
| | | | | | Turns on EmulatedTLS support by default in EngineBuilder. ;) llvm-svn: 316200
* Disabling the transformation introduced in r315888Nemanja Ivanovic2017-10-202-3/+3
| | | | | | | The commit at https://reviews.llvm.org/rL315888 is causing some failures with internal testing. Disabling this code until we can resolve the issues. llvm-svn: 316199
* [XRay] [docs] Document how to generate flamegraphs from xray traces.Keith Wyss2017-10-192-7/+77
| | | | | | | | | | | | | | Summary: Updated the XRayExample docs with instructions for using the llvm-xray stacks command. Reviewers: dberris Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D39106 llvm-svn: 316192
* [Transforms] Fix some Clang-tidy modernize and Include What You Use ↵Eugene Zelenko2017-10-193-302/+449
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 316190
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