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* [NFC] Remove multiple semicolonsMandeep Singh Grang2017-06-282-2/+2
| | | | | | | | | | | | Reviewers: bogner, whitequark, mgrang Reviewed By: mgrang Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34785 llvm-svn: 306613
* Introduce symbol cache to PDB NativeSessionAdrian McCarthy2017-06-283-7/+28
| | | | | | | | | | | | | Instead of creating symbols directly in the findChildren methods of the native symbol implementations, they will rely on the NativeSession to act as a factory for these types. This lets NativeSession cache the NativeRawSymbols in its new symbol cache and makes that cache the source of unique IDs for the symbols. Right now, this affects only NativeCompilandSymbols. There's no external change yet, so I think the existing tests are still sufficient. Coming soon are patches to extend this to built-in types and enums. llvm-svn: 306610
* Revert "Make OrderedInstructions and OrderedBasicBlock use AssertingVH, to ↵Xin Tong2017-06-282-5/+3
| | | | | | | | | | | | | try and catch mistakes" This reverts commit 50ec560f05dcb8a1be18be442660d0305bc7de25. It catches some bug in NewGVN it seems. I am in middle of something and will not be able to investigate Revert for now. http://lab.llvm.org:8011/builders/clang-atom-d525-fedora-rel/builds/6268 llvm-svn: 306608
* Make OrderedInstructions and OrderedBasicBlock use AssertingVH, to try and ↵Xin Tong2017-06-282-3/+5
| | | | | | | | | | | | | | catch mistakes Summary: Make OrderedInstructions and OrderedBasicBlock use AssertingVH to try and catch mistakes Reviewers: efriedma Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34780 llvm-svn: 306605
* AMDGPU: Remove SITypeRewriterMatt Arsenault2017-06-2817-564/+401
| | | | | | | This was an old workaround for using v16i8 in some old intrinsics for resource descriptors. llvm-svn: 306603
* [lit] Remove dead code (not referenced anywhere), and clarify some function ↵David L. Jones2017-06-281-177/+41
| | | | | | | | | | | | | | | | | | | | | | | names. Summary: The dead code seems to be unreferenced, according to textual search across the LLVM SVN repo. The clarification part of this change alters the name of a module-level function so that it is different from the name of the class-methods that call it. Currently, there are no erroneous references, but stylistically (c.f. PEP-8), internal "helper" functions should generally be named accordingly by prepending an underscore. (I also chose to add '_impl', which isn't necessary, but helps me at least to mentally disambiguate the interface and implementation functions.) Reviewers: zturner, modocache Subscribers: sanjoy, llvm-commits Differential Revision: https://reviews.llvm.org/D34775 llvm-svn: 306600
* Fix a typo.Eric Christopher2017-06-281-1/+1
| | | | llvm-svn: 306599
* Fold fneg and fabs like multiplicationsStanislav Mekhanoshin2017-06-282-0/+83
| | | | | | | | | | | Given no NaNs and no signed zeroes it folds: (fmul X, (select (fcmp X > 0.0), -1.0, 1.0)) -> (fneg (fabs X)) (fmul X, (select (fcmp X > 0.0), 1.0, -1.0)) -> (fabs X) Differential Revision: https://reviews.llvm.org/D34579 llvm-svn: 306592
* [InstCombine] add tests for icmp with bitreversed ops; NFCSanjay Patel2017-06-281-0/+30
| | | | | | This is similar enough to bswap that we might as well handle them together in one patch. llvm-svn: 306591
* [AArch64] Make assert messages uniform and general [NFC]Mandeep Singh Grang2017-06-284-8/+5
| | | | | | | | | | | | | | Summary: Make assert messages related to Darwin, ELF and COFF uniform. Reviewers: rnk, ruiu, compnerd, t.p.northover Reviewed By: t.p.northover Subscribers: t.p.northover, aemerson, rengolin, javed.absar, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D34730 llvm-svn: 306589
* [AArch64][Falkor] Attempt to fix Windows buildbotsGeoff Berry2017-06-281-1/+1
| | | | llvm-svn: 306588
* Reuse existing variables. NFC.Rafael Espindola2017-06-281-11/+9
| | | | llvm-svn: 306586
* Break up long lines, NFCKrzysztof Parzyszek2017-06-281-2/+4
| | | | llvm-svn: 306585
* [AArch64][Falkor] Try to avoid exhausting HW prefetcher resources when ↵Geoff Berry2017-06-282-0/+228
| | | | | | | | | | | | unrolling. Reviewers: t.p.northover, mcrosier Subscribers: aemerson, rengolin, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D34533 llvm-svn: 306584
* Reuse existing variable. NFC.Rafael Espindola2017-06-281-2/+2
| | | | llvm-svn: 306582
* [Dominators] Move helper functions into SemiNCAInfoJakub Kuderski2017-06-282-192/+185
| | | | | | | | | | | | | | Summary: Helper functions (DFSPass, ReverseDFSPass, Eval) need SemiNCAInfo anyway, so it's simpler to have them there as member functions. This also makes them simpler by removing template boilerplate. Reviewers: dberlin, sanjoy, chandlerc Reviewed By: dberlin Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34427 llvm-svn: 306579
* [BBVectorize][X86] Regenerate simple testsSimon Pilgrim2017-06-284-152/+240
| | | | llvm-svn: 306578
* [InstCombine] Remove 64-bit bit width restriction from m_ConstantInt(uint64_t*&)Craig Topper2017-06-282-9/+4
| | | | | | | | | | I think we only need to make sure the value fits in 64-bits not that bit width is 64-bit. This helps places that use this for shift amounts since the shift amount needs to be the same bitwidth as the LHS, but can't be larger than the bit width. Differential Revision: https://reviews.llvm.org/D34737 llvm-svn: 306577
* [Dominators] Move SemiNCAInfo and helper functions out of DominatorTreeBaseJakub Kuderski2017-06-282-96/+88
| | | | | | | | | | | | | | | | | Summary: This moves SemiNCAInfo from DeminatorTreeBase to GenericDomTreeConstruction. It also put helper functions used during tree constructions in the same file. The point of this change is to further clean up DominatorTreeBase and make it easier to construct and verify (in future patches). Reviewers: dberlin, sanjoy, chandlerc Reviewed By: dberlin Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34420 llvm-svn: 306576
* [LV] Fix PR33613 - retain order of insertelement per partAyal Zaks2017-06-282-10/+62
| | | | | | | | | | | | r306381 caused PR33613, by reversing the order in which insertelements were generated per unroll part. This patch fixes PR33613 by retraining this order, placing each set of insertelements per part immediately after the last scalar being packed for this part. Includes a test case derived from PR33613. Reference: https://bugs.llvm.org/show_bug.cgi?id=33613 Differential Revision: https://reviews.llvm.org/D34760 llvm-svn: 306575
* [Dominators] Move IDoms out of DominatorTreeBase and put them in SNCAInfoJakub Kuderski2017-06-282-22/+21
| | | | | | | | | | | | | | Summary: The temporary IDoms map was used only during DomTree calculation. We can move it to SNCAInfo so that it's no longer a DominatorTreeBase member. Reviewers: sanjoy, dberlin, chandlerc Reviewed By: dberlin Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34317 llvm-svn: 306574
* Fix PR33625.Rafael Espindola2017-06-282-1/+13
| | | | | | We were failing to convert this expression to pcrel. llvm-svn: 306573
* [Dominators] Move InfoRec outside of DominatorTreeBaseJakub Kuderski2017-06-282-66/+68
| | | | | | | | | | | | | | | | | Summary: The InfoRec struct is used only during tree construction, so there is no point having it as a DominatorTreeBase member. This patch moves it into the Calculate function instead and makes it pass it to its helper functions. Reviewers: sanjoy, dberlin, chandlerc Reviewed By: dberlin Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34305 llvm-svn: 306572
* [BBVectorize] Regenerate simple testsSimon Pilgrim2017-06-284-578/+609
| | | | llvm-svn: 306571
* Don't repeat name in comment and format. NFC.Rafael Espindola2017-06-281-19/+15
| | | | llvm-svn: 306568
* Another test commit.Chih-Hung Hsieh2017-06-281-4/+4
| | | | llvm-svn: 306567
* [LoopUnroll] Fix bug in computeUnrollCount causing it to not honor MaxCountGeoff Berry2017-06-282-0/+33
| | | | | | | | | | Reviewers: sanjoy, anna, reames, apilipenko, igor-laevsky, mkuper Subscribers: mcrosier, llvm-commits, mzolotukhin Differential Revision: https://reviews.llvm.org/D34532 llvm-svn: 306564
* [InstCombine] add tests for icmp with bswapped operands; NFCSanjay Patel2017-06-281-0/+30
| | | | llvm-svn: 306563
* [Dominators] Move number to node mapping out of DominatorTreeBaseJakub Kuderski2017-06-282-36/+38
| | | | | | | | | | | | | | Summary: Number to node mapping in DominatorTreeBase is used only during calculation, so there is no point keeping is as a member variable. This patch moves this mapping to Calculate function and passes it to helper functions. It also makes the name more descriptive. Reviewers: sanjoy, dberlin, davide, chandlerc Reviewed By: dberlin Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D34295 llvm-svn: 306562
* [InstCombine] use local variable to reduce code; NFCISanjay Patel2017-06-281-18/+14
| | | | llvm-svn: 306560
* Rangify loops, formatting changes, use bool instead of unsigned, NFCKrzysztof Parzyszek2017-06-281-18/+16
| | | | llvm-svn: 306557
* Don't repeat names and reformat. NFC.Rafael Espindola2017-06-281-46/+37
| | | | llvm-svn: 306556
* [LoopUnroll] Pass SCEV to getUnrollingPreferences hook. NFCI.Geoff Berry2017-06-2817-37/+48
| | | | | | | | | | Reviewers: sanjoy, anna, reames, apilipenko, igor-laevsky, mkuper Subscribers: jholewinski, arsenm, mzolotukhin, nemanjai, nhaehnle, javed.absar, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D34531 llvm-svn: 306554
* Missed a check for UndefVI in r306466Krzysztof Parzyszek2017-06-282-1/+50
| | | | llvm-svn: 306553
* [globalisel][tablegen] Post-commit review nits for r306388. NFCDaniel Sanders2017-06-281-37/+31
| | | | | | One early exit and a missing assert string. llvm-svn: 306552
* [AArch64] AArch64CondBrTuningPass generates wrong branch instructionsAlexandros Lamprineas2017-06-282-7/+7
| | | | | | | | | | | Some conditional branch instructions generated by this pass are checking the wrong condition code. The instructions TBZ and TBNZ are transformed into B.GE and B.LT instead of B.PL and B.MI respectively. They should only be checking the Negative bit. Differential Revision: https://reviews.llvm.org/D34743 llvm-svn: 306550
* Don't repeat name in comments. 80 columns. NFC.Rafael Espindola2017-06-281-22/+16
| | | | llvm-svn: 306548
* [ARM] Improve if-conversion for M-class CPUs without branch predictorsJohn Brawn2017-06-286-14/+239
| | | | | | | | | | | | | The current heuristic in isProfitableToIfCvt assumes we have a branch predictor, and so gives the wrong answer in some cases when we don't. This patch adds a subtarget feature to indicate that a subtarget has no branch predictor, and changes the heuristic in isProfitableToiIfCvt when it's present. This gives a slight overall improvement in a set of embedded benchmarks on Cortex-M4 and Cortex-M33. Differential Revision: https://reviews.llvm.org/D34398 llvm-svn: 306547
* [X86] Added BSWAP tests for illegal i64/i128/i256 'wide' scalar integersSimon Pilgrim2017-06-281-0/+173
| | | | llvm-svn: 306546
* [X86][SSE] Dropped -mcpu from vector bswap testsSimon Pilgrim2017-06-281-7/+4
| | | | | | Use triple and attribute only for consistency llvm-svn: 306545
* [globalisel][tablegen] Multiple 80-col corrections.Daniel Sanders2017-06-281-20/+41
| | | | llvm-svn: 306544
* [X86][LLVM][test]Expanding Supports lowerInterleavedStore() in ↵Michael Zuckerman2017-06-281-0/+58
| | | | | | | | | X86InterleavedAccess test. Exapnding the test to include AVX target. Adding base tast (to trunk) for Store strid=4 vf=32. llvm-svn: 306543
* Create inliner params based on size and opt levels.Easwaran Raman2017-06-281-3/+11
| | | | | | Differential revision: https://reviews.llvm.org/D34309 llvm-svn: 306542
* Add zero-length check to memcpy/memset load store loop expansionTeresa Johnson2017-06-282-5/+16
| | | | | | | | | | | | | | | | Summary: I was testing using this expansion logic in other cases besides NVPTX, and found some runtime failures due to the lack of a check for a zero length memcpy/memset before the loop. There is already such a check in the memmove expansion code though. Reviewers: hfinkel Subscribers: jholewinski, wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D34707 llvm-svn: 306541
* [GlobalISel][X86] Test G_CONSTANT i32 0 TableGen'erated selection.NFC.Igor Breger2017-06-281-0/+21
| | | | llvm-svn: 306537
* Revert r306528Nikolai Bozhenov2017-06-282-1/+10
| | | | llvm-svn: 306536
* [GlobalISel][X86] Support bitwise operations : G_AND, G_OR, G_XORIgor Breger2017-06-2811-2/+1100
| | | | | | | | | | | | | | Summary: Support G_AND, G_OR, G_XOR for i8/i16/i32/i64. Selection done via TableGen'erated code. Reviewers: zvi, guyblank, aymanmus, m_zuckerman Reviewed By: aymanmus Subscribers: rovka, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D34605 llvm-svn: 306533
* Reverting commit 306414 on behalf of @gadi.haberMichael Zuckerman2017-06-2832-9532/+5254
| | | | llvm-svn: 306532
* [X86][AVX2] Dropped -mcpu from avx2 arithmetic/intrinsics testsSimon Pilgrim2017-06-2810-384/+364
| | | | | | Use triple and attribute only for consistency llvm-svn: 306531
* [X86] Correct dwarf unwind information in function epiloguePetar Jovanovic2017-06-2874-266/+1846
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CFI instructions that set appropriate cfa offset and cfa register are now inserted in emitEpilogue() in X86FrameLowering. Majority of the changes in this patch: 1. Ensure that CFI instructions do not affect code generation. 2. Enable maintaining correct information about cfa offset and cfa register in a function when basic blocks are reordered, merged, split, duplicated. These changes are target independent and described below. Changed CFI instructions so that they: 1. are duplicable 2. are not counted as instructions when tail duplicating or tail merging 3. can be compared as equal Add information to each MachineBasicBlock about cfa offset and cfa register that are valid at its entry and exit (incoming and outgoing CFI info). Add support for updating this information when basic blocks are merged, split, duplicated, created. Add a verification pass (CFIInfoVerifier) that checks that outgoing cfa offset and register of predecessor blocks match incoming values of their successors. Incoming and outgoing CFI information is used by a late pass (CFIInstrInserter) that corrects CFA calculation rule for a basic block if needed. That means that additional CFI instructions get inserted at basic block beginning to correct the rule for calculating CFA. Having CFI instructions in function epilogue can cause incorrect CFA calculation rule for some basic blocks. This can happen if, due to basic block reordering, or the existence of multiple epilogue blocks, some of the blocks have wrong cfa offset and register values set by the epilogue block above them. Patch by Violeta Vukobrat. Differential Revision: https://reviews.llvm.org/D18046 llvm-svn: 306529
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