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* Revert "(HEAD -> master, origin/master, origin/HEAD) CodeGen: Remove ↵Matthias Braun2016-08-2325-95/+174
| | | | | | | | | | MachineFunctionAnalysis => Enable (Machine)ModulePasses" Reverting while tracking down a use after free. This reverts commit r279502. llvm-svn: 279503
* CodeGen: Remove MachineFunctionAnalysis => Enable (Machine)ModulePassesMatthias Braun2016-08-2325-174/+95
| | | | | | | | | | | | | | | | | | | This patch removes the MachineFunctionAnalysis. Instead we keep a map from IR Function to MachineFunction in the MachineModuleInfo. This allows the insertion of ModulePasses into the codegen pipeline without breaking it because the MachineFunctionAnalysis gets dropped before a module pass. Peak memory should stay unchanged without a ModulePass in the codegen pipeline: Previously the MachineFunction was freed at the end of a codegen function pipeline because the MachineFunctionAnalysis was dropped; With this patch the MachineFunction is freed after the AsmPrinter has finished. Differential Revision: http://reviews.llvm.org/D23736 llvm-svn: 279502
* BranchRelaxation: Fix handling of blocks with multiple conditionalMatt Arsenault2016-08-232-12/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | branches Looping over all terminators exposed AArch64 tests hitting an assert from analyzeBranch failing. I believe these cases were miscompiled before. e.g. fcmp s0, s1 b.ne LBB0_1 b.vc LBB0_2 b LBB0_2 LBB0_1: ; Large block LBB0_2: ; ... Both of the individual conditional branches need to be expanded, since neither can reach the final block. Split the original block into ones which analyzeBranch will be able to understand. llvm-svn: 279499
* [lanai] Make Lanai backend non-experimentalJacques Pienaar2016-08-231-0/+1
| | | | | | | | | | | | | | | Summary: Add Lanai backend to default targets. Discussion of proposal: http://lists.llvm.org/pipermail/llvm-dev/2016-July/102480.html. ISA added in r279149. Reviewers: jyknight, rengolin, eliben, chandlerc Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D22530 llvm-svn: 279498
* [lanai] Exit early in Mem Alu combiner if sentinel reach.Jacques Pienaar2016-08-231-0/+3
| | | | | | LanaiMemAluCombiner could try to query the debug value of a list sentinel. Add check to exit early instead. llvm-svn: 279497
* [MemorySSA] Remove unused field. NFC.George Burgess IV2016-08-221-6/+1
| | | | | | | | Given that we're not currently using blocker info, and whether or not we will end up using it it is unclear, don't waste 8 (or 4) bytes of memory per path node. llvm-svn: 279493
* [InstSimplify] add helper function for SimplifyICmpInst(); NFCISanjay Patel2016-08-221-133/+143
| | | | | | | | | And add a FIXME because the helper excludes folds for vectors. It's not clear yet how many of these are actually testable (and therefore necessary?) because later analysis uses computeKnownBits and other methods to catch many of these cases. llvm-svn: 279492
* Fix crash from assert in r279466.Pete Cooper2016-08-221-1/+1
| | | | | | | | | | The assert in r279466 checks that we call the correct version of Intrinsic::getName. The version which accepts only an ID should not be used for intrinsics with overloaded types. The global-isel code was calling the wrong version. The test CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll will ensure that we call the correct version from now on. llvm-svn: 279487
* ADT: Separate some list manipulation API into ilist_base, NFCDuncan P. N. Exon Smith2016-08-226-78/+295
| | | | | | | | | | | | | | | | | | Separate algorithms in iplist<T> that don't depend on T into ilist_base, and unit test them. While I was adding unit tests for these algorithms anyway, I also added unit tests for ilist_node_base and ilist_sentinel<T>. To make the algorithms and unit tests easier to write, I also did the following minor changes as a drive-by: - encapsulate Prev/Next in ilist_node_base to so that algorithms are easier to read, and - update ilist_node_access API to take nodes by reference. There should be no real functionality change here. llvm-svn: 279484
* Fix header comment for unittests/ADT/ilistTest.cppDuncan P. N. Exon Smith2016-08-221-1/+1
| | | | llvm-svn: 279483
* [ADT] Actually mutate the iterator VisitStack.back().second, not its copy.Tim Shen2016-08-225-229/+312
| | | | | | | | | | | | | | | Summary: Before the change, *Opt never actually gets updated by the end of toNext(), so for every next time the loop has to start over from child_begin(). This bug doesn't affect the correctness, since Visited prevents it from re-entering the same node again; but it's slow. Reviewers: dberris, dblaikie, dannyb Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D23649 llvm-svn: 279482
* [InstCombine] change param type from Instruction to BinaryOperator for icmp ↵Sanjay Patel2016-08-222-97/+109
| | | | | | | | helpers; NFCI This saves some casting in the helper functions and eases some further refactoring. llvm-svn: 279478
* [GraphTraits] Replace all NodeType usage with NodeRefTim Shen2016-08-2224-234/+141
| | | | | | | | This should finish the GraphTraits migration. Differential Revision: http://reviews.llvm.org/D23730 llvm-svn: 279475
* ADT: Remove ilist_*sentinel_traits, NFCDuncan P. N. Exon Smith2016-08-2218-80/+3
| | | | | | | | | | Remove all the dead code around ilist_*sentinel_traits. This is a follow-up to gutting them as part of r279314 (originally r278974), staged to prevent broken builds in sub-projects. Uses were removed from clang in r279457 and lld in r279458. llvm-svn: 279473
* [InstCombine] use m_APInt to allow icmp (shr exact X, Y), 0 folds for splat ↵Sanjay Patel2016-08-222-18/+15
| | | | | | constant vectors llvm-svn: 279472
* Add ADT headers to the cmake headers directory for LLVMSupport. NFC.Pete Cooper2016-08-221-0/+1
| | | | | | | | | Xcode and MSVC list the headers and source files for each library. LLVMSupport lists included the source files for ADT but not the headers. This add the ADT headers so that they are browsable by the UI. llvm-svn: 279470
* Add comments and an assert to follow-up on r279113. NFC.Pete Cooper2016-08-222-0/+8
| | | | | | | | | | | Philip commented on r279113 to ask for better comments as to when to use the different versions of getName. Its also possible to assert in the simple case that we aren't an overloaded intrinsic as those have to use the more capable version of getName. Thanks for the comments Philip. llvm-svn: 279466
* IDFCalculator: Remove unused field.Daniel Berlin2016-08-221-1/+0
| | | | llvm-svn: 279465
* AMDGPU: Split SILowerControlFlow into two piecesMatt Arsenault2016-08-228-365/+555
| | | | | | | | | | | | | | Do most of the lowering in a pre-RA pass. Keep the skip jump insertion late, plus a few other things that require more work to move out. One concern I have is now there may be COPY instructions which do not have the necessary implicit exec uses if they will be lowered to v_mov_b32. This has a positive effect on SGPR usage in shader-db. llvm-svn: 279464
* MSSA: Factor out phi node placementDaniel Berlin2016-08-222-17/+24
| | | | llvm-svn: 279462
* MSSA: Only rename accesses whose defining access is nullptrDaniel Berlin2016-08-221-14/+6
| | | | llvm-svn: 279461
* [SimplifyCFG] Rewrite SinkThenElseCodeToEndJames Molloy2016-08-225-153/+470
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Recommitting now an unrelated assertion in SROA is sorted out] The new version has several advantages: 1) IMSHO it's more readable and neater 2) It handles loads and stores properly 3) It can handle any number of incoming blocks rather than just two. I'll be taking advantage of this in a followup patch. With this change we can now finally sink load-modify-store idioms such as: if (a) return *b += 3; else return *b += 4; => %z = load i32, i32* %y %.sink = select i1 %a, i32 5, i32 7 %b = add i32 %z, %.sink store i32 %b, i32* %y ret i32 %b When this works for switches it'll be even more powerful. Round 4. This time we should handle all instructions correctly, and not replace any operands that need to be constant with variables. This was really hard to determine safely, so the helper function should be put into the Instruction API. I'll do that as a followup. llvm-svn: 279460
* [SROA] Remove incorrect assertionJames Molloy2016-08-221-3/+0
| | | | | | | | | Confirmed with aprantl, this assertion is incorrect - code can get here (for example 80-bit FP types) and if it does it's benign. This is exposed by a completely unrelated patch of mine, so stop the compiler falling over. Original differential: http://reviews.llvm.org/D16187 aprantl's advice to remove assertion: http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20160815/382129.html llvm-svn: 279454
* [SSP] Do not set __guard_local to hidden for OpenBSD SSPTim Shen2016-08-221-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | __guard_local is defined as long on OpenBSD. If the source file contains a definition of __guard_local, it mismatches with the int8 pointer type used in LLVM. In that case, Module::getOrInsertGlobal() returns a cast operation instead of a GlobalVariable. Trying to set the visibility on the cast operation leads to random segfaults (seen when compiling the OpenBSD kernel, which also runs with stack protection). In the kernel, the hidden attribute does not matter. For userspace code, __guard_local is defined as hidden in the startup code. If a program re-defines __guard_local, the definition from the startup code will either win or the linker complains about multiple definitions (depending on whether the re-defined __guard_local is placed in the common segment or not). It also matches what gcc on OpenBSD does. Thanks Stefan Kempf <sisnkemp@gmail.com> for the patch! Differential Revision: http://reviews.llvm.org/D23674 llvm-svn: 279449
* [InstCombine] Allow sinking from unique predecessor with multiple edgesJun Bum Lim2016-08-222-1/+24
| | | | | | | | | | | | Summary: We can allow sinking if the single user block has only one unique predecessor, regardless of the number of edges. Note that a switch statement with multiple cases can have the same destination. Reviewers: mcrosier, majnemer, spatel, reames Subscribers: reames, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D23722 llvm-svn: 279448
* Revert "[SimplifyCFG] Rewrite SinkThenElseCodeToEnd"James Molloy2016-08-225-470/+153
| | | | | | This reverts commit r279443. It caused buildbot failures. llvm-svn: 279447
* [SimplifyCFG] Rewrite SinkThenElseCodeToEndJames Molloy2016-08-225-153/+470
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new version has several advantages: 1) IMSHO it's more readable and neater 2) It handles loads and stores properly 3) It can handle any number of incoming blocks rather than just two. I'll be taking advantage of this in a followup patch. With this change we can now finally sink load-modify-store idioms such as: if (a) return *b += 3; else return *b += 4; => %z = load i32, i32* %y %.sink = select i1 %a, i32 5, i32 7 %b = add i32 %z, %.sink store i32 %b, i32* %y ret i32 %b When this works for switches it'll be even more powerful. Round 4. This time we should handle all instructions correctly, and not replace any operands that need to be constant with variables. This was really hard to determine safely, so the helper function should be put into the Instruction API. I'll do that as a followup. llvm-svn: 279443
* [X86][AVX] Don't use SubVectorBroadcast if there are additional users of the ↵Simon Pilgrim2016-08-224-4/+84
| | | | | | | | chain (PR29088) We could improve on this by making X86SubVBroadcast a full memory intrinsic similar to X86vzload llvm-svn: 279441
* Fix Gold Plugin after API change in the LTO API (constify callback type)Mehdi Amini2016-08-221-2/+2
| | | | llvm-svn: 279440
* [mips][ias] Support .dtprel[d]word and .tprel[d]word directivesSimon Atanasyan2016-08-2213-8/+267
| | | | | | | | | | | | | Assembler directives .dtprelword, .dtpreldword, .tprelword, and .tpreldword generates relocations R_MIPS_TLS_DTPREL32, R_MIPS_TLS_DTPREL64, R_MIPS_TLS_TPREL32, and R_MIPS_TLS_TPREL64 respectively. The main motivation for this patch is to be able to write test cases for checking correctness of the LLD linker's behaviour. Differential Revision: https://reviews.llvm.org/D23669 llvm-svn: 279439
* [LTO] Constify the Module Hook function (NFC)Mehdi Amini2016-08-222-4/+4
| | | | | | | | It use to be non-const for the sole purpose of custom handling of commons symbol. This is moved now in the regular LTO handling now and such we can constify the callback. llvm-svn: 279438
* Reset isUndef when removing subreg from a def operandKrzysztof Parzyszek2016-08-221-0/+2
| | | | llvm-svn: 279437
* [X86] Only accept SM_SentinelUndef (-1) as an undefined shuffle mask in rangeSimon Pilgrim2016-08-221-3/+3
| | | | | | As discussed on D23027 we should be trying to be more strict on what is an undefined mask value. llvm-svn: 279435
* Remove missing file from r279433 reversalArtur Pilipenko2016-08-221-97/+0
| | | | llvm-svn: 279434
* Revert -r278267 [ValueTracking] An improvement to IR ValueTracking on ↵Artur Pilipenko2016-08-222-38/+2
| | | | | | | | | | Non-negative Integers This change cause performance regression on MultiSource/Benchmarks/TSVC/Symbolics-flt/Symbolics-flt from LNT and some other bechmarks. See https://reviews.llvm.org/D18777 for details. llvm-svn: 279433
* Revert -r278269 [IndVarSimplify] Eliminate zext of a signed IV when the IV ↵Artur Pilipenko2016-08-222-89/+2
| | | | | | | | | | is known to be non-negative This change needs to be reverted in order to revert -r278267 which cause performance regression on MultiSource/Benchmarks/TSVC/Symbolics-flt/Symbolics-flt from LNT and some other bechmarks. See comments on https://reviews.llvm.org/D18777 for details. llvm-svn: 279432
* [PM] Port LoopDataPrefetch AArch64 tests to new pass managerBalaram Makam2016-08-224-0/+12
| | | | | | | | | | Reviewers: mcrosier, tejohnson Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D23724 llvm-svn: 279431
* [X86][SSE] Avoid specifying unused arguments in SHUFPD loweringSimon Pilgrim2016-08-2214-201/+216
| | | | | | | | | | | | | | | | As discussed on PR26491, we are missing the opportunity to make use of the smaller MOVHLPS instruction because we set both arguments of a SHUFPD when using it to lower a single input shuffle. This patch sets the lowered argument to UNDEF if that shuffle element is undefined. This in turn makes it easier for target shuffle combining to decode UNDEF shuffle elements, allowing combines to MOVHLPS to occur. A fix to match against MOVHPD stores was necessary as well. This builds on the improved MOVLHPS/MOVHLPS lowering and memory folding support added in D16956 Adding similar support for SHUFPS will have to wait until have better support for target combining of binary shuffles. Differential Revision: https://reviews.llvm.org/D23027 llvm-svn: 279430
* [mips][microMIPS] Implement BLTZC, BLEZC, BGEZC and BGTZC instructions, fix ↵Hrvoje Varga2016-08-2219-154/+608
| | | | | | | | disassembly and add operand checking to existing B<cond>C implementations Differential Revision: https://reviews.llvm.org/D22667 llvm-svn: 279429
* [MC] Remove guard(s). NFCI.Davide Italiano2016-08-229-20/+0
| | | | | | | All the methods are already marked with LLVM_DUMP_METHOD. llvm-svn: 279428
* [ThinLTO][X86] Fix windows buildSimon Pilgrim2016-08-221-1/+2
| | | | | | Windows 'rm' complains about non-existent files if a wildcard is used. Be more explicit about the files deleted to avoid this. llvm-svn: 279426
* [X86] Create a new instruction format to handle 4VOp3 encoding. This saves ↵Craig Topper2016-08-229-82/+128
| | | | | | one bit in TSFlags and simplifies MRMSrcMem/MRMSrcReg format handling. llvm-svn: 279424
* [X86] Create a new instruction format to handle MemOp4 encoding. This saves ↵Craig Topper2016-08-227-85/+151
| | | | | | one bit in TSFlags and simplifies MRMSrcMem/MRMSrcReg format handling. llvm-svn: 279423
* [X86] Space out the encodings of X86 instruction formats. I plan to add some ↵Craig Topper2016-08-223-175/+187
| | | | | | | | new encodings in future commits and this will reduce the size of those commits. NFC This tries to keep all the ModRM memory and register forms in their own regions of the encodings. Hoping to make it simple on some of the switch statements that operate on these encodings. llvm-svn: 279422
* [X86] Merge small helper function into the switch that calls it since they ↵Craig Topper2016-08-221-17/+9
| | | | | | both operate on the same variable. NFC llvm-svn: 279421
* [X86] Explicitly list all X86 instruction forms in switch statement so its ↵Craig Topper2016-08-221-1/+10
| | | | | | easier to detect when one is missing. NFC llvm-svn: 279420
* Add REQUIRES:X86 to test/tools/llvm-lto2/common.llMehdi Amini2016-08-221-0/+1
| | | | llvm-svn: 279418
* [LTO] Handles commons in monolithic LTOMehdi Amini2016-08-225-58/+111
| | | | | | | | | The gold-plugin was doing this internally, now the API is handling commons correctly based on the given resolution. Differential Revision: https://reviews.llvm.org/D23739 llvm-svn: 279417
* [LTO] Add a "CodeGenOnly" option. Allows the client to skip the optimizer.Mehdi Amini2016-08-223-21/+32
| | | | | | | | | | | | Summary: Slowly getting on par with libLTO Reviewers: tejohnson Subscribers: llvm-commits, mehdi_amini Differential Revision: https://reviews.llvm.org/D23615 llvm-svn: 279416
* [asan] Use 1 byte aligned stores to poison shadow memoryVitaly Buka2016-08-221-2/+2
| | | | | | | | | | | | Summary: r279379 introduced crash on arm 32bit bot. I suspect this is alignment issue. Reviewers: eugenis Subscribers: llvm-commits, aemerson Differential Revision: https://reviews.llvm.org/D23762 llvm-svn: 279413
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