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* Revert r212572 "improve BasicAA CS-CS queries", it causes PR20303.Nick Lewycky2014-07-155-371/+126
| | | | llvm-svn: 213024
* Convert test to FileCheck.Matt Arsenault2014-07-151-13/+35
| | | | | | Check the individual test functions for more useful failure errors. llvm-svn: 213021
* [DAGCombiner] Avoid calling method 'isShuffleMaskLegal' on illegal vector types.Andrea Di Biagio2014-07-152-0/+14
| | | | | | | | | | | | | | | | | | This patch fixes a crasher in method 'DAGCombiner::visitOR' due to an invalid call to method 'isShuffleMaskLegal'. On x86, method 'isShuffleMaskLegal' always expects a legal vector value type in input. With this patch, we immediately check if the input OR dag node has a legal vector type; we only try to fold a OR dag node into a single shufflevector if we know that the resulting shuffle will have a legal type. This is to avoid calling method 'isShuffleMaskLegal' on a potentially illegal vector value type. Added a new test-case to file 'CodeGen/X86/combine-or.ll' to verify that DAGCombiner doesn't crash in the attempt to check/combine an OR between shuffles with illegal types. llvm-svn: 213020
* R600: Add denormal handling subtarget features.Matt Arsenault2014-07-146-8/+79
| | | | llvm-svn: 213018
* R600/SI: Default to no single precision denormals.Matt Arsenault2014-07-142-2/+10
| | | | llvm-svn: 213017
* Revert "Revert "Move clang feature flags settings out of LLVM core and into ↵Alp Toker2014-07-141-16/+0
| | | | | | | | | | cfe"" It turns out this commit was fine. The problem was in the legacy build system (fixed r213010). This reverts commit r213005. llvm-svn: 213015
* [RuntimeDyld] Handle endiannes differences between the host and target whileLang Hames2014-07-141-14/+19
| | | | | | | | | | reading MachO files magic numbers in RuntimeDyld. This is required now that we're testing cross-platform JITing (via RuntimeDyldChecker), and should fix some issues that David Fang has seen on PPC builds. llvm-svn: 213012
* [X86] Specify all TSFlags bit-offsets symbolicallyAdam Nemet2014-07-141-3/+6
| | | | | | | | | | | | | | | No functional change. The offsets for the other bitfields are specified symbolically. I need to increase the size for one of the earlier fields which is easier after this cleanup. Why these bits are relative to VEXShift is a bit strange but that is for another cleanup. I made sure that the values for the enums are unchanged after this change. llvm-svn: 213011
* CodeGen: Stick constant pool entries in COMDAT sections for WinCOFFDavid Majnemer2014-07-1416-27/+191
| | | | | | | | | | | | | | | | COFF lacks a feature that other object file formats support: mergeable sections. To work around this, MSVC sticks constant pool entries in special COMDAT sections so that each constant is in it's own section. This permits unused constants to be dropped and it also allows duplicate constants in different translation units to get merged together. This fixes PR20262. Differential Revision: http://reviews.llvm.org/D4482 llvm-svn: 213006
* Revert "Move clang feature flags settings out of LLVM core and into cfe"Alp Toker2014-07-141-0/+16
| | | | | | | | | This broke one of the builds, presumably side-by-side modular CMake. Investigating. This reverts commit r212998. llvm-svn: 213005
* Fix a -Wunused-local-typedefs warningAlp Toker2014-07-141-1/+1
| | | | llvm-svn: 213002
* [DAGCombiner] Add more rules to combine shuffle vector dag nodes.Andrea Di Biagio2014-07-142-0/+417
| | | | | | | | | | | | | | | | This patch teaches the DAGCombiner how to fold a pair of shuffles according to rules: 1. shuffle(shuffle A, B, M0), B, M1) -> shuffle(A, B, M2) 2. shuffle(shuffle A, B, M0), A, M1) -> shuffle(A, B, M3) The new rules would only trigger if the resulting shuffle has legal type and legal mask. Added test 'combine-vec-shuffle-3.ll' to verify that DAGCombiner correctly folds shuffles on x86 when the resulting mask is legal. Also added some negative cases to verify that we avoid introducing illegal shuffles. llvm-svn: 213001
* Look through addrspacecast in IsConstantOffsetFromGlobalMatt Arsenault2014-07-142-1/+15
| | | | llvm-svn: 213000
* Look through addrspacecast in GetPointerBaseWithConstantOffsetMatt Arsenault2014-07-142-1/+15
| | | | llvm-svn: 212999
* Move clang feature flags settings out of LLVM core and into cfeAlp Toker2014-07-141-16/+0
| | | | | | | clang r212997 incorporated these settings into its own build system. They no longer need to be set from LLVM. llvm-svn: 212998
* CodeGen: Add a getSectionKind method to MachineConstantPoolEntryDavid Majnemer2014-07-143-15/+35
| | | | | | This is just a helper routine, no functionality has changed. llvm-svn: 212993
* Convert test to FileCheckMatt Arsenault2014-07-141-31/+52
| | | | llvm-svn: 212992
* ADT: Surface LowerCase argument for utohexstrDavid Majnemer2014-07-141-4/+4
| | | | | | | | The underlying function. utohex_buffer, already supports an argument for deciding if the hex characters should be upper or lower case. Expose an identical argument for utohexstr. llvm-svn: 212991
* removed circular definitions in commentsSanjay Patel2014-07-141-5/+5
| | | | llvm-svn: 212990
* Support: Fix option handling when using cl::Required with aliasoptJustin Bogner2014-07-143-4/+27
| | | | | | | | | | | | | | | | Until now, attempting to create an alias of a required option would complain if the user supplied the alias, because the required option didn't have a value. Similarly, if you said the alias was required, then using the base option would complain that the alias wasn't supplied. Lastly, if you put required on both, *neither* option would work. By changning alias to overload addOccurrence and setting cl::Required on the original option, we can get this to behave in a more useful way. I've also added a test and updated a user that was getting this wrong. llvm-svn: 212986
* Fix a test broken in r212981David Majnemer2014-07-141-1/+1
| | | | | | | @icmp_sdiv_neg1 should have referred to %a instead of %call, it was renamed at the last second. llvm-svn: 212983
* InstSimplify: Correct sdiv x / -1David Majnemer2014-07-142-11/+24
| | | | | | | | | | | Determining the bounds of x/ -1 would start off with us dividing it by INT_MIN. Suffice to say, this would not work very well. Instead, handle it upfront by checking for -1 and mapping it to the range: [INT_MIN + 1, INT_MAX. This means that the result of our division can be any value other than INT_MIN. llvm-svn: 212981
* fixed linkSanjay Patel2014-07-141-1/+1
| | | | llvm-svn: 212977
* InstSimplify: The upper bound of X / C was missing a rounding stepDavid Majnemer2014-07-142-1/+20
| | | | | | | | | | | | | | | | | | Summary: When calculating the upper bound of X / -8589934592, we would perform the following calculation: Floor[INT_MAX / 8589934592] However, flooring the result would make us wrongly come to the conclusion that 1073741824 was not in the set of possible values. Instead, use the ceiling of the result. Reviewers: nicholas Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D4502 llvm-svn: 212976
* Support: Use a range-based forJustin Bogner2014-07-141-5/+4
| | | | llvm-svn: 212973
* Look through addrspacecast when checking isDereferenceablePointerMatt Arsenault2014-07-142-0/+41
| | | | llvm-svn: 212971
* Don't eliminate memcpy's when the address of the pointer may itself be ↵Nick Lewycky2014-07-147-7/+35
| | | | | | relevant. Fixes PR18304. Patch by David Wiberg! llvm-svn: 212970
* Unify the lowering of arguments during SjLj prepare.Bill Wendling2014-07-142-29/+11
| | | | | | | The 'select true, %arg, undef' instruction can be used for both aggregate and non-aggregate arguments. llvm-svn: 212967
* fixed typoSanjay Patel2014-07-141-1/+1
| | | | llvm-svn: 212966
* Use pointer type cast helpers.Matt Arsenault2014-07-141-3/+2
| | | | llvm-svn: 212963
* Add CreatePointerBitCastOrAddrSpaceCast to IRBuilder and co.Matt Arsenault2014-07-145-8/+70
| | | | llvm-svn: 212962
* Update comments to include addrspacecastMatt Arsenault2014-07-141-2/+2
| | | | llvm-svn: 212961
* Remove GCC 3.3 workaroundMatt Arsenault2014-07-141-8/+3
| | | | llvm-svn: 212960
* X86: correct 64-bit atomics on 32-bitSaleem Abdulrasool2014-07-142-12/+9
| | | | | | | | | | | | | | | | We would emit a libcall for a 64-bit atomic on x86 after SVN r212119. This was due to the misuse of hasCmpxchg16 to indicate if cmpxchg8b was supported on a 32-bit target. They were added at different times and would result in the border condition being mishandled. This fixes the border case to emit the cmpxchg8b instruction for 64-bit atomic operations on x86 at the cost of restoring a long-standing bug in the codegen. We emit a cmpxchg8b on all x86 targets even where the CPU does not support this instruction (pre-Pentium CPUs). Although this bug should be fixed, this was present prior to SVN r212119 and this change, so this is not really introducing a regression. llvm-svn: 212956
* CodeGen: add missing includeSaleem Abdulrasool2014-07-141-0/+1
| | | | | | | Found during windows unwinding work. This header is indirectly included through a chain leading through Support/Win64EH.h. Explicitly include the header. NFC. llvm-svn: 212955
* llvm-objdump: Handle BSS sections larger than the object fileDavid Majnemer2014-07-143-4/+14
| | | | | | | | | The size of the uninitialized sections, like BSS, can exceed the size of the object file. Do not attempt to grab the contents of such sections. llvm-svn: 212953
* X86: remove temporary atomicrmw used during lowering.Tim Northover2014-07-142-2/+6
| | | | | | | | | | | We construct a temporary "atomicrmw xchg" instruction when lowering atomic stores for widths that aren't supported natively. This isn't on the top-level worklist though, so it won't be removed automatically and we have to do it ourselves once that itself has been lowered. Thanks Saleem for pointing this out! llvm-svn: 212948
* Re-commit: [mips] Correct section alignments and EntrySizes for .bss, .text, ↵Daniel Sanders2014-07-1412-221/+235
| | | | | | | | .data, .reginfo, .MIPS.options, and .MIPS.abiflags The lld tests will temporarily fail again but Simon Atanasyan will commit a fix for those shortly. llvm-svn: 212946
* Revert: [mips] Correct section alignments and EntrySizes for .bss, .text, ↵Daniel Sanders2014-07-1412-235/+221
| | | | | | | | .data, .reginfo, .MIPS.options, and .MIPS.abiflags This commit causes multiple lld tests to fail. Reverting while I investigate the issue. llvm-svn: 212945
* [mips] Correct section alignments and EntrySizes for .bss, .text, .data, ↵Daniel Sanders2014-07-1412-221/+235
| | | | | | | | | | | | | | | | | | .reginfo, .MIPS.options, and .MIPS.abiflags Summary: .bss, .text, and .data are at least 16-byte aligned. .reginfo is 4-byte aligned and has a 24-byte EntrySize. .MIPS.abiflags has an 24-byte EntrySize. .MIPS.options is 8-byte aligned and has 1-byte EntrySize. Using a 1-byte EntrySize for .MIPS.options seems strange because the records are neither 1-byte long nor fixed-length but this matches the value that GAS emits. Differential Revision: http://reviews.llvm.org/D4487 llvm-svn: 212939
* [mips] For the FP64A ABI, odd-numbered double-precision moves must not use ↵Daniel Sanders2014-07-147-71/+443
| | | | | | | | | | | | | | | | | | | | | mtc1/mfc1. Summary: This is because the FP64A the hardware will redirect 32-bit reads/writes from/to odd-numbered registers to the upper 32-bits of the corresponding even register. In effect, simulating FR=0 mode when FR=0 mode is not available. Unfortunately, we have to make the decision to avoid mfc1/mtc1 before register allocation so we currently do this for even registers too. FPXX has a similar requirement on 32-bit architectures that lack mfhc1/mthc1 so this patch also handles the affected moves from the FPU for FPXX too. Moves to the FPU were supported by an earlier commit. Differential Revision: http://reviews.llvm.org/D4484 llvm-svn: 212938
* [mips] Use MFHC1 when it is available (MIPS32r2 and later) for both FP32 and ↵Daniel Sanders2014-07-146-186/+182
| | | | | | | | | | | | | | FP64 moves Summary: This is similar to r210771 which did the same thing for MTHC1. Also corrected MTHC1_D32 and MTHC1_D64 which used AFGR64 and FGR64 on the wrong definitions. Differential Revision: http://reviews.llvm.org/D4483 llvm-svn: 212936
* [CMake][Win32.DLL] Let llvm_add_library(SHARED) link dependent libraries as ↵NAKAMURA Takumi2014-07-141-0/+7
| | | | | | | | | | | | | | PRIVATE. For example, c-index-test.exe requires just libclang.dll (its import library). When libraries in libclang were not PRIVATE but PUBLIC, c-index-test required libraries transitive by libclang. Note, on mingw with BUILD_SHARED_LIBS, library dependencies would become more strict. In principle, required libraries should be "required in its source file". This will help to detect missing dependencies. llvm-svn: 212934
* AArch64: remove unnecessary pseudo-instruction.Tim Northover2014-07-143-17/+5
| | | | | | | Sufficiently twisted use of TableGen lets us write patterns directly for f16 (as an i16 promoted to i32) -> f32 conversion. llvm-svn: 212933
* [mips] Correct the AFL_FLAGS1_ODDSPREG flag in .MIPS.abiflags when no ↵Daniel Sanders2014-07-1410-11/+26
| | | | | | | | '.module oddspreg' is used Differential Revision: http://reviews.llvm.org/D4486 llvm-svn: 212932
* [mips] Expand BuildPairF64 to a spill and reload when the O32 FPXX ABI isSasa Stankovic2014-07-148-13/+226
| | | | | | | | | | | | | | | enabled and mthc1 and dmtc1 are not available (e.g. on MIPS32r1) This prevents the upper 32-bits of a double precision value from being moved to the FPU with mtc1 to an odd-numbered FPU register. This is necessary to ensure that the code generated executes correctly regardless of the current FPU mode. MIPS32r2 and above continues to use mtc1/mthc1, while MIPS-IV and above continue to use dmtc1. Differential Revision: http://reviews.llvm.org/D4465 llvm-svn: 212930
* Support lowering of empty aggregates.Bill Wendling2014-07-142-11/+42
| | | | | | | | | | | | | This crash was pretty common while compiling Rust for iOS (armv7). Reason - SjLj preparation step was lowering aggregate arguments as ExtractValue + InsertValue. ExtractValue has assertion which checks that there is some data in value, which is not true in case of empty (no fields) structures. Rust uses them quite extensively so this patch uses a 'select true, %val, undef' instruction to lower the argument. Patch by Valerii Hiora. llvm-svn: 212922
* [CMake] LINK_COMPONENTS: Add also corresponding MCTargetDesc and TargetInfo ↵NAKAMURA Takumi2014-07-141-0/+9
| | | | | | as well, when target names or "nativecodegen" are specified. llvm-svn: 212921
* [CMake] Update libdeps.NAKAMURA Takumi2014-07-1415-0/+17
| | | | llvm-svn: 212920
* NVPTX/LLVMBuild.txt: Add "Scalar" to required_libraries. It is really ↵NAKAMURA Takumi2014-07-141-1/+1
| | | | | | referenced. llvm-svn: 212918
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