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* Check the alwaysinline attribute on the call as well as on the caller.Peter Collingbourne2014-05-193-3/+13
| | | | | | Differential Revision: http://reviews.llvm.org/D3815 llvm-svn: 209150
* Use range forMatt Arsenault2014-05-191-4/+1
| | | | llvm-svn: 209147
* reverting r209132Jyotsna Verma2014-05-194-703/+250
| | | | llvm-svn: 209139
* MemoryBuffer: Use GetNativeSystemInfo()Alp Toker2014-05-192-17/+6
| | | | | | | Removes old 4096 byte workaround. This functionality has been available since Windows XP. llvm-svn: 209137
* Revert "Patch for function cloning to inline all blocks whose address is taken"Eric Christopher2014-05-191-106/+34
| | | | | | | | as it was causing build failures in ruby. This reverts commit r207713. llvm-svn: 209135
* [ARM64] Split tbz/tbnz into W/X register variantBradley Smith2014-05-199-66/+146
| | | | llvm-svn: 209134
* Hexagon: Add encoding bits to the mpy instructions.Jyotsna Verma2014-05-194-250/+703
| | | | llvm-svn: 209132
* [mips][mips64r6] Sorted *_ENC, *_DESC classes and testsZoran Jovanovic2014-05-193-153/+160
| | | | | | Differential Revision: http://reviews.llvm.org/D3808 llvm-svn: 209129
* Resolving MSVC warnings about switch statements with a default label, but no ↵Aaron Ballman2014-05-192-11/+6
| | | | | | case labels. No functional changes intended. llvm-svn: 209126
* Flip on vectorization of bswap intrinsics.Benjamin Kramer2014-05-192-0/+45
| | | | | | | | | The cost model conservatively assumes that it will always get scalarized and that's about as good as we can get with the generic TTI; reasoning whether a shuffle with an efficient lowering is available is hard. We can override that conservative estimate for some targets in the future. llvm-svn: 209125
* SDAG: Legalize vector BSWAP into a shuffle if the shuffle is legal but the ↵Benjamin Kramer2014-05-199-7/+184
| | | | | | | | | | bswap not. - On ARM/ARM64 we get a vrev because the shuffle matching code is really smart. We still unroll anything that's not v4i32 though. - On X86 we get a pshufb with SSSE3. Required more cleverness in isShuffleMaskLegal. - On PPC we get a vperm for v8i16 and v4i32. v2i64 is unrolled. llvm-svn: 209123
* Added inst-combine for 'MIN(MIN(A, 97), 23)' and 'MAX(MAX(A, 23), 97)'Dinesh Dwivedi2014-05-192-5/+65
| | | | | | | | | | | This removes TODO added in r208849 [http://reviews.llvm.org/D3629] MIN(MIN(A, 97), 23) -> MIN(A, 23) MAX(MAX(A, 23), 97) -> MAX(A, 97) Differential Revision: http://reviews.llvm.org/D3785 llvm-svn: 209110
* Change the blend tests to AVX, not AVX2.Filipe Cabecinhas2014-05-191-1/+1
| | | | llvm-svn: 209107
* Reformat blank lines.NAKAMURA Takumi2014-05-1913-14/+5
| | | | llvm-svn: 209106
* Whitespace.NAKAMURA Takumi2014-05-196-28/+27
| | | | llvm-svn: 209105
* Remove last uses of OwningPtr from llvm. As far as I can tell these method ↵Craig Topper2014-05-186-106/+0
| | | | | | versions are not used by lldb, lld, or clang. llvm-svn: 209103
* Use std::unique_ptr instead of OwningPtr in the MemoryBuffer unittests.Craig Topper2014-05-182-7/+5
| | | | llvm-svn: 209102
* ARM: make libcall setup more table drivenSaleem Abdulrasool2014-05-181-161/+100
| | | | | | | | | Rather than create a series of function calls to setup the library calls, create a table with the information and just use the table to drive the configuration of the library calls. This makes it easier to both inspect the list as well as to modify it. NFC. llvm-svn: 209089
* Options: Use erase_if to remove Args from the list.Benjamin Kramer2014-05-182-9/+4
| | | | | | | While there make getOption return a const reference so we don't have to put it on the stack when calling methods on it. No functionality change. llvm-svn: 209088
* ARM: improve WoA ABI conformance for frame registerSaleem Abdulrasool2014-05-183-3/+67
| | | | | | | | | Windows on ARM uses R11 for the frame pointer even though the environment is a pure Thumb-2, thumb-only environment. Replicate this behaviour to improve Windows ABI compatibility. This register is used for fast stack walking, and thus is part of the Windows ABI. llvm-svn: 209085
* ARM: consolidate frame pointer register knowledgeSaleem Abdulrasool2014-05-181-3/+5
| | | | | | | | | | | Use the ARMBaseRegisterInfo to query the frame register. The base register info is aware of the frame register that is used for the frame pointer. Use that to determine the frame register rather than duplicating the knowledge. Although, the code path is slightly different in that it may return SP, that can only occur if the frame pointer has been omitted in the machine function, which is supposed to contain the desired value in that case. llvm-svn: 209084
* Target: remove old constructors for CallLoweringInfoSaleem Abdulrasool2014-05-1719-256/+190
| | | | | | | | | | This is mostly a mechanical change changing all the call sites to the newer chained-function construction pattern. This removes the horrible 15-parameter constructor for the CallLoweringInfo in favour of setting properties of the call via chained functions. No functional change beyond the removal of the old constructors are intended. llvm-svn: 209082
* Target: add support to build CallLoweringInfoSaleem Abdulrasool2014-05-171-0/+86
| | | | | | | | | | | Rather than introducing an auxiliary CallLoweringInfoBuilder, add the methods to do chained function construction directly to CallLoweringInfo. This reduces the monstrous 15-parameter constructor into a series of simpler (for some definition of simpler) functions that control particular aspects of the call. The old interfaces can be completely removed once callers are moved to the new chained constructor pattern. llvm-svn: 209081
* Target: change member from reference to pointerSaleem Abdulrasool2014-05-176-10/+15
| | | | | | | | | This is a preliminary step to help ease the construction of CallLoweringInfo. Changing the construction to a chained function pattern requires that the parameter be nullable. However, rather than copying the vector, save a pointer rather than the reference to permit a late binding of the arguments. llvm-svn: 209080
* ARM: whitespaceSaleem Abdulrasool2014-05-171-3/+3
| | | | | | Remove some whitespace. NFC. llvm-svn: 209079
* Use create methods since msvc doesn't handle delegating constructors.Rafael Espindola2014-05-1711-40/+62
| | | | llvm-svn: 209076
* Handle ConstantAggregateZero when upgrading global_ctors.Rafael Espindola2014-05-173-6/+12
| | | | llvm-svn: 209075
* Reduce abuse of default values in the GlobalAlias constructor.Rafael Espindola2014-05-1711-28/+52
| | | | | | This is in preparation for adding an optional offset. llvm-svn: 209073
* Revert r209049 and r209065, "Add support for combining GEPs across PHI nodes"NAKAMURA Takumi2014-05-172-122/+0
| | | | | | It broke clang selfhosting even after r209065. llvm-svn: 209067
* MachO: Add comments describing section flags/attrsDavid Majnemer2014-05-171-0/+48
| | | | | | | | | | | | | | When pruning superfluous MachO structure definitions, I chose to keep the most generically useful which is why Support's definitions won over the ones in MC. However, the MC copy had some useful comments describing some of the field values. Bring these back to the copy in Support. While doing this, fill in some of the underdocumented definitions as well. llvm-svn: 209066
* Fix for sanitizer crash introduced in r209049Louis Gerbarg2014-05-171-1/+8
| | | | | | | | | | This patch fixes 3 issues introduced by r209049 that only showed up in on the sanitizer buildbots. One was a typo in a compare. The other is a check to confirm that the single differing value in the two incoming GEPs is the same type. The final issue was the the IRBuilder under some circumstances would build PHIs in the middle of the block. llvm-svn: 209065
* Target: Replace getSection().empty() with hasSection()David Majnemer2014-05-171-1/+1
| | | | | | No functional change, just a small cleanup. llvm-svn: 209064
* test: fix copy-paste mistakeSaleem Abdulrasool2014-05-171-1/+1
| | | | | | Accidental over-quoting of the match string. llvm-svn: 209058
* ARM: use the proper target object format for WoASaleem Abdulrasool2014-05-172-1/+17
| | | | | | | | WoA uses COFF, not ELF. ARMISelLowering::createTLOF would previously return ELF for any non-MachO platform. This was a missed site when the original change for target format support for Windows on ARM was done. llvm-svn: 209057
* [x86] Fix a bad predicate I spotted by inspection -- pshufhw and pshuflwChandler Carruth2014-05-172-3/+3
| | | | | | | | | | were added in SSE2, no SSSE3. Found this while auditing all uses of SSSE3 in the X86 target. I don't actually expect this to make a significant difference on anything and I don't have any detailed test cases but I updated the existing test cases that already covered some of this code path. llvm-svn: 209056
* [DWARF parser] Teach DIContext to fetch short (non-linkage) function names ↵Alexey Samsonov2014-05-177-24/+40
| | | | | | | | | | for a given address. Change --functions option in llvm-symbolizer tool to accept values "none", "short" or "linkage". Update the tests and docs accordingly. llvm-svn: 209050
* Add support for combining GEPs across PHI nodesLouis Gerbarg2014-05-162-0/+115
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently LLVM will generally merge GEPs. This allows backends to use more complex addressing modes. In some cases this is not happening because there is PHI inbetween the two GEPs: GEP1--\ |-->PHI1-->GEP3 GEP2--/ This patch checks to see if GEP1 and GEP2 are similiar enough that they can be cloned (GEP12) in GEP3's BB, allowing GEP->GEP merging (GEP123): GEP1--\ --\ --\ |-->PHI1-->GEP3 ==> |-->PHI2->GEP12->GEP3 == > |-->PHI2->GEP123 GEP2--/ --/ --/ This also breaks certain use chains that are preventing GEP->GEP merges that the the existing instcombine would merge otherwise. Tests included. rdar://15547484 llvm-svn: 209049
* Use a sized enum for MachineOperandType. No functionality changePete Cooper2014-05-162-3/+3
| | | | llvm-svn: 209048
* Added tests for the cost of lowering VSELECT instructions.Filipe Cabecinhas2014-05-161-0/+126
| | | | llvm-svn: 209045
* Implemented special cases for PerformVSELECTCombine.Filipe Cabecinhas2014-05-162-5/+67
| | | | | | | | | | vselects with constant masks, after legalization, will get turned into specialized shuffle_vectors so they can be matched to blend+imm instructions. Fixed some tests. llvm-svn: 209044
* Lower vselects into X86ISD::BLENDI when appropriate.Filipe Cabecinhas2014-05-166-19/+128
| | | | | | | | | | | | | | | | LowerVSELECT will, if possible, generate a X86ISD::BLENDI DAG node if the condition is constant and we can emit that instruction, given the subtarget. This is not enough for all cases. An additional SELECTCombine optimization will be committed. Fixed tests that were expecting variable blends but where a blend+imm can be generated. Added test where we can't emit blend+immediate. Added avx2 blend+imm tests. llvm-svn: 209043
* Implemented LowerVSELECT to custom lower some instructions.Filipe Cabecinhas2014-05-162-16/+46
| | | | | | | | No functionality change intended. The types that previously were set to lower as Expand or Legal are doing the same thing with this lowering function. llvm-svn: 209042
* Delete getAliasedGlobal.Rafael Espindola2014-05-1617-31/+19
| | | | llvm-svn: 209040
* DebugInfo: Assert rather than conditionalizing when a CU's subprogram list ↵David Blaikie2014-05-161-2/+2
| | | | | | contains declarations. llvm-svn: 209039
* DebugInfo: Handle emitting constants of C++ unicode character type.David Blaikie2014-05-162-23/+37
| | | | | | | | Patch by Stephan Tolksdorf! (with some test case stuff by me) Differential Revision: http://reviews.llvm.org/D3810 llvm-svn: 209037
* R600/SI: Refactor the VOP3_32 tablegen classTom Stellard2014-05-166-34/+112
| | | | | | | | This will allow us to use a single MachineInstr to represent instructions which behave the same but have different encodings on some subtargets. llvm-svn: 209028
* R600/SI: Add a PredicateControl class for managing TableGen predicatesTom Stellard2014-05-163-28/+22
| | | | | | This was inspired by the PredicateControl class in the MIPS backend. llvm-svn: 209027
* R600/SI: Move tablegen patterns away from instruction defsTom Stellard2014-05-161-30/+31
| | | | llvm-svn: 209026
* R600/SI: Remove unused instructionTom Stellard2014-05-161-7/+0
| | | | llvm-svn: 209025
* R600/SI: Promote f32 SELECT to i32Tom Stellard2014-05-163-7/+4
| | | | llvm-svn: 209024
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