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* [GISEL]: Move getConstantVReg to UtilsAditya Nandakumar2017-04-195-20/+21
| | | | | | NFCI llvm-svn: 300751
* [InstCombine] Add frem constant folding test (PR32177)Simon Pilgrim2017-04-191-0/+9
| | | | llvm-svn: 300750
* [ARM] Use TableGen patterns to select vtbl. NFC.Eli Friedman2017-04-194-93/+60
| | | | | | Differential Revision: https://reviews.llvm.org/D32103 llvm-svn: 300749
* [APInt] Use SignExtend64 instead of reinventing it. NFCCraig Topper2017-04-191-2/+1
| | | | llvm-svn: 300747
* [SCEV] Make SCEV or modeling more aggressive.Eli Friedman2017-04-192-22/+44
| | | | | | | | | | Use haveNoCommonBitsSet to figure out whether an "or" instruction is equivalent to addition. This handles more cases than just checking for a constant on the RHS. Differential Revision: https://reviews.llvm.org/D32239 llvm-svn: 300746
* Using address range map to speedup finding inline stack for address.Dehao Chen2017-04-195-52/+99
| | | | | | | | | | | | | | | | | | | | Summary: In the current implementation, to find inline stack for an address incurs expensive linear search in 2 places: * linear search for the top-level DIE * recursive linear traverse the DIE tree to find the path to the leaf DIE In this patch, a map is built from address to its corresponding leaf DIE. The inline stack is built by traversing from the leaf DIE up to the root DIE. This speeds up batch symbolization by ~10X without noticible memory overhead. Reviewers: dblaikie Reviewed By: dblaikie Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D32177 llvm-svn: 300742
* Update the madd.ll test with utils/update_llc_test_checks.py (NFC)Dehao Chen2017-04-191-48/+264
| | | | llvm-svn: 300740
* PR32710: Disable using PMADDWD for unsigned short.Dehao Chen2017-04-192-6/+56
| | | | | | | | | | | | | | Summary: PMADDWD can only handle signed short. Reviewers: mkuper, wmi Reviewed By: mkuper Subscribers: andreadb, llvm-commits Differential Revision: https://reviews.llvm.org/D32236 llvm-svn: 300737
* AMDGPU: Don't emit amd_kernel_code_t for callable functionsMatt Arsenault2017-04-192-8/+21
| | | | | | | | | | | | This is inserted directly in the text section. The relocation for the function ends up resolving to the beginning of the amd_kernel_code_t header rather than the actual function entry point. Also skip some of the comments for initialization that only makes sense for kernels. llvm-svn: 300736
* [tblgen] GCC/MS builtin to target intrisics map.Aditya Nandakumar2017-04-192-7/+17
| | | | | | | | | | | Patch by Ettore Speziale Allow TableGen to generate static functions to perform GCC/MS builtin name to target specific intrinsic ID mapping. https://reviews.llvm.org/D31150 llvm-svn: 300735
* [AMDGPU][mc][tests][NFC] Update bulk ISA tests for Gfx7 and Gfx8Artem Tamazov2017-04-192-4377/+10806
| | | | | | Added approx. 1100 gfx7 and 1040 gfx8 test cases. llvm-svn: 300734
* StructurizeCFG: Directly invert cmp instructionsMatt Arsenault2017-04-198-112/+184
| | | | | | | | | | | | | | | | The most common case for a branch condition is a single use compare. Directly invert the branch predicate rather than adding a lot of xor i1 true which the DAG will have to fold later. This produces nicer to read structurizer output. This produces some random changes in codegen due to the DAG swapping branch conditions itself, and then does a poor job of dealing with those inverts. llvm-svn: 300732
* [GVN] Don't coerce non-integral pointers to integers or vice versaSanjoy Das2017-04-193-0/+83
| | | | | | | | | | | | | | | | | Summary: See http://llvm.org/docs/LangRef.html#non-integral-pointer-type The NewGVN test does not fail without these changes (perhaps it does try to coerce pointers <-> integers to begin with?), but I added the test case anyway. Reviewers: dberlin Subscribers: mcrosier, llvm-commits, Prazek Differential Revision: https://reviews.llvm.org/D32208 llvm-svn: 300730
* Update comment to match r300252.Richard Smith2017-04-191-1/+1
| | | | llvm-svn: 300728
* ARM: TLS calling convention doesn't preserve r9 or r12 on Darwin.Tim Northover2017-04-192-3/+27
| | | | llvm-svn: 300726
* [DAG] add splat vector support for 'and' in SimplifyDemandedBitsSanjay Patel2017-04-195-31/+9
| | | | | | | | | | | | | | | | | | | | | The patch itself is simple: stop discriminating against vectors in visitAnd() and again in SimplifyDemandedBits(). Some notes for reference: 1. We're not consistent about calls to SimplifyDemandedBits in the various visitXXX functions. Sometimes, we check if the RHS is a constant first. Other times (like here), we just dive in. 2. I'd like to break the vector shackles in steps for the sake of risk minimization, but we could make similar simultaneous changes in other places if we think that would be better. 3. I don't know what the intent of the changed tests in this patch was supposed to be, but since they wiggled in a positive way, I'm just going with that. :) 4. In the rotate tests, note that we can see through non-splat constants. This is a result of D24253. 5. My motivation for being here now is to make D31944 look better, so this is step 1 of N towards improving the vector codegen in that patch without writing any actual new code. Differential Revision: https://reviews.llvm.org/D32230 llvm-svn: 300725
* IR: Remove some comments that are documenting the obvious. NFC.Peter Collingbourne2017-04-191-4/+0
| | | | llvm-svn: 300724
* [MathExtras] Fix undefined behavior (shift by bit width)Benjamin Kramer2017-04-192-1/+6
| | | | | | While there add some unit tests for uint64_t. Found by ubsan. llvm-svn: 300721
* AMDGPU: Don't align callable functions to 256Matt Arsenault2017-04-193-1/+34
| | | | llvm-svn: 300720
* AMDGPU: Change DivergenceAnalysis for function argumentsMatt Arsenault2017-04-193-598/+780
| | | | | | Stop assuming all functions are kernels. llvm-svn: 300719
* Prefer addAttr(Attribute::AttrKind) over the AttributeList overloadReid Kleckner2017-04-196-69/+45
| | | | | | | | This should simplify the call sites, which typically want to tweak one attribute at a time. It should also avoid creating ephemeral AttributeLists that live forever. llvm-svn: 300718
* [InstCombine] Reduce visitLoadInst() code duplication. NFCI.Davide Italiano2017-04-191-20/+18
| | | | llvm-svn: 300717
* [APInt] Move the 'return *this' from the slow cases of assignment operators ↵Craig Topper2017-04-192-27/+25
| | | | | | | | inline. We should let the compiler see that the fast/slow cases both return *this. I don't think we chain assignments together very often so this shouldn't matter much. llvm-svn: 300715
* [InstSimplify] fold identity shuffles (recursing if needed)Sanjay Patel2017-04-192-27/+117
| | | | | | | | | | | | | | | | | This patch simplifies the examples from D31509 and D31927 (PR30630) and catches the basic identity shuffle tests that Zvi recently added. I'm not sure if we have something like this in DAGCombiner, but we should? It's worth noting that "MaxRecurse / RecursionLimit" is only 3 on entry at the moment. We might want to bump that up if there are longer shuffle chains like this in the wild. For now, we're ignoring shuffles that have undef mask elements because it's not clear how those should be handled. Differential Revision: https://reviews.llvm.org/D31960 llvm-svn: 300714
* use 'auto' with 'dyn_cast' and fix formatting; NFCSanjay Patel2017-04-191-8/+7
| | | | llvm-svn: 300713
* Add an #include for <climits> for CHAR_BIT.Zachary Turner2017-04-191-0/+1
| | | | llvm-svn: 300711
* [Support] Add some helpers to generate bitmasks.Zachary Turner2017-04-192-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | Frequently you you want a bitmask consisting of a specified number of 1s, either at the beginning or end of a word. The naive way to do this is to write template<typename T> T leadingBitMask(unsigned N) { return (T(1) << N) - 1; } but using this function you cannot produce a word with every bit set to 1 (i.e. leadingBitMask<uint8_t>(8)) because left shift is undefined when N is greater than or equal to the number of bits in the word. This patch provides an efficient, branch-free implementation that works for all values of N in [0, CHAR_BIT*sizeof(T)] Differential Revision: https://reviews.llvm.org/D32212 llvm-svn: 300710
* Revert r300697 which causes buildbot failure.Dehao Chen2017-04-194-58/+52
| | | | llvm-svn: 300708
* [Hexagon] Generate proper offset in opt-addr-modeKrzysztof Parzyszek2017-04-193-11/+33
| | | | | | | | | Also, make a few changes to allow using the pass in .mir testcases. Among other things, change the abbreviation from opt-amode to amode-opt, because otherwise lit would expand the "opt" part to the full path to the opt binary. llvm-svn: 300707
* [Hexagon] Remove RDefMap, use Liveness:getNearestAliasedRef insteadKrzysztof Parzyszek2017-04-191-48/+5
| | | | llvm-svn: 300706
* [RDF] Switch NodeList to SmallVector from std::vectorKrzysztof Parzyszek2017-04-191-1/+2
| | | | | | | The list has a single element 75+% of the time, reservation of 4 elements is sufficient in 95% of cases. llvm-svn: 300705
* [RDF] Use faster version of findBlockKrzysztof Parzyszek2017-04-191-1/+1
| | | | llvm-svn: 300704
* [RDF] Cache register units for reg masks instead of recalculating themKrzysztof Parzyszek2017-04-192-31/+29
| | | | llvm-svn: 300702
* [Hexagon] Cache reached blocks in bit tracker instead of scanning listKrzysztof Parzyszek2017-04-192-10/+10
| | | | llvm-svn: 300701
* [PowerPC] add test and auto-generate checks; NFCSanjay Patel2017-04-191-19/+33
| | | | llvm-svn: 300700
* [ARM] add test and auto-generate checks; NFCSanjay Patel2017-04-191-122/+440
| | | | llvm-svn: 300698
* Using address range map to speedup finding inline stack for address.Dehao Chen2017-04-194-52/+58
| | | | | | | | | | | | | | | | | | | | Summary: In the current implementation, to find inline stack for an address incurs expensive linear search in 2 places: * linear search for the top-level DIE * recursive linear traverse the DIE tree to find the path to the leaf DIE In this patch, a map is built from address to its corresponding leaf DIE. The inline stack is built by traversing from the leaf DIE up to the root DIE. This speeds up batch symbolization by ~10X without noticible memory overhead. Reviewers: dblaikie Reviewed By: dblaikie Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D32177 llvm-svn: 300697
* [InstSimplify] Deduce correct type for vector GEP.Davide Italiano2017-04-192-1/+27
| | | | | | | | | | InstSimplify returned the wrong type when simplifying a vector GEP and we ended up crashing when trying to replace all uses with the new value. Fixes PR32697. Differential Revision: https://reviews.llvm.org/D32180 llvm-svn: 300693
* [DAG] Loop over remaining candidates on successful merge of stores ofNirav Dave2017-04-191-30/+43
| | | | | | extracted vectors types. NFCI. llvm-svn: 300688
* [AVR] Remove the 'multibyte' asm testDylan McKay2017-04-191-135/+0
| | | | | | It tests registers which are not actually used on AVR. llvm-svn: 300684
* Regenerate test. NFCI.Simon Pilgrim2017-04-191-8/+9
| | | | llvm-svn: 300683
* [AVR] Fix the test suiteDylan McKay2017-04-194-35/+40
| | | | | | | | | | | | A bunch of tests failed because memory operations have been reordered. I am unsure which commit changed this behaviour as the AVR build was failing at that point with an unrelated error. This commit just reoders some of the CHECK lines in some tests to suit current llc output. llvm-svn: 300682
* [GlobalIsel][X86] support G_TRUNC selection.Igor Breger2017-04-196-0/+361
| | | | | | | | | | | | | | | | Summary: [GlobalIsel][X86] support G_TRUNC selection. Add regbank-select and legalizer tests. Currently legalization of trunc i64 on 32bit platform not supported. Reviewers: ab, zvi, rovka Reviewed By: zvi Subscribers: dberris, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D32115 llvm-svn: 300678
* [X86] Add D32039/PR31357 tests to show current BSWAP codegenSimon Pilgrim2017-04-192-0/+255
| | | | llvm-svn: 300672
* [X86][SSE] Add scheduling latency/throughput tests for (most) SSE2 instructionsSimon Pilgrim2017-04-191-0/+6039
| | | | llvm-svn: 300671
* Revert "ARMFrameLowering: Reserve emergency spill slot for large arguments"Renato Golin2017-04-192-135/+8
| | | | | | This reverts commit r300639, as it broke self-hosting on ARM. PR32709. llvm-svn: 300668
* [GlobalISel][X86] Split select tests. NFC.Igor Breger2017-04-197-444/+455
| | | | llvm-svn: 300666
* [ARM] GlobalISel: Add support for G_MULDiana Picus2017-04-197-2/+338
| | | | | | | | Support G_MUL, very similar to G_ADD and G_SUB. The only difference is in the instruction selector, where we have to select either MUL or MULv5 depending on the target. llvm-svn: 300665
* [GlobalISel] Support vector-of-pointers in LLTKristof Beyls2017-04-197-69/+213
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes PR32471. As comment 10 on that bug report highlights (https://bugs.llvm.org//show_bug.cgi?id=32471#c10), there are quite a few different defendable design tradeoffs that could be made, including not representing pointers at all in LLT. I decided to go for representing vector-of-pointer as a concept in LLT, while keeping the size of the LLT type 64 bits (this is an increase from 48 bits before). My rationale for keeping pointers explicit is that on some targets probably it's very handy to have the distinction between pointer and non-pointer (e.g. 68K has a different register bank for pointers IIRC). If we keep a scalar pointer, it probably is easiest to also have a vector-of-pointers to keep LLT relatively conceptually clean and orthogonal, while we don't have a very strong reason to break that orthogonality. Once we gain more experience on the use of LLT, we can of course reconsider this direction. Rejecting vector-of-pointer types in the IRTranslator is also an option to avoid the crash reported in PR32471, but that is only a very short-term solution; also needs quite a bit of code tweaks in places, and is probably fragile. Therefore I didn't consider this the best option. llvm-svn: 300664
* [GlobalISel] Remove non-determinism from IRTranslator.Kristof Beyls2017-04-191-12/+16
| | | | | | | | | | | This showed up in r300535/r300537, which were reverted in r300538 due to some of the introduced tests in there failing on some bots, due to the non-determinism fixed in this commit. Re-committing r300535/r300537 will add 2 tests for the change in this commit. llvm-svn: 300663
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