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* Internalize: Remove reference of @llvm.noinline, it was replaced with the ↵Benjamin Kramer2012-03-311-1/+0
| | | | | | noinline attribute a long time ago. llvm-svn: 153806
* These strings aren't 'const char *' but 'char *'.Bill Wendling2012-03-312-2/+2
| | | | llvm-svn: 153805
* Cleanup whitespace.Bill Wendling2012-03-311-17/+17
| | | | llvm-svn: 153804
* Free the codegen options when deleting LTO code generator object.Bill Wendling2012-03-311-26/+21
| | | | llvm-svn: 153803
* Cleanup whitespace and remove unneeded 'extern' keyword on function definitions.Bill Wendling2012-03-312-27/+27
| | | | llvm-svn: 153802
* Clean up the naming in this test. Someone pointed this out in review atChandler Carruth2012-03-311-3/+3
| | | | | | one point, and I forgot to go back and clean it up. Sorry about that. =/ llvm-svn: 153801
* FileCheck-ize this test, and generally tidy it up prior to changingChandler Carruth2012-03-311-21/+26
| | | | | | things around. llvm-svn: 153799
* I noticed in passing that the Metadata getIfExists method was creating a newDuncan Sands2012-03-312-4/+11
| | | | | | node and returning it if one didn't exist. llvm-svn: 153798
* Correctly vectorize powi.Hal Finkel2012-03-312-11/+77
| | | | | | | | The powi intrinsic requires special handling because it always takes a single integer power regardless of the result type. As a result, we can vectorize only if the powers are equal. Fixes PR12364. llvm-svn: 153797
* comment typoAndrew Trick2012-03-311-1/+1
| | | | llvm-svn: 153796
* Select static relocation model if it is jitting.Akira Hatanaka2012-03-311-1/+3
| | | | llvm-svn: 153795
* Introduce Register Units: Give each leaf register a number.Andrew Trick2012-03-312-0/+60
| | | | | | | | First small step toward modeling multi-register multi-pressure. In the future, register units can also be used to model liveness and aliasing. llvm-svn: 153794
* Add a 2 byte safety margin in offset computations.Jakob Stoklund Olesen2012-03-311-2/+5
| | | | | | | | | | | | ARMConstantIslandPass still has bugs where jump table compression can cause constant pool entries to go out of range. Add a safety margin of 2 bytes when placing constant islands, but use the real max displacement for verification. <rdar://problem/11156595> llvm-svn: 153789
* Add more debugging output to ARMConstantIslandPass.Jakob Stoklund Olesen2012-03-311-2/+16
| | | | llvm-svn: 153788
* * Set the scope attributes for the ASM symbol we added to be the value passedBill Wendling2012-03-301-14/+18
| | | | | | | into the function. * Reorder some header files. llvm-svn: 153783
* Rip out emission of the regIsInRegClass function for the asm printer.Benjamin Kramer2012-03-303-68/+4
| | | | | | It's slow, bloated and completely redundant with MCRegisterClass::contains. llvm-svn: 153782
* ARM fix encoding fixup resolution for ldrd and friends.Jim Grosbach2012-03-301-0/+2
| | | | | | | | | The 8-bit payload is not contiguous in the opcode. Move the upper nibble over 4 bits into the correct place. rdar://11158641 llvm-svn: 153780
* Use SequenceToOffsetTable in emitRegisterNameString.Jakob Stoklund Olesen2012-03-302-8/+28
| | | | | | This allows suffix sharing in register names. (AX is a suffix of EAX). llvm-svn: 153777
* Reapply 153764 and 153761 with a fix.Jakob Stoklund Olesen2012-03-303-115/+87
| | | | | | | | | Use an explicit comparator instead of the default. The sets are sorted, but not using the default comparator. Hopefully, this will unbreak the Linux builders. llvm-svn: 153772
* Revert 153764 and 153761. They broke a --enable-optimized --enable-assertionsRafael Espindola2012-03-303-86/+115
| | | | | | --enable-expensive-checks build. llvm-svn: 153771
* ARM assembler should prefer non-aliases encoding of cmp.Jim Grosbach2012-03-302-6/+11
| | | | | | | | When an immediate is both a value [t2_]so_imm and a [t2_]so_imm_neg, we want to use the non-negated form to make sure we prefer the normal encoding, not the aliased encoding via the negation of, e.g., 'cmp.w'. llvm-svn: 153770
* ARM encoding for VSWP got the second operand incorrect.Jim Grosbach2012-03-302-4/+11
| | | | | | | | | Make the non-tied register operand names line up with what the base class encoding handler expects. rdar://11157236 llvm-svn: 153766
* ARM can only use narrow encoding for low regs.Jim Grosbach2012-03-301-0/+1
| | | | llvm-svn: 153765
* Compress SimpleValueType lists by sharing.Jakob Stoklund Olesen2012-03-302-22/+17
| | | | | | Many register classes have the same value types. Share the table space. llvm-svn: 153764
* Compress register lists by sharing suffixes.Jakob Stoklund Olesen2012-03-302-93/+69
| | | | | | | | TableGen emits lists of sub-registers, super-registers, and overlaps. Put them all in a single table and use a SequenceToOffsetTable to share suffixes. llvm-svn: 153761
* Add a SequenceToOffsetTable to TableGen.Jakob Stoklund Olesen2012-03-301-0/+123
| | | | | | | | This is similar to the StringToOffsetTable we use to produce string tables, but it can be used for other sequences than strings, and it eliminates entries for suffixes. llvm-svn: 153760
* ARM integrated assembler should encoding choice for add/sub imm.Jim Grosbach2012-03-302-0/+33
| | | | | | | | | For 'adds r2, r2, #56' outside of an IT block, the 16-bit encoding T2 can be used for this syntax. Prefer the narrow encoding when possible. rdar://11156277 llvm-svn: 153759
* Handle unreachable code in the dominates functions. This changes users whenRafael Espindola2012-03-306-11/+239
| | | | | | | needed for correctness, but still doesn't clean up code that now unnecessary checks for reachability. llvm-svn: 153755
* Re-factored RuntimeDyLd:Danil Malyshev2012-03-309-1073/+753
| | | | | | | | | | | | | | | 1. The main works will made in the RuntimeDyLdImpl with uses the ObjectFile class. RuntimeDyLdMachO and RuntimeDyLdELF now only parses relocations and resolve it. This is allows to make improvements of the RuntimeDyLd more easily. In addition the support for COFF can be easily added. 2. Added ARM relocations to RuntimeDyLdELF. 3. Added support for stub functions for the ARM, allowing to do a long branch. 4. Added support for external functions that are not loaded from the object files, but can be loaded from external libraries. Now MCJIT can correctly execute the code containing the printf, putc, and etc. 5. The sections emitted instead functions, thanks Jim Grosbach. MemoryManager.startFunctionBody() and MemoryManager.endFunctionBody() have been removed. 6. MCJITMemoryManager.allocateDataSection() and MCJITMemoryManager. allocateCodeSection() used JMM->allocateSpace() instead of JMM->allocateCodeSection() and JMM->allocateDataSection(), because I got an error: "Cannot allocate an allocated block!" with object file contains more than one code or data sections. llvm-svn: 153754
* ARM assembly parsing needs to be paranoid about negative immediates.Jim Grosbach2012-03-302-4/+7
| | | | | | | | Make sure to treat immediates as unsigned when doing relative comparisons. rdar://11153621 llvm-svn: 153753
* Add computeMaskedBitsLoad back, as it was the change to instsimplify thatRafael Espindola2012-03-301-0/+26
| | | | | | caused the slowdown last time. llvm-svn: 153747
* Add a note about a missed cmov -> sbb opportunity.Benjamin Kramer2012-03-301-0/+18
| | | | llvm-svn: 153741
* Cleanup whitespace. Doxygenize comments. And indent to llvm coding standards.Bill Wendling2012-03-301-214/+119
| | | | llvm-svn: 153740
* Ensure conditional BL instructions for ARM are given the fixup ↵James Molloy2012-03-308-12/+61
| | | | | | | | fixup_arm_condbranch. Patch by Tim Northover! llvm-svn: 153737
* ARM target should allow codegenprep to duplicate ret instructions to enable ↵Evan Cheng2012-03-302-1/+43
| | | | | | tailcall opt. rdar://11140249 llvm-svn: 153717
* Testcase for r153710.Bill Wendling2012-03-301-0/+35
| | | | llvm-svn: 153711
* Add testcase for r153705Bill Wendling2012-03-301-0/+59
| | | | llvm-svn: 153706
* If we have a VLA that has a "use" in a metadata node that's then usedBill Wendling2012-03-301-1/+12
| | | | | | | | | | | | | | | | here but it has no other uses, then we have a problem. E.g., int foo (const int *x) { char a[*x]; return 0; } If we assign 'a' a vreg and fast isel later on has to use the selection DAG isel, it will want to copy the value to the vreg. However, there are no uses, which goes counter to what selection DAG isel expects. <rdar://problem/11134152> llvm-svn: 153705
* Change the constant in this testcase so that it results in a constant poolLang Hames2012-03-291-3/+3
| | | | | | load. llvm-svn: 153704
* Revert r153694. It was causing failures in the buildbots.Bill Wendling2012-03-2957-1828/+1073
| | | | llvm-svn: 153701
* Invalidate liveness in ARMConstantIslandPass.Jakob Stoklund Olesen2012-03-291-0/+4
| | | | | | | | | | This pass splits basic blocks to insert constant islands, and it doesn't recompute the live-in lists. No later passes depend on accurate liveness information. This fixes PR12410 where the machine code verifier was complaining. llvm-svn: 153700
* Prefer even-odd D-register pairs.Jakob Stoklund Olesen2012-03-291-1/+2
| | | | | | | | | | | We are sometimes allocatinog from the DPair register class which contains odd-even pairs in addition to the Q registers. Place the Q registers first in the DPair allocation order as they can be copied with a single instruction. The odd-even pairs should only be allocated as a last resort. llvm-svn: 153699
* Filecheck-ize this test so that it actually tests something reasonable.Chandler Carruth2012-03-291-2/+13
| | | | llvm-svn: 153697
* Try using vmov.i32 to materialize FP32 constants that can't be materialized byLang Hames2012-03-291-23/+54
| | | | | | vmov.f32. llvm-svn: 153696
* Re-factored RuntimeDyld.Danil Malyshev2012-03-2957-1073/+1828
| | | | | | Added ExecutionEngine/MCJIT tests. llvm-svn: 153694
* Lowercase the tag name to match the rest of dwarf.Eric Christopher2012-03-294-5/+5
| | | | llvm-svn: 153691
* ARM assembly 'cmp lr, #0' should not encode using 'cmn'.Jim Grosbach2012-03-294-4/+10
| | | | | | | | | The CMP->CMN alias was matching for an immediate of zero when it should only match for negative values. rdar://11129224 llvm-svn: 153689
* The shuffle scheduler is only available in asserts build - make misched-new.llLang Hames2012-03-291-0/+1
| | | | | | testcase require asserts. llvm-svn: 153687
* Handle register copies for the new ARM register classes.Jakob Stoklund Olesen2012-03-291-19/+41
| | | | | | | | | | | | | ARM recently gained DPair, DTriple, and DQuad register classes. Update copyPhysReg() to handle copies in these register classes. No test case, it is difficult to make the register allocator emit the odd copies reliably. The missing DPair copy caused a failure on partialsums in the nightly test suite. <rdar://problem/11147997> llvm-svn: 153686
* Drop O4 from the llc manpage, it was removed in r70445.Benjamin Kramer2012-03-291-1/+1
| | | | llvm-svn: 153684
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