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* [X86] Fix the AllRegs AVX calling convention.Quentin Colombet2016-05-092-2/+2
| | | | | | | | | | We used to list registers that were not in the AVX space. In other words, we were pushing registers that the ISA cannot encode (YMM16-YMM31). This is part of llvm.org/PR27481. llvm-svn: 268983
* [Inliner] don't assume that a Constant alloca size is a ConstantInt (PR27277)Sanjay Patel2016-05-092-4/+34
| | | | | | Differential Revision: http://reviews.llvm.org/D20077 llvm-svn: 268980
* Fix buildbot failure from r268968.Rong Xu2016-05-091-1/+1
| | | | llvm-svn: 268979
* Typo. NFC.Chad Rosier2016-05-091-1/+1
| | | | llvm-svn: 268975
* Cleanup followup of r268710 - [PM] port IR based PGO prof-gen pass to new ↵Xinliang David Li2016-05-092-28/+25
| | | | | | pass manager llvm-svn: 268974
* [X86] Strengthen the setting of inline asm constraints for fp regclasses.Quentin Colombet2016-05-091-5/+22
| | | | | | | | | | | | | This is similar to r268953, but for floating point and vector register classes. Explanations: The setting of the inline asm constraints was implicitly relying on the order of the register classes in the file generated by tablegen. Since, we do not have any control on that order, make sure we do not depend on it anymore. llvm-svn: 268973
* [X86][SSE] Improve cost model for i64 vector comparisons on pre-SSE42 targetsSimon Pilgrim2016-05-092-11/+19
| | | | | | | | | | | | As discussed on PR24888, until SSE42 we don't have access to PCMPGTQ for v2i64 comparisons, but the cost models don't reflect this, resulting in over-optimistic vectorizaton. This patch adds SSE2 'base level' costs that match what a typical target is capable of and only reduces the v2i64 costs at SSE42. Technically SSE41 provides a PCMPEQQ v2i64 equality test, but as getCmpSelInstrCost doesn't give us a way to discriminate between comparison test types we can't easily make use of this, otherwise we could split the cost of integer equality and greater-than tests to give better costings of each. Differential Revision: http://reviews.llvm.org/D20057 llvm-svn: 268972
* [PGO] Fix __llvm_profile_raw_version linkage in MACHORong Xu2016-05-092-1/+10
| | | | | | | | | | | | | | | | | | | IR instrumentation generates a COMDAT symbol __llvm_profile_raw_version to overwrite the same symbol in profile run-time to distinguish IR profiles from Clang generated profiles. In MACHO, LinkOnceODR linkage is used due to the lack of COMDAT support. But LinkOnceODR linkage might have .weak_def_can_be_hidden assembly directive, while the weak variable in run-time has a .weak_definition directive. Linker will not merge these two symbols even they have the same name. The end result is IR profiles are not properly flagged in MACHO. This patch changes the linkage for __llvm_profile_raw_version in each module to LinkOnceAny so that it has same .weak_definition directive as in the run-time. Differential Revision: http://reviews.llvm.org/D20078 llvm-svn: 268969
* [libFuzzer] add a test for libFuzzer+ubsan, extend the docs on using ↵Kostya Serebryany2016-05-095-5/+64
| | | | | | libFuzzer+ubsan llvm-svn: 268968
* [MSan] [AArch64] Fix vararg helper for >1 or non-int fixed arguments.Marcin Koscielnicki2016-05-092-9/+20
| | | | | | | | | | | | | | | | | | This fixes http://llvm.org/PR27646 on AArch64. There are three issues here: - The GR save area is 7 words in size, instead of 8. This is not enough if none of the fixed arguments is passed in GRs (they're all floats or aggregates). - The first argument is ignored (which counteracts the above if it's passed in GR). - Like x86_64, fixed arguments landing in the overflow area are wrongly counted towards the overflow offset. Differential Revision: http://reviews.llvm.org/D20023 llvm-svn: 268967
* Separate the Verifier into an analysis and a transformation pass andAdrian Prantl2016-05-096-9/+110
| | | | | | | | | | | | | | | | | | | | | | | | allow the transformation to strip invalid debug info. This patch separates the Verifier into an analysis and a transformation pass, with the transformation pass optionally stripping malformed debug info. The problem I'm trying to solve with this sequence of patches is that historically we've done a really bad job at verifying debug info. We want to be able to make the verifier stricter without having to worry about breaking bitcode compatibility with existing producers. For example, we don't necessarily want IR produced by an older version of clang to be rejected by an LTO link just because of malformed debug info, and rather provide an option to strip it. Note that merely outdated (but well-formed) debug info would continue to be auto-upgraded in this scenario. http://reviews.llvm.org/D19988 rdar://problem/25818489 This reapplies r268937 without modifications. llvm-svn: 268966
* Allow the LTO code generator to strip invalid debug info from the input.Adrian Prantl2016-05-095-7/+58
| | | | | | | | | | | | | | | | | | | | | This patch introduces a new option -lto-strip-invalid-debug-info, which drops malformed debug info from the input. The problem I'm trying to solve with this sequence of patches is that historically we've done a really bad job at verifying debug info. We want to be able to make the verifier stricter without having to worry about breaking bitcode compatibility with existing producers. For example, we don't necessarily want IR produced by an older version of clang to be rejected by an LTO link just because of malformed debug info, and rather provide an option to strip it. Note that merely outdated (but well-formed) debug info would continue to be auto-upgraded in this scenario. rdar://problem/25818489 http://reviews.llvm.org/D19987 This reapplies 268936 with a test case fix for Linux (-exported-symbol foo) llvm-svn: 268965
* [X86] Drop the 64-bit alignment for LOW32_ADDR_ACCESS register class.Quentin Colombet2016-05-091-2/+3
| | | | | | | The only 64-bit register in that register class is RIP and it will not get spilled in the current ABIs. llvm-svn: 268963
* [libFuzzer] reshuffle docs moreKostya Serebryany2016-05-091-1/+1
| | | | llvm-svn: 268961
* [InstCombine] Fold icmp eq/ne (udiv i32 A, B), 0 -> icmp ugt/ule B, A.Chad Rosier2016-05-093-0/+61
| | | | | | Differential Revision: http://reviews.llvm.org/D20036 llvm-svn: 268960
* [libFuzzer] reshuffle docs Kostya Serebryany2016-05-091-35/+37
| | | | llvm-svn: 268959
* [libFuzzer] better document the -merge=1 flag, part 2 Kostya Serebryany2016-05-091-0/+7
| | | | llvm-svn: 268958
* [libFuzzer] better document the -merge=1 flagKostya Serebryany2016-05-092-5/+14
| | | | llvm-svn: 268957
* Reapply [X86] Add a new LOW32_ADDR_ACCESS_RBP register class.Quentin Colombet2016-05-094-4/+20
| | | | | | | | | | | | | | | This reapplies commit r268796, with a fix for the setting of the inline asm constraints. I.e., "mark" LOW32_ADDR_ACCESS_RBP as a GR variant, so that the regular processing of the GR operands (setting of the subregisters) happens. Original commit log: [X86] Add a new LOW32_ADDR_ACCESS_RBP register class. ABIs like NaCl uses 32-bit addresses but have 64-bit frame. The new register class reflects those constraints when choosing a register class for a address access. llvm-svn: 268955
* [X86] Update a regexp in a test case to resist register allocationQuentin Colombet2016-05-091-5/+12
| | | | | | changes. llvm-svn: 268954
* [X86] Strengthen the setting of inline asm constraints.Quentin Colombet2016-05-091-2/+38
| | | | | | | | | The setting of the inline asm constraints was implicitly relying on the order of the register classes in the file generated by tablegen. Since, we do not have any control on that order, make sure we do not depend on it anymore. llvm-svn: 268953
* [Power9] Add support for -mcpu=pwr9 in the back endNemanja Ivanovic2016-05-0910-6/+28
| | | | | | | | | This patch corresponds to review: http://reviews.llvm.org/D19683 Simply adds the bits for being able to specify -mcpu=pwr9 to the back end. llvm-svn: 268950
* clean up; NFCSanjay Patel2016-05-091-9/+11
| | | | llvm-svn: 268949
* Fix build error with ambiguity of size_t.Zachary Turner2016-05-091-1/+1
| | | | llvm-svn: 268948
* [Hexagon] Treat all conditional branches as predicted (not-taken by default)Krzysztof Parzyszek2016-05-095-11/+69
| | | | llvm-svn: 268946
* [AMDGPU] Clean up debugger testsKonstantin Zhuravlyov2016-05-093-59/+81
| | | | llvm-svn: 268944
* Unbreak the non-windows build.Benjamin Kramer2016-05-091-5/+5
| | | | llvm-svn: 268943
* [pdb] Parse the module info stream for each module.Zachary Turner2016-05-097-27/+311
| | | | | | | Differential Revision: http://reviews.llvm.org/D20026 Reviewed By: rnk llvm-svn: 268942
* Make TypeIterator generic so it can iterate symbols too.Zachary Turner2016-05-098-100/+138
| | | | | | | Reviewed By: amccarth Differential Revision: http://reviews.llvm.org/D20038 llvm-svn: 268941
* Revert "Allow the LTO code generator to strip invalid debug info from the ↵Adrian Prantl2016-05-095-57/+7
| | | | | | | | input." This reverts commit 268936 while investigating buildbot breakage. llvm-svn: 268940
* Revert "Separate the Verifier into an analysis and a transformation pass and"Adrian Prantl2016-05-096-110/+9
| | | | | | This reverts commit 268937 while investigating build bot breakage. llvm-svn: 268939
* [mips] Fix a partially initialized member variable that was introduced in ↵Daniel Sanders2016-05-091-0/+2
| | | | | | r268896. llvm-svn: 268938
* Separate the Verifier into an analysis and a transformation pass andAdrian Prantl2016-05-096-9/+110
| | | | | | | | | | | | | | | | | | | | | | allow the transformation to strip invalid debug info. This patch separates the Verifier into an analysis and a transformation pass, with the transformation pass optionally stripping malformed debug info. The problem I'm trying to solve with this sequence of patches is that historically we've done a really bad job at verifying debug info. We want to be able to make the verifier stricter without having to worry about breaking bitcode compatibility with existing producers. For example, we don't necessarily want IR produced by an older version of clang to be rejected by an LTO link just because of malformed debug info, and rather provide an option to strip it. Note that merely outdated (but well-formed) debug info would continue to be auto-upgraded in this scenario. http://reviews.llvm.org/D19988 rdar://problem/25818489 llvm-svn: 268937
* Allow the LTO code generator to strip invalid debug info from the input.Adrian Prantl2016-05-095-7/+57
| | | | | | | | | | | | | | | | | | | This patch introduces a new option -lto-strip-invalid-debug-info, which drops malformed debug info from the input. The problem I'm trying to solve with this sequence of patches is that historically we've done a really bad job at verifying debug info. We want to be able to make the verifier stricter without having to worry about breaking bitcode compatibility with existing producers. For example, we don't necessarily want IR produced by an older version of clang to be rejected by an LTO link just because of malformed debug info, and rather provide an option to strip it. Note that merely outdated (but well-formed) debug info would continue to be auto-upgraded in this scenario. rdar://problem/25818489 http://reviews.llvm.org/D19987 llvm-svn: 268936
* [CGP] avoid crashing from weightlessnessSanjay Patel2016-05-092-3/+19
| | | | | | | It's possible that we have branch weights with 0 values. In that case, don't try to create an impossible BranchProbability. llvm-svn: 268935
* DivergenceAnalysis: Fix crash with no return blocksMatt Arsenault2016-05-092-1/+37
| | | | | | The post dominator tree does not have a root node in this case. llvm-svn: 268933
* [TargetLowering] make helper function for SetCC + and optimizations (NFC)Sanjay Patel2016-05-092-52/+45
| | | | | | | | | | After looking at D19087 again, it occurred to me that we can do better. If we consolidate the valueHasExactlyOneBitSet() transforms, we won't incur extra overhead from calling it a 2nd time, and we can shrink SimplifySetCC() a bit. No functional change intended. Differential Revision: http://reviews.llvm.org/D20050 llvm-svn: 268932
* Fixed unused but set variable warningSimon Pilgrim2016-05-091-3/+0
| | | | llvm-svn: 268931
* AMDGPU: Fold shift into cvt_f32_ubyteNMatt Arsenault2016-05-093-3/+137
| | | | llvm-svn: 268930
* fix spelling; NFCSanjay Patel2016-05-091-2/+2
| | | | llvm-svn: 268929
* [mips] Try to fix 'truncation from FindBestPredicateResult to bool' reported ↵Daniel Sanders2016-05-091-3/+3
| | | | | | by MSVC llvm-svn: 268928
* [mips][ias] Attempt to fix 'not all control paths return a value' reported ↵Daniel Sanders2016-05-091-0/+2
| | | | | | by MSVC. llvm-svn: 268927
* [dsymutil] Prevent use-after-freeFrederic Riss2016-05-094-2/+15
| | | | | | | | | | | | The BinaryHolder would query the archive member MemoryBuffer name to check if the current open archive also contains the next requested objectfile. This comparison was using a StringRef to a temporary buffer. It only happened with fat archives. This commit adds long-lived storage along with the MemoryBuffers for the fat archive filename. The added test would fail during an ASAN build without the fix. llvm-svn: 268924
* Optimize a printf with a double procent to putchar.Joerg Sonnenberger2016-05-092-2/+14
| | | | llvm-svn: 268922
* [VectorUtils] Query number of sign bits to allow more truncationsJames Molloy2016-05-092-4/+50
| | | | | | When deciding if a vector calculation can be done in a smaller bitwidth, use sign bit information from ValueTracking to add more information and allow more truncations. llvm-svn: 268921
* [mips][micromips] Make getPointerRegClass() result depend on the instruction.Daniel Sanders2016-05-096-14/+58
| | | | | | | | | | | | | | | | | | | Summary: Previously, it returned the GPR16MMRegClass for all instructions which was incorrect for instructions like lwsp/lwgp and unnecesarily restricted the permitted registers for instructions like lw32. This fixes quite a few of the -verify-machineinstrs errors reported in PR27458. I've only added -verify-machineinstrs to one test in this change since I understand there is a plan to enable the verifier by default. Reviewers: hvarga, zbuljan, zoran.jovanovic, sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D19873 llvm-svn: 268918
* Fix bug where temporary file would be left behind every time an archive was ↵Rafael Espindola2016-05-093-9/+29
| | | | | | | | | | | | | | | | | | | updated. When updating an existing archive, llvm-ar opens the old archive into a `MemoryBuffer`, does its thing, and writes the results to a temporary file. That file is then renamed to the original archive filename, thus replacing it with the updated contents. However, on Windows at least, what would happen is that the `MemoryBuffer` for the old archive would actually be an mmap'ed view of the file, so when it came time to do the rename via Win32's `ReplaceFile`, it would succeed but would be unable to fully replace the file since there would still be a handle open on it; instead, the old version got renamed to a random temporary name and left behind. Patch by Cameron! llvm-svn: 268916
* [X86][SSE] Added TODO comment to add support for AVX512 mask registers to ↵Simon Pilgrim2016-05-092-0/+2
| | | | | | | | shuffle comments This came up in discussion on D19198 llvm-svn: 268915
* [mips] Fix use after free and an unnecessary copy introduced in r268896.Daniel Sanders2016-05-091-3/+4
| | | | llvm-svn: 268913
* [PowerPC] fix register alignment for long double typeStrahinja Petrovic2016-05-097-4/+122
| | | | | | | | | This patch fixes register alignment for long double type in soft float mode. Before this patch alignment was 8 and this patch changes it to 4. Differential Revision: http://reviews.llvm.org/D18034 llvm-svn: 268909
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