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* [Sparc][LEON] Add UMAC and SMAC instruction support for Sparc LEON subtargetsChris Dewhurst2016-05-097-5/+79
| | | | | | | | | | | | This change adds SMAC (signed multiply-accumulate) and UMAC (unsigned multiply-accumulate) for LEON subtargets of the Sparc processor. The new files LeonFeatures.td and leon-instructions.ll will both be expanded in future, so I want to leave them separate as small files for this review, to be expanded in future check-ins. Note: The functions are provided only for inline-assembly provision. No DAG selection is provided. Differential Revision: http://reviews.llvm.org/D19911 llvm-svn: 268908
* [AArch64] Implement lowering of the X constraint on AArch64Silviu Baranga2016-05-094-0/+193
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This implements the lowering of the X constraint on AArch64. The default behaviour of the X constraint lowering is to restrict it to "f". This is a problem because the "f" constraint is not implemented on AArch64 and would be too restrictive anyway. Therefore, the AArch64 hook will lower this to "w" (if the operand is a floating point or vector) or "r" otherwise. The implementation is similar with the one added for ARM (r267411). This is the AArch64 side of the fix for http://llvm.org/PR26493 Reviewers: rengolin Subscribers: aemerson, rengolin, llvm-commits, t.p.northover Differential Revision: http://reviews.llvm.org/D19967 llvm-svn: 268907
* [X86][AVX512] Added masked version of combine testsSimon Pilgrim2016-05-091-0/+112
| | | | llvm-svn: 268904
* Revert "[Mips] Fix use after free."Benjamin Kramer2016-05-091-1/+2
| | | | | | | | Fixes use after free but breaks tests. This reverts commit r268901. llvm-svn: 268902
* [Mips] Fix use after free.Benjamin Kramer2016-05-091-2/+1
| | | | llvm-svn: 268901
* [mips][ias] R_MIPS_(GOT|HI|LO|PC)16 and R_MIPS_GPREL32 do not need symbols.Daniel Sanders2016-05-094-54/+111
| | | | | | | | | | | | | | | | | Summary: In theory, care must be taken to ensure that pairs of R_MIPS_(GOT|HI|LO)16 make the same decision on both relocs in the reloc pair but in practice this isn't as hard as it sounds and only limits the complexity of the predicate used. We handle all three with the same code to ensure their decisions always agree with each other. Reviewers: sdardis Subscribers: rafael, dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D19016 llvm-svn: 268900
* [mips][microMIPS] Implement LWP and SWP instructionsZlatko Buljan2016-05-0912-10/+123
| | | | | | Differential Revision: http://reviews.llvm.org/D10640 llvm-svn: 268896
* [dsymutil] Fix -arch option for thumb variants.Frederic Riss2016-05-094-1/+18
| | | | | | | | | | r267249 removed the dual ARM/Thumb interface from MachOObjectFile, simplifying llvm-dsymutil's code. This unfortunately also regressed llvm-dsymutil's ability to select thumb slices, because the simplified code was also dealing with the discrepency between the slice arch (eg. armv7m) and the triple arch name (eg. thumbv7m). llvm-svn: 268894
* [X86] Strengthen some type contraints for floating point round and extend.Craig Topper2016-05-091-14/+10
| | | | llvm-svn: 268892
* [AVX512] Fix up types for arguments of int_x86_avx512_mask_cvtsd2ss_round ↵Craig Topper2016-05-094-33/+33
| | | | | | and int_x86_avx512_mask_cvtss2sd_round. Only the argument being converted should be a different type. The other 2 argument should have the same type as the result. llvm-svn: 268891
* ThinLTOCodeGenerator: ignore 0 values for the cache settings.Mehdi Amini2016-05-092-9/+17
| | | | | From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 268890
* [AVX512] Add non-temporal store patterns for v16i32/v32i16/v64i8.Craig Topper2016-05-082-2/+23
| | | | llvm-svn: 268889
* Minor code cleanups. NFC.Junmo Park2016-05-081-3/+3
| | | | llvm-svn: 268888
* [AVX512] Add missing patterns for non-temporal stores of 128/256-bit ↵Craig Topper2016-05-082-0/+55
| | | | | | | | vXi8/vXi16/vXi32 when VLX is enabled. The equivalent AVX1/2 patterns are disabled by VLX. This caused regular stores to be emitted instead. llvm-svn: 268886
* [AVX512] Change predicates on some vXi16/vXi8 AVX store patterns so they ↵Craig Topper2016-05-081-16/+22
| | | | | | | | stay enabled unless VLX and BWI instructions are supported." Without this we could fail instruction selection if VLX was enabled, but BWI wasn't. llvm-svn: 268885
* [AVX512] Add VLX 128/256-bit SET0 operations that encode to 128/256-bit EVEX ↵Craig Topper2016-05-0814-82/+114
| | | | | | encoded VPXORD so all 32 registers can be used. llvm-svn: 268884
* [X86] Re-generate tests using update_llc_test_checks.py to prepare for a ↵Craig Topper2016-05-082-157/+180
| | | | | | future commit. NFC llvm-svn: 268883
* Remove Windows line endings in some tests to prepare for a future commit. NFCCraig Topper2016-05-082-251/+251
| | | | llvm-svn: 268882
* [Bitcode] Fix an unsigned integer overflow while parsing bitcode wrapper headerBruno Cardoso Lopes2016-05-081-1/+2
| | | | | | | | | | | | | Specially crafted bitcode wrapper headers can cause unsigned interger overflow and lead to crashes when wrapping around. Fix the offset check and avoid such scenarios. Writing a testcase for this would involve editing the binary to generate values that trigger the overflow, since this would never happen while generating the bitcode in regular compilation flows, so there's currently no feasible way add one. llvm-svn: 268881
* [X86] Remove extra patterns that check for BUILD_VECTOR of all 0s. These are ↵Craig Topper2016-05-082-24/+7
| | | | | | always canonicalized to v4i32/v8i32/v16i32 except for in SSE1 only when only v4f32 is supported. llvm-svn: 268880
* [CostModel][X86] Extended comparison instruction cost model tests to include ↵Simon Pilgrim2016-05-081-33/+113
| | | | | | SSE2/SSE3/SSSE3/SSE41/SSE42 targets llvm-svn: 268877
* [X86] Promote several single precision FP libcalls on WindowsDavid Majnemer2016-05-082-10/+14
| | | | | | | | | | | | A number of libcalls don't exist in any particular lib but are, instead, defined in math.h as inline functions (even in C mode!). Don't rely on their existence when lowering @llvm.{cos,sin,floor,..}.f32, promote them instead. N.B. We had logic to handle FREM but were missing out on a number of others. This change generalizes the FREM handling. llvm-svn: 268875
* [X86] Lower 256-bit vector all-zero constants to v8i32 even with AVX1 only. ↵Craig Topper2016-05-083-12/+4
| | | | | | Either way a 256-bit VXORPS will be used. llvm-svn: 268873
* [X86] Add patterns for 256-bit non-temporal stores when only AVX1 is ↵Craig Topper2016-05-082-6/+59
| | | | | | supported. While there, add a predicate to the SSE2 patterns to avoid an ordering dependency. llvm-svn: 268872
* [X86] No need to avoid selecting AVX_SET0 for 256-bit integer types when ↵Craig Topper2016-05-086-34/+11
| | | | | | only AVX1 is supported. AVX_SET0 just expands to 256-bit VXORPS which is legal in AVX1. llvm-svn: 268871
* [ARM] Fix Scavenger assert due to underestimated stack sizeWeiming Zhao2016-05-082-5/+217
| | | | | | | | | | | | | | | | (re-apply r268810 as it exposed an uninitialized variable in ARM MFI. Patch 268868 should fix that.) Summary: Currently, when checking if a stack is "BigStack" or not, it doesn't count into spills and arguments. Therefore, LLVM won't reserve spill slot for this actually "BigStack". This may cause scavenger failure. Reviewers: rengolin Subscribers: vitalybuka, aemerson, rengolin, tberghammer, danalbert, srhines, llvm-commits Differential Revision: http://reviews.llvm.org/D19896 llvm-svn: 268869
* Fix use-of-uninitialized-value of ARMMachineFunctionInfoWeiming Zhao2016-05-081-1/+1
| | | | | | | | | | | | Summary: Explicitly initialize ArgumentStackSize to prevent the msan failure. Reviewers: rengolin Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D20051 llvm-svn: 268868
* Fix unused variable warning.Simon Pilgrim2016-05-071-1/+0
| | | | llvm-svn: 268867
* [SelectionDAG] Added bitreverse(bitreverse(v)) --> vSimon Pilgrim2016-05-073-320/+38
| | | | | | Added bitreverse creation testing llvm-svn: 268865
* [X86] Fix InstAliases to not allow FARCALL32i/FARCALL16i/FARJMP32i/FARJMP16i ↵Craig Topper2016-05-071-8/+8
| | | | | | in 64-bit mode. llvm-svn: 268863
* [X86] Added BITREVERSE constant folding and identity testsSimon Pilgrim2016-05-071-1/+363
| | | | | | Identity tests are currently failing - this will be fixed soon llvm-svn: 268862
* [X86] Pulled out duplicate mask width calculation. NFCI.Simon Pilgrim2016-05-071-2/+3
| | | | llvm-svn: 268861
* [CostModel][X86] Split BSWAP/BITREVERSE cost tests from CTPOP/CTLZ/CTTZ 'bit ↵Simon Pilgrim2016-05-073-176/+188
| | | | | | count' cost tests llvm-svn: 268859
* [x86, BMI] add TLI hook for 'andn' and use it to simplify comparisonsSanjay Patel2016-05-075-11/+143
| | | | | | | | | | | | | | | | | | | | | For the sake of minimalism, this patch is x86 only, but I think that at least PPC, ARM, AArch64, and Sparc probably want to do this too. We might want to generalize the hook and pattern recognition for a target like PPC that has a full assortment of negated logic ops (orc, nand). Note that http://reviews.llvm.org/D18842 will cause this transform to trigger more often. For reference, this relates to: https://llvm.org/bugs/show_bug.cgi?id=27105 https://llvm.org/bugs/show_bug.cgi?id=27202 https://llvm.org/bugs/show_bug.cgi?id=27203 https://llvm.org/bugs/show_bug.cgi?id=27328 Differential Revision: http://reviews.llvm.org/D19087 llvm-svn: 268858
* ErrorInfoBase::message(): Don't use raw_string_ostream's buffer, Msg, before ↵NAKAMURA Takumi2016-05-071-1/+1
| | | | | | closing. Use raw_string_ostream::str() to flush the buffer. llvm-svn: 268856
* [PM] code refactoring -- preparation for new PM porting /NFCXinliang David Li2016-05-076-22/+37
| | | | llvm-svn: 268851
* Fix stripDebugInfo: was modifying "DebugLoc" attached to the intrinsic after ↵Mehdi Amini2016-05-071-0/+1
| | | | | | | | | deleting it. Fix MSAN build. From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 268849
* MipsELFObjectWriter.cpp: Activate debug printer just for +Asserts. ↵NAKAMURA Takumi2016-05-071-0/+2
| | | | | | [-Wunused-function] llvm-svn: 268848
* Refactor stripDebugInfo(Function) to handle intrinsicMehdi Amini2016-05-075-22/+82
| | | | | | | | | | | | | | This moves the code that handles stripping debug info intrinsic from StripDebugInfo(Module) to StripDebugInfo(Function). The latter is already walking every instructions so it makes sense to do it at the same time. This makes also stripDebugInfo(Function) as an API more useful: it is really dropping every debug info in the Function. Finally the existing code is trigerring an assertion when the Module is not fully materialized. From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 268847
* [Orc] Fix missing rename from r268845.Lang Hames2016-05-071-1/+1
| | | | llvm-svn: 268846
* [Orc] Rename OrcArchitectureSupport to OrcABISupport and add Win32 ABI support.Lang Hames2016-05-077-110/+233
| | | | | | | | This enables lazy JITing on Windows x86-64. Patch by David. Thanks David! llvm-svn: 268845
* Revert r268832 "Refactor stripDebugInfo(Function) to handle intrinsic"Vitaly Buka2016-05-074-80/+21
| | | | | | It breaks many bots llvm-svn: 268837
* [ValueTracking] Hoist some computation out of a loop; NFCSanjoy Das2016-05-071-20/+11
| | | | | | There is no need to match the comparison instruction repeatedly. llvm-svn: 268836
* Clean up comment; NFCSanjoy Das2016-05-071-1/+1
| | | | llvm-svn: 268835
* Delete trailing whitespace; NFCSanjoy Das2016-05-071-8/+8
| | | | llvm-svn: 268834
* Revert r268810 becase it brakes msan bot.Vitaly Buka2016-05-072-217/+5
| | | | | | | 16802==WARNING: MemorySanitizer: use-of-uninitialized-value lib/Target/ARM/ARMFrameLowering.cpp:1632 llvm-svn: 268833
* Refactor stripDebugInfo(Function) to handle intrinsicMehdi Amini2016-05-074-21/+80
| | | | | | | | | | | | | | This moves the code that handles stripping debug info intrinsic from StripDebugInfo(Module) to StripDebugInfo(Function). The latter is already walking every instructions so it makes sense to do it at the same time. This makes also stripDebugInfo(Function) as an API more useful: it is really dropping every debug info in the Function. Finally the existing code is trigerring an assertion when the Module is not fully materialized. From: Mehdi Amini <mehdi.amini@apple.com> llvm-svn: 268832
* [X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr.Ahmed Bougacha2016-05-0718-227/+503
| | | | | | | | | | | | | | | | | | | | | | | | | This re-applies r268760, reverted in r268794. Fixes http://llvm.org/PR27670 The original imp-defs assertion was way overzealous: forward all implicit operands, except imp-defs of the new super-reg def (r268787 for GR64, but also possible for GR16->GR32), or imp-uses of the new super-reg use. While there, mark the source use as Undef, and add an imp-use of the old source reg: that should cover any case of dead super-regs. At the stage the pass runs, flags are unlikely to matter anyway; still, let's be as correct as possible. Also add MIR tests for the various interesting cases. Original commit message: Codesize is less (16) or equal (8), and we avoid partial dependencies. Differential Revision: http://reviews.llvm.org/D19999 llvm-svn: 268831
* [X86] Register and initialize the FixupBW pass.Ahmed Bougacha2016-05-073-8/+19
| | | | | | That lets us use it in MIR tests. llvm-svn: 268830
* [libFuzzer] modify the docs for startup/initKostya Serebryany2016-05-061-3/+7
| | | | llvm-svn: 268824
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