summaryrefslogtreecommitdiffstats
path: root/llvm
Commit message (Collapse)AuthorAgeFilesLines
* Canonicalize min/max expressions correctly.James Molloy2015-05-154-7/+120
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces a canonical form for min/max idioms where one operand is extended or truncated. This often happens when the other operand is a constant. For example: %1 = icmp slt i32 %a, i32 0 %2 = sext i32 %a to i64 %3 = select i1 %1, i64 %2, i64 0 Would now be canonicalized into: %1 = icmp slt i32 %a, i32 0 %2 = select i1 %1, i32 %a, i32 0 %3 = sext i32 %2 to i64 This builds upon a patch posted by David Majenemer (https://www.marc.info/?l=llvm-commits&m=143008038714141&w=2). That pass passively stopped instcombine from ruining canonical patterns. This patch additionally actively makes instcombine canonicalize too. Canonicalization of expressions involving a change in type from int->fp or fp->int are not yet implemented. llvm-svn: 237453
* Allow min/max detection to see through casts.James Molloy2015-05-152-15/+72
| | | | | | | | | | | | | | This teaches the min/max idiom detector in ValueTracking to see through casts such as SExt/ZExt/Trunc. SCEV can already do this, so we're bringing non-SCEV analyses up to the same level. The returned LHS/RHS will not match the type of the original SelectInst any more, so a CastOp is returned too to inform the caller how to convert to the SelectInst's type. No in-tree users yet; this will be used by InstCombine in a followup. llvm-svn: 237452
* [llvm-readobj] Teach llvm-readobj to print PT_MIPS_ABIFLAGS program headerSimon Atanasyan2015-05-153-5/+18
| | | | llvm-svn: 237451
* NFC - Test case invokes llc on a file rather than redirected from a file.Nemanja Ivanovic2015-05-151-1/+1
| | | | | | | | This has caused some local failures. Updating the test case to be more like the majority of the similar test cases. Committing on behalf of Hubert Tong (hstong@ca.ibm.com). llvm-svn: 237449
* [xcore] Only support the 'm' inline assembly memory constraint. NFC.Daniel Sanders2015-05-151-6/+0
| | | | | | | | | | | | | | | | | | Summary: XCore doesn't seem to have any additional constraints. Therefore remove the target hook. No functional change intended. Reviewers: friedgold Reviewed By: friedgold Subscribers: friedgold, llvm-commits Differential Revision: http://reviews.llvm.org/D8921 llvm-svn: 237442
* [DependenceAnalysis] Fix for PR21585: collectUpperBound triggers assertsJames Molloy2015-05-152-2/+125
| | | | | | | | | | collectUpperBound hits an assertion when the back edge count is wider then the desired type. If that happens, truncate the backedge count. Patch by Philip Pfaffe! llvm-svn: 237439
* [mips] [IAS] Fix expansion of negative 32-bit immediates for LI/DLI.Toma Tabacu2015-05-153-5/+36
| | | | | | | | | | | | | | | | | | Summary: To maintain compatibility with GAS, we need to stop treating negative 32-bit immediates as 64-bit values when expanding LI/DLI. This currently happens because of sign extension. To do this we need to choose the 32-bit value expansion for values which use their upper 33 bits only for sign extension (i.e. no 0's, only 1's). Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8662 llvm-svn: 237428
* Add SDNodes for umin, umax, smin and smax.James Molloy2015-05-159-9/+85
| | | | | | | | | | | | | This adds new SDNodes for signed/unsigned min/max. These nodes are built from select/icmp pairs matched at SDAGBuilder stage. This patch adds the nodes, as well as legalization support and sets them to be "expand" for all targets. NFC for now; this will be tested when I switch AArch64 to using these new nodes. llvm-svn: 237423
* Doxygen: Enable autobrief feature and update coding standards.Matthias Braun2015-05-152-16/+17
| | | | llvm-svn: 237417
* [PlaceSafepoints] Fix a bug that came in with rL236672.Sanjoy Das2015-05-152-0/+44
| | | | | | | | Transfer the calling convention from the invoke being replaced by PlaceStatepoints to the new invoke to gc.statepoint created. Add a test case that would have caught this issue. llvm-svn: 237414
* [PlaceSafepoints] Fix a bug that came in with rL236672.Sanjoy Das2015-05-152-1/+43
| | | | | | | | | rL236672 would generate all invoke statepoints with deopt args set to a list containing the single element "0", instead of an empty list. Also add a test case that would have caught this. llvm-svn: 237413
* Stop resetting SanitizeAddress in TargetMachine::resetTargetOptions. NFC.Akira Hatanaka2015-05-154-5/+12
| | | | | | | | | | | | | | Instead of doing that, create a temporary copy of MCTargetOptions and reset its SanitizeAddress field based on the function's attribute every time an InlineAsm instruction is emitted in AsmPrinter::EmitInlineAsm. This is part of the work to remove TargetMachine::resetTargetOptions (the FIXME added to TargetMachine.cpp in r236009 explains why this function has to be removed). Differential Revision: http://reviews.llvm.org/D9570 llvm-svn: 237412
* Fix the check strings in a test case committed in r212455.Akira Hatanaka2015-05-151-2/+2
| | | | | | | The access size (8, in this case) was missing in the function name that was being checked. llvm-svn: 237410
* docs: Fix up some .rst formattingJustin Bogner2015-05-141-3/+3
| | | | llvm-svn: 237409
* MC: Avoid some UB caused by left shifting a negative value. NFCJustin Bogner2015-05-141-1/+1
| | | | llvm-svn: 237408
* [ValueTracking] refactor: extract method haveNoCommonBitsSetJingyue Wu2015-05-145-71/+100
| | | | | | | | | | | | | | | | | | | | | Summary: Extract method haveNoCommonBitsSet so that we don't have to duplicate this logic in InstCombine and SeparateConstOffsetFromGEP. This patch also makes SeparateConstOffsetFromGEP more precise by passing DominatorTree to computeKnownBits. Test Plan: value-tracking-domtree.ll that tests ValueTracking indeed leverages dominating conditions Reviewers: broune, meheff, majnemer Reviewed By: majnemer Subscribers: jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D9734 llvm-svn: 237407
* Add a missing piece of existing practice to the developer policy. This may ↵Nick Lewycky2015-05-141-0/+5
| | | | | | need further refinement, but I think is roughly correct. llvm-svn: 237405
* YAML: Add support for literal block scalar I/O.Alex Lorenz2015-05-144-1/+313
| | | | | | | | | | | | | This commit gives the users of the YAML Traits I/O library the ability to serialize scalars using the YAML literal block scalar notation by allowing them to implement a specialization of the `BlockScalarTraits` struct for their custom types. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D9613 llvm-svn: 237404
* 80-col fixups.Eric Christopher2015-05-141-15/+21
| | | | llvm-svn: 237403
* [lib/Fuzzer] Add SHA1 implementation from public domain.Kostya Serebryany2015-05-145-38/+225
| | | | | | | | | | | | | | | | | | | | | | | Summary: This adds a SHA1 implementation taken from public domain code. The change is trivial, but as it involves third-party code I'd like a second pair of eyes before commit. LibFuzzer can not use SHA1 from openssl because openssl may not be available and because we may be fuzzing openssl itself. Using sha1sum via a pipe is too slow. Test Plan: n/a Reviewers: chandlerc Reviewed By: chandlerc Subscribers: majnemer, llvm-commits Differential Revision: http://reviews.llvm.org/D9733 llvm-svn: 237400
* Reflow comments and remove one that predated the enum being inEric Christopher2015-05-141-4/+3
| | | | | | the current file. llvm-svn: 237399
* Remove setting FloatABIType from the X86 port, nothing uses it.Eric Christopher2015-05-141-4/+0
| | | | llvm-svn: 237398
* Add another InstCombine pass after LoopUnroll.Wei Mi2015-05-142-0/+88
| | | | | | | | This is to cleanup some redundency generated by LoopUnroll pass. Such redundency may not be cleaned up by existing passes after LoopUnroll. Differential Revision: http://reviews.llvm.org/D9777 llvm-svn: 237395
* Don't rely on implicit pointerness of 'auto'. Davide Italiano2015-05-141-1/+1
| | | | | | | This ends up being a copy. Pointy hat to me. Reported by: dexonsmith, dblaikie llvm-svn: 237394
* Fix memory leak introduced in r237314.Alex Lorenz2015-05-141-1/+1
| | | | | | | | | | | | | | The commit r237314 that implements YAML block parsing introduced a leak that was caught by the ASAN linux buildbot. YAML Parser stores its tokens in an ilist, and allocates tokens using a BumpPtrAllocator, but doesn't call the destructor for the allocated tokens. R237314 added an std::string field to a Token which leaked as the Token's destructor wasn't called. This commit fixes this leak by calling the Token's destructor when a Token is being removed from an ilist of tokens. llvm-svn: 237389
* [Hexagon] Generate hardware loop for a vectorized loopBrendon Cahoon2015-05-142-7/+139
| | | | | | | | | The induction variable in the vectorized loop wasn't recognized properly, so a hardware loop wasn't generated. Differential Revision: http://reviews.llvm.org/D9722 llvm-svn: 237388
* Turn effective assert(0) into llvm_unreachableMatthias Braun2015-05-141-3/+1
| | | | llvm-svn: 237379
* Update obsolete comments, fix typo, delete trailing space.Douglas Katzman2015-05-141-5/+5
| | | | llvm-svn: 237378
* [ConstantFolding] Fix wrong folding of intrinsic 'convert.from.fp16'.Andrea Di Biagio2015-05-142-2/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Function 'ConstantFoldScalarCall' (in ConstantFolding.cpp) works under the wrong assumption that a call to 'convert.from.fp16' returns a value of type 'float'. However, intrinsic 'convert.from.fp16' can be overloaded; for example, we can call 'convert.from.fp16.f64' to convert from half to double; etc. Before this patch, the following example would have triggered an assertion failure in opt (with -constprop): ``` define double @foo() { entry: %0 = call double @llvm.convert.from.fp16.f64(i16 0) ret double %0 } ``` This patch fixes the problem in ConstantFolding.cpp. When folding a call to convert.from.fp16, we perform a different kind of conversion based on the call return type. Added test 'Transform/ConstProp/convert-from-fp16.ll'. Differential Revision: http://reviews.llvm.org/D9771 llvm-svn: 237377
* TargetSchedule: factor out common code; NFCMatthias Braun2015-05-142-21/+20
| | | | llvm-svn: 237376
* Remove MCInstrItineraries includes in parts that don't use them anymoreMatthias Braun2015-05-143-3/+0
| | | | llvm-svn: 237375
* [Hexagon] Remove dead constant assignment in hardware loop passBrendon Cahoon2015-05-142-3/+32
| | | | | | | | | | | After converting a loop to a hardware loop, the pass should remove any unnecessary instructions from the old compare-and-branch code. This patch removes a dead constant assignment that was used in the compare instruction. Differential Revision: http://reviews.llvm.org/D9720 llvm-svn: 237373
* Enable solid lzma compression for cpack, decreases setup size by ~30%Ismail Donmez2015-05-141-0/+1
| | | | | | Reviewed by Hans Wennborg llvm-svn: 237372
* Reflow long lines of some LLVMBuild filesDouglas Katzman2015-05-143-3/+24
| | | | | | Differential Revision: http://reviews.llvm.org/D9752 llvm-svn: 237367
* [mips] [IAS] Enforce .set nomacro.Toma Tabacu2015-05-143-0/+89
| | | | | | | | | | | | | | Summary: When used, ".set nomacro" causes warning messages to be reported when we expand pseudo-instructions to multiple machine instructions. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9564 llvm-svn: 237366
* [Hexagon] Check for underflow/wrap in hardware loop passBrendon Cahoon2015-05-145-55/+505
| | | | | | | | If the loop trip count may underflow or wrap, the compiler should not generate a hardware loop since the trip count will be incorrect. llvm-svn: 237365
* [mips] [IAS] Emit .set macro/nomacro.Toma Tabacu2015-05-143-2/+6
| | | | | | | | | | | | Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9563 llvm-svn: 237363
* [mips] Do not place users of $ra in the delay slot of call instructions.Vasileios Kalintiris2015-05-142-0/+191
| | | | | | | | | | | | | | | Summary: When we are trying to fill the delay slot of a call instruction, we must avoid filler instructions that use the $ra register. This fixes the test MultiSource/Applications/JM/lencod when we enable the forward delay slot filler. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9670 llvm-svn: 237362
* Re-apply r237247 - [AArch64] Codegen VMAX/VMIN for safe math casesArtyom Skrobov2015-05-143-47/+105
| | | | | | No longer breaks SPEC2000/2006 llvm-svn: 237361
* Attempt to fix MSVC botsAdam Nemet2015-05-141-3/+3
| | | | llvm-svn: 237359
* New Loop Distribution passAdam Nemet2015-05-1412-0/+1487
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This implements the initial version as was proposed earlier this year (http://lists.cs.uiuc.edu/pipermail/llvmdev/2015-January/080462.html). Since then Loop Access Analysis was split out from the Loop Vectorizer and was made into a separate analysis pass. Loop Distribution becomes the second user of this analysis. The pass is off by default and can be enabled with -enable-loop-distribution. There is currently no notion of profitability; if there is a loop with dependence cycles, the pass will try to split them off from other memory operations into a separate loop. I decided to remove the control-dependence calculation from this first version. This and the issues with the PDT are actively discussed so it probably makes sense to treat it separately. Right now I just mark all terminator instruction required which keeps identical CFGs for each distributed loop. This seems to be working pretty well for 456.hmmer where even though there is an empty if-then block in the distributed loop initially, it gets completely removed. The pass keeps DominatorTree and LoopInfo updated. I've tested this with -loop-distribute-verify with the testsuite where we distribute ~90 loops. SimplifyLoop is violated in some cases and I have a FIXME covering this. Reviewers: hfinkel, nadav, aschwaighofer Reviewed By: aschwaighofer Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8831 llvm-svn: 237358
* Fixed some typos and broken links in source level debugging docs.Michael Kuperstein2015-05-142-11/+13
| | | | llvm-svn: 237357
* [mips] [IAS] Warn when LA is used with a 64-bit symbol.Toma Tabacu2015-05-143-25/+20
| | | | | | | | | | | | Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9295 llvm-svn: 237356
* [mips] [IAS] Give expandLoadAddressSym() more specific arguments. NFC.Toma Tabacu2015-05-141-23/+13
| | | | | | | | | | | | | | | | Summary: If we only pass the necessary operands, we don't have to determine the position of the symbol operand when entering expandLoadAddressSym(). This simplifies the expandLoadAddressSym() code. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9291 llvm-svn: 237355
* [AArch64] Slight naming changes and comments for AArch64NamedImmMapperVladimir Sukharev2015-05-141-4/+7
| | | | | | | | | | | | Reviewers: echristo Subscribers: llvm-commits Follow-up to: http://reviews.llvm.org/D8496#158595 Relates to: http://reviews.llvm.org/rL235089 llvm-svn: 237354
* AVX-512: Added i1 type handling for calling conventions.Elena Demikhovsky2015-05-143-22/+99
| | | | | | | | i1 type is a legal type on AVX-512 and can be passed as parameter or return value. i1 is promoted to i8 on return and to i32 for call arguments (i8 is also promoted to i32 here). The result code is similar to the previous X86 targets, where i1 is allways promoted to i8. llvm-svn: 237350
* TableGen: Avoid undefined behaviour by doing this shift in int64Justin Bogner2015-05-141-1/+1
| | | | | | | | Found by ubsan. This was taking a bool and left shifting by 32 - the result is 64 bit, so we should really do the math in a type it fits in. llvm-svn: 237345
* [TableGen] Remove an unnecessary outer 'if' around 3 separate inner ifs. No ↵Craig Topper2015-05-141-29/+25
| | | | | | | | functional change intended. The outer if had 3 separate conditions ORed together and then the inner ifs detected which of the three conditions it was by using only a portion of the specific condition. Just put the whole condition in each inner if and remove the outer if. llvm-svn: 237343
* [TableGen] Simplify some code. NFCCraig Topper2015-05-141-9/+4
| | | | llvm-svn: 237342
* [TableGen] Remove ListInit::size() in favor of getSize() which does the same ↵Craig Topper2015-05-142-3/+2
| | | | | | thing and is already used in most places. NFC. llvm-svn: 237341
OpenPOWER on IntegriCloud