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* [Reassociate] Don't canonicalize x + (-Constant * y) -> x - (Constant * y)..Chad Rosier2017-08-232-0/+28
| | | | | | | | | | | | | ..if the resulting subtract will be broken up later. This can cause us to get into an infinite loop. x + (-5.0 * y) -> x - (5.0 * y) ; Canonicalize neg const x - (5.0 * y) -> x + (0 - (5.0 * y)) ; Break up subtract x + (0 - (5.0 * y)) -> x + (-5.0 * y) ; Replace 0-X with X*-1. PR34078 llvm-svn: 311554
* [Bash-autocompletion] Add support for static analyzer flagsYuka Takahashi2017-08-234-8/+60
| | | | | | | | | | | | | | | | | | | | | | Summary: This is a patch for clang autocomplete feature. It will collect values which -analyzer-checker takes, which is defined in clang/StaticAnalyzer/Checkers/Checkers.inc, dynamically. First, from ValuesCode class in Options.td, TableGen will generate C++ code in Options.inc. Options.inc will be included in DriverOptions.cpp, and calls OptTable's addValues function. addValues function will add second argument to Option's Values class. Values contains string like "foo,bar,.." which is handed to Values class in OptTable. Reviewers: v.g.vassilev, teemperor, ruiu Subscribers: hiraditya, cfe-commits Differential Revision: https://reviews.llvm.org/D36782 llvm-svn: 311552
* [globalisel][tablegen] Add support for ImmLeaf without SDNodeXFormDaniel Sanders2017-08-235-19/+234
| | | | | | | | | | | | | | | | | | | Summary: This patch adds support for predicates on imm nodes but only for ImmLeaf and not for PatLeaf or PatFrag and only where the value does not need to be transformed before being rendered into the instruction. The limitation on PatLeaf/PatFrag/SDNodeXForm is due to differences in the necessary target-supplied C++ for GlobalISel. Depends on D36085 Reviewers: ab, t.p.northover, qcolombet, rovka, aditya_nandakumar Reviewed By: rovka Subscribers: kristof.beyls, javed.absar, igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D36086 llvm-svn: 311546
* [ARM] Check for assembler instructions in test.Florian Hahn2017-08-231-9/+10
| | | | | | Currently this test causes test failures on some machines, due to isel not being registered. Update the test to run all passes and check emitted assembly instructions for now. llvm-svn: 311545
* [ARM] Add missing patterns for insert_subvector.Florian Hahn2017-08-232-0/+49
| | | | | | | | | | | | | | Summary: In some cases, shufflevector instruction can be transformed involving insert_subvector instructions. The ARM backend was missing some insert_subvector patterns, causing a failure during instruction selection. AArch64 has similar patterns. Reviewers: t.p.northover, olista01, javed.absar, rengolin Reviewed By: javed.absar Subscribers: aemerson, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D36796 llvm-svn: 311543
* [globalisel][tablegen] Add tests for FeatureBitsets and ComplexPattern ↵Daniel Sanders2017-08-232-4/+26
| | | | | | predicates. llvm-svn: 311542
* [gold] Test we don't strip globals when producing relocatables.Davide Italiano2017-08-231-0/+26
| | | | | | | lld was broken in this regard (PR33097). The gold plugin gets this right so, no changes needed, but better adding a test. llvm-svn: 311541
* [InstCombine] Fold branches with irrelevant conditions to a constant.Davide Italiano2017-08-234-7/+17
| | | | | | | | | | | | | | | | InstCombine folds instructions with irrelevant conditions to undef. This, as Nuno confirmed is a bug. (see https://bugs.llvm.org/show_bug.cgi?id=33409#c1 ) Given the original motivation for the change is that of removing an USE, we now fold to false instead (which reaches the same goal without undesired side effects). Fixes PR33409. Differential Revision: https://reviews.llvm.org/D36975 llvm-svn: 311540
* [PowerPC] better instruction selection for OR (XOR) with a 32-bit immediateHiroshi Inoue2017-08-232-0/+147
| | | | | | | | | | | | | | | | | | | | | | | | | - recommitting after fixing a test failure on MacOS On PPC64, OR (XOR) with a 32-bit immediate can be done with only two instructions, i.e. ori + oris. But the current LLVM generates three or four instructions for this purpose (and also it clobbers one GPR). This patch makes PPC backend generate ori + oris (xori + xoris) for OR (XOR) with a 32-bit immediate. e.g. (x | 0xFFFFFFFF) should be ori 3, 3, 65535 oris 3, 3, 65535 but LLVM generates without this patch li 4, 0 oris 4, 4, 65535 ori 4, 4, 65535 or 3, 3, 4 Differential Revision: https://reviews.llvm.org/D34757 llvm-svn: 311538
* [AArch64] Silence unused variable warning in opt mode after r311533Krasimir Georgiev2017-08-231-4/+3
| | | | llvm-svn: 311535
* [AArch64] ISel legalization debug messages. NFCI.Sjoerd Meijer2017-08-231-12/+47
| | | | | | | | | | | Debugging AArch64 instruction legalization and custom lowering is really an unpleasant experience because it shows nodes that appear out of thin air. In commit r311444, some debug messages have been added to SelectionDAG, the target independent part, and this patch adds some AArch64 specific messages. Differential Revision: https://reviews.llvm.org/D36964 llvm-svn: 311533
* [Lanai] Remove dead functions from LanaiRegisterInfoAlex Bradbury2017-08-232-13/+0
| | | | | | | | | getEHExceptionRegister and getEHHandlerRegister are unused and were removed from most backends in rL192099. This patch removes them from Lanai. Differential Revision: https://reviews.llvm.org/D36829 llvm-svn: 311531
* Revert rL311526: [PowerPC] better instruction selection for OR (XOR) with a ↵Hiroshi Inoue2017-08-232-147/+0
| | | | | | | | 32-bit immediate This reverts commit rL311526 due to failures in some buildbot. llvm-svn: 311530
* [InstCombine] Remove unused argument. NFCCraig Topper2017-08-232-5/+4
| | | | llvm-svn: 311529
* [InstCombine] Replace a simple matcher with a plain old dyn_cast. NFCCraig Topper2017-08-231-2/+1
| | | | llvm-svn: 311528
* [InstCombine] Remove an unnecessary dyn_cast to Instruction and a switch ↵Craig Topper2017-08-232-25/+18
| | | | | | | | over two opcodes. Just dyn_cast to the specific instruction classes individually. NFC Change the helper methods to take the more specific class as well. llvm-svn: 311527
* [PowerPC] better instruction selection for OR (XOR) with a 32-bit immediateHiroshi Inoue2017-08-232-0/+147
| | | | | | | | | | | | | | | | | | | | | | | On PPC64, OR (XOR) with a 32-bit immediate can be done with only two instructions, i.e. ori + oris. But the current LLVM generates three or four instructions for this purpose (and also it clobbers one GPR). This patch makes PPC backend generate ori + oris (xori + xoris) for OR (XOR) with a 32-bit immediate. e.g. (x | 0xFFFFFFFF) should be ori 3, 3, 65535 oris 3, 3, 65535 but LLVM generates without this patch li 4, 0 oris 4, 4, 65535 ori 4, 4, 65535 or 3, 3, 4 Differential Revision: https://reviews.llvm.org/D34757 llvm-svn: 311526
* [XRay][CodeGen] Use PIC-friendly code in XRay sleds; remove synthetic ↵Dean Michael Berris2017-08-2314-150/+132
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | references in .text Summary: This change achieves two things: - Redefine the Custom Event handling instrumentation points emitted by the compiler to not require dynamic relocation of references to the __xray_CustomEvent trampoline. - Remove the synthetic reference we emit at the end of a function that we used to keep auxiliary sections alive in favour of SHF_LINK_ORDER associated with the section where the function is defined. To achieve the custom event handling change, we've had to introduce the concept of sled versioning -- this will need to be supported by the runtime to allow us to understand how to turn on/off the new version of the custom event handling sleds. That change has to land first before we change the way we write the sleds. To remove the synthetic reference, we rely on a relatively new linker feature that preserves the sections that are associated with each other. This allows us to limit the effects on the .text section of ELF binaries. Because we're still using absolute references that are resolved at runtime for the instrumentation map (and function index) maps, we mark these sections write-able. In the future we can re-define the entries in the map to use relative relocations instead that can be statically determined by the linker. That change will be a bit more invasive so we defer this for later. Depends on D36816. Reviewers: dblaikie, echristo, pcc Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D36615 llvm-svn: 311525
* bpf: add variants of -mcpu=# and support for additional jmp insnsYonghong Song2017-08-239-17/+147
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | -mcpu=# will support: . generic: the default insn set . v1: insn set version 1, the same as generic . v2: insn set version 2, version 1 + additional jmp insns . probe: the compiler will probe the underlying kernel to decide proper version of insn set. We did not not use -mcpu=native since llc/llvm will interpret -mcpu=native as the underlying hardware architecture regardless of -march value. Currently, only x86_64 supports -mcpu=probe. Other architecture will silently revert to "generic". Also added -mcpu=help to print available cpu parameters. llvm will print out the information only if there are at least one cpu and at least one feature. Add an unused dummy feature to enable the printout. Examples for usage: $ llc -march=bpf -mcpu=v1 -filetype=asm t.ll $ llc -march=bpf -mcpu=v2 -filetype=asm t.ll $ llc -march=bpf -mcpu=generic -filetype=asm t.ll $ llc -march=bpf -mcpu=probe -filetype=asm t.ll $ llc -march=bpf -mcpu=v3 -filetype=asm t.ll 'v3' is not a recognized processor for this target (ignoring processor) ... $ llc -march=bpf -mcpu=help -filetype=asm t.ll Available CPUs for this target: generic - Select the generic processor. probe - Select the probe processor. v1 - Select the v1 processor. v2 - Select the v2 processor. Available features for this target: dummy - unused feature. Use +feature to enable a feature, or -feature to disable it. For example, llc -mcpu=mycpu -mattr=+feature1,-feature2 ... Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> Signed-off-by: Yonghong Song <yhs@fb.com> Acked-by: Alexei Starovoitov <ast@kernel.org> llvm-svn: 311522
* Fix tail-merge-after-mbp testMatthias Braun2017-08-231-14/+14
| | | | | | | | The output of this test changed after the fix in r311520 to have -run-pass=block-placement behave like it does in a normal pipeline. Adjust the test. llvm-svn: 311521
* Add test case for r311511Matthias Braun2017-08-235-5/+46
| | | | | | | | This also changes the TailDuplicator to be configured explicitely pre/post regalloc rather than relying on the isSSA() flag. This was necessary to have `llc -run-pass` work reliably. llvm-svn: 311520
* NFC: fix ToolDrivers syntax and typo errorsMartell Malone2017-08-232-7/+7
| | | | | | | infoTable -> InfoTable camelCase Libtool Options #define offset llvm-svn: 311517
* Update LLVM fuzzers to use the libFuzzer bundled with the compiler toolchainGeorge Karpenkov2017-08-238-25/+16
| | | | | | Differential Revision: https://reviews.llvm.org/D37041 llvm-svn: 311515
* Remove llvm-pdbutil/fuzzer.George Karpenkov2017-08-233-124/+0
| | | | | | | | The code does not compile, is not maintained, and does not have a buildbot. Differential Revision: https://reviews.llvm.org/D37032 llvm-svn: 311512
* TargetInstrInfo: Change duplicate() to work on bundles.Matthias Braun2017-08-227-36/+73
| | | | | | | | | | | | | | Adds infrastructure to clone whole instruction bundles rather than just single instructions. This fixes a bug where tail duplication would unbundle instructions while cloning. This should unbreak the "Clang Stage 1: cmake, RA, with expensive checks enabled" build on greendragon. The bot broke with r311139 hitting this pre-existing bug. A proper testcase will come next. llvm-svn: 311511
* [SelectionDAG] Make ISD::isConstantSplatVector always return an element ↵Craig Topper2017-08-224-23/+16
| | | | | | | | | | | | sized APInt. This partially reverts r311429 in favor of making ISD::isConstantSplatVector do something not confusing. Turns out the only other user of it was also having to deal with the weird property of it returning a smaller size. So rather than continue to deal with this quirk everywhere, just make the interface do something sane. Differential Revision: https://reviews.llvm.org/D37039 llvm-svn: 311510
* [InstCombine] Remove check for sext of vector icmp from shouldOptimizeCastCraig Topper2017-08-222-9/+2
| | | | | | | | | | | | Looks like for 'and' and 'or' we end up performing at least some of the transformations this is bocking in a round about way anyway. For 'and sext(cmp1), sext(cmp2) we end up later turning it into 'select cmp1, sext(cmp2), 0'. Then we optimize that back to sext (and cmp1, cmp2). This is the same result we would have gotten if shouldOptimizeCast hadn't blocked it. We do something analogous for 'or'. With this patch we allow that transformation to happen directly in foldCastedBitwiseLogic. And we now support the same thing for 'xor'. This is definitely opening up many other cases, but since we already went around it for some cases hopefully it's ok. Differential Revision: https://reviews.llvm.org/D36213 llvm-svn: 311508
* Revert "[llvm-dwarfdump] Print type names in DW_AT_type DIEs"Jonas Devlieghere2017-08-222-319/+1
| | | | | | This reverts commit r311492. llvm-svn: 311499
* [llvm-dwarfdump] Print type names in DW_AT_type DIEsJonas Devlieghere2017-08-222-1/+319
| | | | | | | This patch adds printing for DW_AT_type DIEs like it's currently already the case for DW_AT_specification DIEs. llvm-svn: 311492
* WholeProgramDevirt: Create bitcast to i8* at each virtual call site.Peter Collingbourne2017-08-226-5/+51
| | | | | | | | | We can't reuse the llvm.assume instruction's bitcast because it may not dominate every user of the vtable pointer. Differential Revision: https://reviews.llvm.org/D36994 llvm-svn: 311491
* [SanitizerCoverage] Optimize stack-depth instrumentation.Matt Morehouse2017-08-222-32/+14
| | | | | | | | | | | | | | | | Summary: Use the initialexec TLS type and eliminate calls to the TLS wrapper. Fixes the sanitizer-x86_64-linux-fuzzer bot failure. Reviewers: vitalybuka, kcc Reviewed By: kcc Subscribers: hiraditya, llvm-commits Differential Revision: https://reviews.llvm.org/D37026 llvm-svn: 311490
* [ADCE][Dominators] Reapply: Teach ADCE to preserve dominatorsJakub Kuderski2017-08-224-7/+130
| | | | | | | | | | | | | | | | | | | | | Summary: This patch teaches ADCE to preserve both DominatorTrees and PostDominatorTrees. This is reapplies the original patch r311057 that was reverted in r311381. The previous version wasn't using the batch update api for updating dominators, which in vary rare cases caused assertion failures. This also fixes PR34258. Reviewers: dberlin, chandlerc, sanjoy, davide, grosser, brzycki Reviewed By: davide Subscribers: grandinj, zhendongsu, llvm-commits, david2050 Differential Revision: https://reviews.llvm.org/D35869 llvm-svn: 311467
* [Debug info] Add new DbgValues after looping over DAGJonas Devlieghere2017-08-221-1/+5
| | | | | | | | | | I was contacted by Jesper Antonsson from Ericsson who ran into problems with r311181 in their test suites with for an out-of-tree target. Because of the latter I don't have a reproducer, but we definitely don't want to modify the data structure on which we are iterating inside the loop. llvm-svn: 311466
* [x86] auto-generate full checks; NFCSanjay Patel2017-08-221-11/+22
| | | | | | I don't see anything Darwin-specific here, so I made the target generic x86-64. llvm-svn: 311465
* [x86] simplify runs and auto-generate full checksSanjay Patel2017-08-221-33/+40
| | | | | | | | | I've replaced the two OS-specific runs with a generic run because there's no functional difference in the resulting output that we're checking. Also, the script still doesn't work with a Win target. llvm-svn: 311463
* Emit section information for extern variablesErich Keane2017-08-221-1/+9
| | | | | | | | | | Update IR generated to retain section information for external declarations. This is related to https://reviews.llvm.org/D36487 Patch By: eandrews Differential Revision: https://reviews.llvm.org/D36712 llvm-svn: 311459
* [ARM][AArch64] Add Armv8.3-a unittestsSam Parker2017-08-221-4/+10
| | | | | | | | Add Armv8.3-A to the architecture to the TargetParser unittests. Differential Revision: https://reviews.llvm.org/D36748 llvm-svn: 311450
* [ARM][AArch64] v8.3-A Javascript ConversionSam Parker2017-08-227-0/+65
| | | | | | | | | | Armv8.3-A adds instructions that convert a double-precision floating point number to a signed 32-bit integer with round towards zero, designed for improving Javascript performance. Differential Revision: https://reviews.llvm.org/D36785 llvm-svn: 311448
* [ARM] Avoid creating duplicate ANDs in SelectionDAGRenato Golin2017-08-222-9/+10
| | | | | | | | | | | When expanding a BRCOND into a BR_CC, do not create an AND 1 if one already exists. Review: D36705 Patch by Joel Galenson <jgalenson@google.com> llvm-svn: 311447
* [ARM] Call setBooleanContents(ZeroOrOneBooleanContent)Renato Golin2017-08-227-161/+30
| | | | | | | | | | | The ARM backend should call setBooleanContents so that it can use known bits to make some optimizations. Review: D35821 Patch by Joel Galenson <jgalenson@google.com> llvm-svn: 311446
* [SelectionDAG] Add getNode debug messagesSjoerd Meijer2017-08-221-8/+37
| | | | | | | | | | This adds debug messages to various functions that create new SDValue nodes. This is e.g. useful to have during legalization, as otherwise it can prints legalization info of nodes that did not appear in the dumps before. Differential Revision: https://reviews.llvm.org/D36984 llvm-svn: 311444
* [AArch64] Cleanup of HasFullFP16 argument. NFC.Sjoerd Meijer2017-08-221-27/+24
| | | | | | | | | This is a clean up of commit r311154; it's not necessary to pass HasFullFP16 as an argument, instead just query the DAG. Differential Revision: https://reviews.llvm.org/D36978 llvm-svn: 311438
* Fix a typo in r311435.Chandler Carruth2017-08-221-1/+1
| | | | llvm-svn: 311437
* Use report_fatal_error for unsupported calling conventionsAlex Bradbury2017-08-227-12/+12
| | | | | | | | | | | The calling convention can be specified by the user in IR. Failing to support a particular calling convention isn't a programming error, and so relying on llvm_unreachable to catch and report an unsupported calling convention is not appropriate. Differential Revision: https://reviews.llvm.org/D36830 llvm-svn: 311435
* [lib/Analysis] - Mark personality functions as live.George Rimar2017-08-225-0/+101
| | | | | | | | | | | | | | | | | | | | | | | | | This is PR33245. Case I am fixing is next: Imagine we have 2 BC files, one defines and uses personality routine, second has only declaration and also uses it. Previously algorithm computing dead symbols (llvm::computeDeadSymbols) did not know about personality routines and leaved them dead even if function that has routine was live. As a result thinLTOInternalizeAndPromoteGUID() method changed binding for such symbol to local. Later when LLD tried to link these objects it failed because one object had undefined global symbol for routine and second object contained local definition instead of global. Patch set the live root flag on the corresponding FunctionSummary for personality routines when we build the per-module summaries during the compile step. Differential revision: https://reviews.llvm.org/D36834 llvm-svn: 311432
* [X86] Prevent several calls to ISD::isConstantSplatVector from returning a ↵Craig Topper2017-08-225-10/+48
| | | | | | | | | | | | | | narrower APInt than the original scalar type ISD::isConstantSplatVector can shrink to the smallest splat width. But we don't check the size of the resulting APInt at all. This can cause us to misinterpret the results. This patch just adds a flag to prevent the APInt from changing width. Fixes PR34271. Differential Revision: https://reviews.llvm.org/D36996 llvm-svn: 311429
* Integrate manifest merging library into LLD.Eric Beckmann2017-08-221-1/+1
| | | | | | | | | | Summary: Now that the llvm-mt manifest merging libraries are complete, we may use them to merge manifests instead of needing to shell out to mt.exe. Subscribers: mgorny, llvm-commits Differential Revision: https://reviews.llvm.org/D36255 llvm-svn: 311424
* dsymutil: don't copy compile units without children from PCM filesAdrian Prantl2017-08-224-0/+30
| | | | | | rdar://problem/33830532 llvm-svn: 311416
* Moving libFuzzer from LLVM to compiler-rt.George Karpenkov2017-08-21152-3642/+4
| | | | | | | | | This change only removes libFuzzer tests and CMake machinery, the source copy temporarily remains at the old location. Differential Revision: https://reviews.llvm.org/D36980 llvm-svn: 311405
* Re-apply "Introduce FuzzMutate library"Justin Bogner2017-08-2117-0/+1624
| | | | | | | | | | | | | | Same as r311392 with some fixes for library dependencies. Thanks to Chapuni for helping work those out! Original commit message: This introduces the FuzzMutate library, which provides structured fuzzing for LLVM IR, as described in my EuroLLVM 2017 talk. Most of the basic mutators to inject and delete IR are provided, with support for most basic operations. llvm-svn: 311402
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