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* Remove a few gendered pronouns.Nico Weber2016-06-103-3/+3
| | | | llvm-svn: 272422
* Disable MSan-hostile loop unswitching.Evgeniy Stepanov2016-06-101-0/+18
| | | | | | | | | | | | | Loop unswitching may cause MSan false positive when the unswitch condition is not guaranteed to execute. This is very similar to ASan and TSan special case in llvm::isSafeToSpeculativelyExecute (they don't like speculative loads and stores), but for branch instructions. This is a workaround for PR28054. llvm-svn: 272421
* Move isGuaranteedToExecute out of LICM.Evgeniy Stepanov2016-06-103-67/+71
| | | | | | | Also rename LICMSafetyInfo to LoopSafetyInfo. Both will be used in LoopUnswitch in a separate change. llvm-svn: 272420
* [SystemZ] Support Compare and TrapsZhan Jun Liau2016-06-1012-44/+776
| | | | | | | | | | | | Support and generate Compare and Traps like CRT, CIT, etc. Support Trap as legal DAG opcodes and generate "j .+2" for them by default. Add support for Conditional Traps and use the If Converter to convert them into the corresponding compare and trap opcodes. Differential Revision: http://reviews.llvm.org/D21155 llvm-svn: 272419
* AMDGPU/SI: Don't use fixup_si_rodata for scratch rsrc relocationsTom Stellard2016-06-103-3/+11
| | | | | | | | | | | | | | | Summary: We need to set the fixup type to FK_Data_4 for the SCRATCH_RSRC_DWORD[01] symbols, since these require absolute relocations, and fixup_si_rodata is for relative relocations. Reviewers: arsenm, kzhuravl Subscribers: arsenm, kzhuravl, llvm-commits Differential Revision: http://reviews.llvm.org/D21153 llvm-svn: 272417
* Move CodeGen test from Generic to X86 specific directoryMehdi Amini2016-06-101-0/+0
| | | | llvm-svn: 272416
* Interprocedural Register Allocation (IPRA): add a Transformation PassMehdi Amini2016-06-105-0/+172
| | | | | | | | | | | | Adds a MachineFunctionPass that scans the body to find calls, and update the register mask with the one saved by the RegUsageInfoCollector analysis in PhysicalRegisterUsageInfo. Patch by Vivek Pandya <vivekvpandya@gmail.com> Differential Revision: http://reviews.llvm.org/D21180 llvm-svn: 272414
* [x86] add test for PR28044Sanjay Patel2016-06-101-0/+62
| | | | llvm-svn: 272411
* Add a period. NFC.Chad Rosier2016-06-101-1/+1
| | | | llvm-svn: 272410
* Fix whitespace. NFC.Chad Rosier2016-06-101-1/+1
| | | | llvm-svn: 272409
* test: split test into two filesSaleem Abdulrasool2016-06-102-38/+39
| | | | | | | Split up the test cases into two inputs as per post-commit review comments from Renato. NFC. llvm-svn: 272408
* [X86] Add costs for SSE zext/sext to v4i64 to TTIMichael Kuperstein2016-06-103-0/+96
| | | | | | | | | The costs are somewhat hand-wavy, but should be much closer to the truth than what we get from BasicTTI. Differential Revision: http://reviews.llvm.org/D21156 llvm-svn: 272406
* Interprocedural Register Allocation (IPRA) AnalysisMehdi Amini2016-06-1012-0/+383
| | | | | | | | | | | | | | | | | | | | | | | Add an option to enable the analysis of MachineFunction register usage to extract the list of clobbered registers. When enabled, the CodeGen order is changed to be bottom up on the Call Graph. The analysis is split in two parts, RegUsageInfoCollector is the MachineFunction Pass that runs post-RA and collect the list of clobbered registers to produce a register mask. An immutable pass, RegisterUsageInfo, stores the RegMask produced by RegUsageInfoCollector, and keep them available. A future tranformation pass will use this information to update every call-sites after instruction selection. Patch by Vivek Pandya <vivekvpandya@gmail.com> Differential Revision: http://reviews.llvm.org/D20769 llvm-svn: 272403
* [AArch64] Add preferred alignments for Exynos M1Evandro Menezes2016-06-103-2/+13
| | | | | | Differential Revision: http://reviews.llvm.org/D21203 llvm-svn: 272400
* [Hexagon] Remove incorrect offset scalingKrzysztof Parzyszek2016-06-101-4/+2
| | | | llvm-svn: 272399
* [x86] fix test attributes and autogenerate checksSanjay Patel2016-06-101-37/+50
| | | | llvm-svn: 272398
* [x86] add missing tests for fcmp ueq/oneSanjay Patel2016-06-101-0/+212
| | | | | | | | | | | | Somehow, the codegen logic for these sequences has gone completely untested until now (note the 2 compare instructions generated per test). There's also an *Intel* AVX optimization opportunity exposed in these cases and the existing tests. Intel's (but not AMD's) AVX spec shows that extra FP predicates were added, so a single comparison should always be sufficient, and operand commutation should never be necessary. llvm-svn: 272397
* [x86] regenerate checksSanjay Patel2016-06-101-184/+309
| | | | llvm-svn: 272396
* Reapply "[TTI] Refine default cost for interleaved load groups with gaps"Matthew Simpson2016-06-102-0/+87
| | | | | | | | This reapplies commit r272385 with a fix. The build was failing when compiled with gcc, but not with clang. With the fix, we now get the data layout from the current TTI implementation, which will hopefully solve the issue. llvm-svn: 272395
* Test commitRoman Shirokiy2016-06-101-3/+3
| | | | llvm-svn: 272393
* [X86][SSE] Added target shuffle combine tests for byte shift/rotates ↵Simon Pilgrim2016-06-101-0/+50
| | | | | | (PSLLDQ/PSRLDQ/PALIGNR) llvm-svn: 272392
* Revert "[TTI] Refine default cost for interleaved load groups with gaps"Matthew Simpson2016-06-102-86/+0
| | | | | | | This reverts commit r272385. This commit broke the build. I'm temporarily reverting to investigate. llvm-svn: 272391
* [TTI] Refine default cost for interleaved load groups with gapsMatthew Simpson2016-06-102-0/+86
| | | | | | | | | | | | This patch refines the default cost for interleaved load groups having gaps. If a load group has gaps, the legalized instructions corresponding to the unused elements will be dead. Thus, we don't need to account for them in the cost model. Instead, we only need to account for the fraction of legalized loads that will actually be used. Differential Revision: http://reviews.llvm.org/D20873 llvm-svn: 272385
* [AMDGPU] AsmParser: Support for sext() modifier in SDWA. Some code cleaning ↵Sam Kolton2016-06-106-263/+362
| | | | | | | | | | | | | | | | | | in AMDGPUOperand. Summary: sext() modifier is supported in SDWA instructions only for integer operands. Spec is unclear should integer operands support abs and neg modifiers with sext - for now they are not supported. Renamed InputModsWithNoDefault to FloatInputMods. Added SextInputMods for operands that support sext() modifier. Added AMDGPUOperand::Modifier struct to handle register and immediate modifiers. Code cleaning in AMDGPUOperand class: organize method in groups (render-, predicate-methods...). Reviewers: vpykhtin, artem.tamazov, tstellarAMD Subscribers: arsenm, kzhuravl Differential Revision: http://reviews.llvm.org/D20968 llvm-svn: 272384
* [X86][AVX512] Added VPSLLDQ/VPSRLDQ memory fold testsSimon Pilgrim2016-06-101-12/+44
| | | | | | | | | | Memory operand is new for AVX512 (SSE/AVX2 didn't support it). Also dropped the 'mask' from the tests (VPSLLDQ/VPSRLDQ don't support masked operations). Regenerated VPALIGNR test now that the shuffle comments work llvm-svn: 272383
* Fix stale name in comment.Sean Silva2016-06-101-1/+1
| | | | llvm-svn: 272382
* test commit: remove trailing whitespaces in README.txtRoger Ferrer Ibanez2016-06-101-8/+8
| | | | llvm-svn: 272380
* Bug fix remove another illegal char from prof symbol nameXinliang David Li2016-06-101-1/+1
| | | | | | | | End-end test with no integrated assembly should be added at some point (not done now because some bots are not properly configured to support -no-integrated-as) llvm-svn: 272376
* [LibFuzzer] Fix some unit test crashes on OSX.Dan Liew2016-06-101-0/+4
| | | | | | | | | | | | | | | | | | | | | This fixes the following unit tests: FuzzerDictionary.ParseOneDictionaryEntry FuzzerDictionary.ParseDictionaryFile The issue appears to be mixing non-ASan-ified code (LibFuzzer) and ASan-ified code (the unittest) as the tests would pass fine if everything was built with ASan enabled. I believe the issue is that different implementations of std::vector<> are being used in LibFuzzer and outside LibFuzzer (in the unittests). For Libcxx (I've not seen the issue manifest for libstdc++) we can disable the ASanified std::vector<> by definining the ``_LIBCPP_HAS_NO_ASAN`` macro. Doing this fixes the tests on OSX. Differential Revision: http://reviews.llvm.org/D21049 llvm-svn: 272374
* Add missing include for r272369Craig Topper2016-06-101-0/+1
| | | | llvm-svn: 272373
* [AVX512] Add shuffle comment printing for masked VPERMPD/VPERMQ.Craig Topper2016-06-102-1/+13
| | | | llvm-svn: 272371
* Make PDBFile take a StreamInterface instead of a MemBuffer.Zachary Turner2016-06-104-123/+137
| | | | | | | | | | | | | | | This is the next step towards being able to write PDBs. MemoryBuffer is immutable, and StreamInterface is our replacement which can be any combination of read-only, read-write, or write-only depending on the particular implementation. The one place where we were creating a PDBFile (in RawSession) is updated to subclass ByteStream with a simple adapter that holds a MemoryBuffer, and initializes the superclass with the buffer's array, so that all the functionality of ByteStream works transparently. llvm-svn: 272370
* Add support for writing through StreamInterface.Zachary Turner2016-06-1023-49/+752
| | | | | | | | | | | This adds method and tests for writing to a PDB stream. With this, even a PDB stream which is discontiguous can be treated as a sequential stream of bytes for the purposes of writing. Reviewed By: ruiu Differential Revision: http://reviews.llvm.org/D21157 llvm-svn: 272369
* [AVX512] Fix shuffle comment printing to handle the masked versions of some ↵Craig Topper2016-06-106-83/+99
| | | | | | shuffles. Previously we were printing the mask operands as the register names. llvm-svn: 272367
* [lit] Only gather redirected files for command failures.Daniel Dunbar2016-06-101-10/+11
| | | | | | | | | | | - The intended use of this was just in diagnostics, so we shouldn't pay the cost of reading these all the time. - This will avoid including the full output of each command in tests which fail, but the most important use case for this was to gather the output of the specific command which failed. llvm-svn: 272365
* AMDGPU: Fix trailing whitespaceMatt Arsenault2016-06-1010-40/+40
| | | | llvm-svn: 272364
* [esan|cfrag] Add the struct field offset array in StructInfoQin Zhao2016-06-102-13/+66
| | | | | | | | | | | | | | | Summary: Adds the struct field offset array in struct StructInfo. Updates test struct_field_count_basic.ll. Reviewers: aizatsky Subscribers: llvm-commits, bruening, eugenis, kcc, zhaoqin, vitalybuka Differential Revision: http://reviews.llvm.org/D21192 llvm-svn: 272362
* [LiveRangeEdit] Add a test case for r272314.Quentin Colombet2016-06-101-0/+268
| | | | | | | | | | The test case is not great espicially because it is still cumbersome to run the regalloc pass with run-pass. (We miss a bunch of initiliazier to be properly implemented.) Related to llvm.org/PR27983 llvm-svn: 272360
* Add null checks before using a pointer.Richard Trieu2016-06-101-0/+4
| | | | llvm-svn: 272359
* [llc] Do not create the pass config several times for run-pass.Quentin Colombet2016-06-101-6/+7
| | | | | | Thanks to Matthias Braun for spotting this. llvm-svn: 272358
* [llc] Add support for several run-pass options.Quentin Colombet2016-06-103-31/+70
| | | | | | | | | | | | | | | | | Previously we could run only one machine pass with the run-pass option. With that patch, we can now specify several passes with several run-pass options (or just one option with a list of comma separated passes) and llc will build the related pipeline. This is great to test the interaction of two passes that are not necessarily next to each other in the pipeline, or play with pass ordering. Now, we should be at parity with opt for the flexibility of running passes. Note: I also moved the run pass option from CommandFlags.h to llc.cpp because, really, this is needed only there! llvm-svn: 272356
* [esan|cfrag] Disable load/store instrumentation for cfragQin Zhao2016-06-103-8/+20
| | | | | | | | | | | | | | | | | | | | Summary: Adds ClInstrumentFastpath option to control fastpath instrumentation. Avoids the load/store instrumentation for the cache fragmentation tool. Renames cache_frag_basic.ll to working_set_slow.ll for slowpath instrumentation test. Adds the __esan_init check in struct_field_count_basic.ll. Reviewers: aizatsky Subscribers: llvm-commits, bruening, eugenis, kcc, zhaoqin, vitalybuka Differential Revision: http://reviews.llvm.org/D21079 llvm-svn: 272355
* Update call site attribute documentationMatt Arsenault2016-06-101-2/+2
| | | | | | convergent is also accepted. llvm-svn: 272353
* docs: Add AMDGPU relocation informationTom Stellard2016-06-101-0/+51
| | | | | | | | | | | | | | | | | | | | Summary: This documents the various relocation types that are supported by the Radeon Open Compute (ROC) runtime (which is essentially the dynamic linker for AMDGPU). Only R_AMDGPU_32 is not currently supported by the ROC runtime, but it will usually be resolved at link time by lld. Patch by: Konstantin Zhuravlyov Reviewers: kzhuravl, rafael Subscribers: rafael, arsenm, llvm-commits, kzhuravl Differential Revision: http://reviews.llvm.org/D20952 llvm-svn: 272352
* AMDGPU: v_cndmask_b32 does not def vccMatt Arsenault2016-06-102-2/+29
| | | | | | Fixes verifier errors after SIShrinkInstructions. llvm-svn: 272351
* AMDGPU/SI: Make sure to emit TargetConstant nodes when matching ds_*permuteTom Stellard2016-06-102-2/+11
| | | | | | | | | | | | | | | Summary: This fixes a bug with ds_*permute instructions where if it was passed a constant address, then the offset operand would get assigned a register operand instead of an immediate. Reviewers: scchan, arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D19994 llvm-svn: 272349
* [CMake] Removing fallback code for CMake versions before 3.1Chris Bieneman2016-06-091-14/+0
| | | | | | This code is dead code now. Out with the old, in with the new! llvm-svn: 272347
* AMDGPU/SI: Use common topological sort algorithm in SIScheduleDAGMITom Stellard2016-06-091-64/+3
| | | | | | | | | | Reviewers: arsenm, axeldavy Subscribers: MatzeB, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D19823 llvm-svn: 272346
* AMDGPU: Fix flat atomicsMatt Arsenault2016-06-098-41/+2301
| | | | | | | | The flat atomics could already be selected, but only when using flat instructions for global memory. Add patterns for flat addresses. llvm-svn: 272345
* AMDGPU: Fix i64 global cmpxchgMatt Arsenault2016-06-095-136/+189
| | | | | | | | | | This was using extract_subreg sub0 to extract the low register of the result instead of sub0_sub1, producing an invalid copy. There doesn't seem to be a way to use the compound subreg indices in tablegen since those are generated, so manually select it. llvm-svn: 272344
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