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* Rework r183728, suppress assert(0) for now. Its behavior depends on ↵NAKAMURA Takumi2013-06-113-7/+4
| | | | | | | assertions on win32 hosts. FIXME: Introduce yet another checker but assert(0). llvm-svn: 183736
* It adds support for negative zero offsets for loads and stores.Mihai Popa2013-06-112-2/+5
| | | | | | | Negative zero is returned by the primary expression parser as INT32_MIN, so all that the method needs to do is to accept this value. Behavior already present for Thumb2. llvm-svn: 183734
* This patch adds support for FPINST/FPINST2 as operands to vmsr/vmrs. These ↵Mihai Popa2013-06-114-6/+33
| | | | | | are optional registers that may be supported some ARM implementations to aid with resolution of floating point exceptions. The manual pages for vmsr and vmrs do not detail their use. Encodings and other information can be found in ARM Architecture Reference Manual section F, chapter 6, paragraph 3. llvm-svn: 183733
* ARM: Enforce decoding rules for VLDn instructionsAmaury de la Vieuville2013-06-115-106/+138
| | | | llvm-svn: 183731
* ARM: Fix STREX/LDREX reecodingAmaury de la Vieuville2013-06-113-10/+56
| | | | | | The decoded MCInst wasn't reencoded as the same instruction llvm-svn: 183729
* Tweak a couple of tests on win32 hosts with +Asserts.NAKAMURA Takumi2013-06-113-1/+7
| | | | | | | | - Don't use assert(0), or tests may pass or fail according to assertions. - For now, The tests are marked as XFAIL for win32 hosts. FIXME: Could we avoid XFAIL to specify triple in the RUN lines? llvm-svn: 183728
* ARMAsmBackend.cpp: Use Triple::isOSBinFormatCOFF() instead of isOSWindows().NAKAMURA Takumi2013-06-111-1/+1
| | | | | | FYI, isOSBinFormatCOFF() is as same as isOSWindows(), on trunk. llvm-svn: 183727
* Whitespace.NAKAMURA Takumi2013-06-111-5/+5
| | | | llvm-svn: 183726
* Fix dubious type name similar to member name.Sean Silva2013-06-118-17/+17
| | | | | | Should bring bots back to life. llvm-svn: 183715
* Fix spurious semicolons.Sean Silva2013-06-101-4/+4
| | | | | | Apparently these macros have semicolons inside of them already. llvm-svn: 183712
* [yaml2obj] Initial ELF support.Sean Silva2013-06-1014-1/+485
| | | | | | | | | Currently, only emitting the ELF header is supported (no sections or segments). The ELFYAML code organization is broadly similar to the COFFYAML code. llvm-svn: 183711
* ARM: diagnose ARM/Thumb assembly switches on CPUs only supporting one.Tim Northover2013-06-108-4/+59
| | | | | | | | | | | Some ARM CPUs only support ARM mode (ancient v4 ones, for example) and some only support Thumb mode (M-class ones currently). This makes sure such CPUs default to the correct mode and makes the AsmParser diagnose an attempt to switch modes incorrectly. rdar://14024354 llvm-svn: 183710
* Fix xemacs mode line, don't put them in .cpp files (just header files). NoNick Lewycky2013-06-101-1/+1
| | | | | | functionality change. llvm-svn: 183709
* Remove a few fixmes, the only work we're doing is getting the stringEric Christopher2013-06-101-4/+0
| | | | | | to return and this is done all over. llvm-svn: 183704
* Fix up comment.Eric Christopher2013-06-101-1/+1
| | | | llvm-svn: 183703
* Remove unused function.Eric Christopher2013-06-101-6/+0
| | | | llvm-svn: 183698
* IndentCount is only used within NDEBUG code.Eric Christopher2013-06-101-0/+2
| | | | llvm-svn: 183695
* X86: Stop LEA64_32r doing unspeakable things to its arguments.Tim Northover2013-06-108-76/+229
| | | | | | | | | | | | Previously LEA64_32r went through virtually the entire backend thinking it was using 32-bit registers until its blissful illusions were cruelly snatched away by MCInstLower and 64-bit equivalents were substituted at the last minute. This patch makes it behave normally, and take 64-bit registers as sources all the way through. Previous uses (for 32-bit arithmetic) are accommodated via SUBREG_TO_REG instructions which make the types and classes agree properly. llvm-svn: 183693
* Add a missing 'e'.Rafael Espindola2013-06-102-2/+2
| | | | llvm-svn: 183692
* tblgen: Assert that InstRWs doesn't grows when we don't expect it.Benjamin Kramer2013-06-101-0/+1
| | | | llvm-svn: 183690
* [PowerPC] Support extended sc mnemonicUlrich Weigand2013-06-102-0/+4
| | | | | | | | | A plain "sc" without argument is supposed to be treated like "sc 0" by the assembler. This patch adds a corresponding alias. Problem reported by Joerg Sonnenberger. llvm-svn: 183687
* [PowerPC] Support branch mnemonics with implied CR0Ulrich Weigand2013-06-102-1/+208
| | | | | | | | | | The extended branch mnemonics are supposed to use an implied CR0 if there is no explicit condition register specified. This patch adds extra variants of the mnemonics to this effect. Problem reported by Joerg Sonnenberger. llvm-svn: 183686
* [PowerPC] Use multiclass to generate extended branch mnemonicsUlrich Weigand2013-06-101-51/+22
| | | | | | | | | This patch removes some redundancy by generating the extended branch mnemonics via a multiclass. No change in behaviour expected. llvm-svn: 183685
* Silencing an MSVC warning about comparing signed and unsigned values.Aaron Ballman2013-06-101-1/+1
| | | | llvm-svn: 183682
* Remove the old IdentifyFileType now that lld was updated.Rafael Espindola2013-06-101-3/+0
| | | | llvm-svn: 183671
* Pass a StringRef to sys::identifyFileType.Rafael Espindola2013-06-109-18/+15
| | | | llvm-svn: 183669
* Fix an out of bounds array access.Rafael Espindola2013-06-101-2/+3
| | | | | | | We were looking at Magic[5] without checking Length. Since this path would not return unless Length >= 18 anyway, just move the >= 18 check up. llvm-svn: 183666
* Update for current naming conventions.Rafael Espindola2013-06-102-31/+35
| | | | | | I will change identifyFileType to use a StringRef in the next patch. llvm-svn: 183664
* Fix misleading comments in ARMAsmParserAmaury de la Vieuville2013-06-101-6/+6
| | | | llvm-svn: 183657
* ARM: ISB cannot be passed the same options as DMBAmaury de la Vieuville2013-06-1013-2/+179
| | | | | | ISB should only accepts full system sync, other options are reserved llvm-svn: 183656
* [NVPTX] Remove old CONST_NOT_GEN address space that is not being used ↵Justin Holewinski2013-06-104-39/+21
| | | | | | anymore and causes constants to be emitted in the global address space llvm-svn: 183652
* Avoid warnings about unused parameters that tend to come up a lot whenDuncan Sands2013-06-106-28/+30
| | | | | | | building outside projects with a different compiler than that used to build LLVM itself (eg switching between gcc and clang). llvm-svn: 183650
* Add test for ARM FastISel load/store register classesJF Bastien2013-06-101-0/+70
| | | | | | r183624 fixed an issue that was tested indirectly. Test it directly with this new test. llvm-svn: 183634
* Fix a regression I introduced when I expanded the complex pseudos inReed Kotler2013-06-093-9/+6416
| | | | | | | | | the Mips16 port. A few of the psuedos could either take signed or unsigned arguments and I did not distinguish the case and improperly rejected some valid cases that the assembler had previously accepted when they were pure pseudos that expanded as assembly instructions. llvm-svn: 183633
* tblgen: always lookup values from the original vector as it could be grown ↵Benjamin Kramer2013-06-091-6/+6
| | | | | | | | under our feet. PR16281. llvm-svn: 183630
* Add a const version of findNearestCommonDominator to PostDom for convenience.Benjamin Kramer2013-06-091-0/+5
| | | | | | PR16283. llvm-svn: 183629
* Refine the ARM EHABI test cases.Logan Chien2013-06-099-413/+323
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we have ARM unwind directive parser and assembler, we can check the correctness in two stages: 1. From LLVM assembly (.ll) to ARM assembly (.s) 2. From ARM assembly (.s) to ELF object file (.o) We already have several "*.s to *.o" test cases. This CL adds some "*.ll to *.s" test cases and removes the redundant "*.ll to *.o" test cases. New test cases to check "*.ll to *.s" code generator: - ehabi.ll: Check the correctness of the generated unwind directives. - section-name.ll: Check the section name of functions. Removed test cases: - ehabi-mc-cantunwind.ll (Covered by ehabi-cantunwind.ll, and eh-directive-cantunwind.s) - ehabi-mc-compact-pr0.ll (Covered by ehabi.ll, eh-compact-pr0.s, eh-directive-save.s, and eh-directive-setfp.s) - ehabi-mc-compact-pr1.ll (Covered by ehabi.ll, eh-compact-pr1.s, eh-directive-save.s, and eh-directive-setfp.s) - ehabi-mc.ll (Covered by ehabi.ll, and eh-directive-integrated-test.s) - ehabi-mc-section-group.ll (Covered by section-name.ll, and eh-directive-section-comdat.s) - ehabi-mc-section.ll (Covered by section-name.ll, and eh-directive-section.s) - ehabi-mc-sh_link.ll (Covered by eh-directive-text-section.s, and eh-directive-section.s) llvm-svn: 183628
* Fix ARM unwind opcode assembler in several cases.Logan Chien2013-06-0910-177/+499
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Changes to ARM unwind opcode assembler: * Fix multiple .save or .vsave directives. Besides, the order is preserved now. * For the directives which will generate multiple opcodes, such as ".save {r0-r11}", the order of the unwind opcode is fixed now, i.e. the registers with less encoding value are popped first. * Fix the $sp offset calculation. Now, we can use the .setfp, .pad, .save, and .vsave directives at any order. Changes to test cases: * Add test cases to check the order of multiple opcodes for the .save directive. * Fix the incorrect $sp offset in the test case. The stack pointer offset specified in the test case was incorrect. (Changed test cases: ehabi-mc-section.ll and ehabi-mc.ll) * The opcode to restore $sp are slightly reordered. The behavior are not changed, and the new output is same as the output of GNU as. (Changed test cases: eh-directive-pad.s and eh-directive-setfp.s) llvm-svn: 183627
* Removed PackedDouble domain from scalar instructions. Added more formats for ↵Elena Demikhovsky2013-06-094-46/+63
| | | | | | the scalar stuff. llvm-svn: 183626
* Make DeadArgumentElimination more conservative on variadic functionsTim Northover2013-06-092-5/+55
| | | | | | | Variadic functions are particularly fragile in the face of ABI changes, so this limits how much the pass changes them llvm-svn: 183625
* ARM FastISel fix load register classesJF Bastien2013-06-091-4/+4
| | | | | | | | The register classes when emitting loads weren't quite restricting enough, leading to MI verification failure on the result register. These are new failures that weren't there the first time I tried enabling ARM FastISel for new targets. llvm-svn: 183624
* TargetLowering: Clean up method description commentsDavid Majnemer2013-06-081-3/+3
| | | | llvm-svn: 183623
* sys::process::get_id() now returns the process ID instead of a process ↵Aaron Ballman2013-06-083-5/+5
| | | | | | handle on Windows. Patch thanks to Kim Gräsman! llvm-svn: 183621
* [Sparc] Delete FPMover Pass and remove Fp* Pseudo-instructions from Sparc ↵Venkatraman Govindaraju2013-06-088-162/+108
| | | | | | backend. llvm-svn: 183613
* ARM: fix VMOVvnf32 decoding when ambiguous with VCVTAmaury de la Vieuville2013-06-082-0/+11
| | | | | | Enforce Table A7-15 (op=1, cmode=0b111) -> UNDEF llvm-svn: 183612
* ARM: enforce SRS decoding constraintsAmaury de la Vieuville2013-06-082-4/+14
| | | | llvm-svn: 183611
* ARM: fix CPS decoding when ambiguous with QADDAmaury de la Vieuville2013-06-084-0/+47
| | | | | | | | | Handle the case when the disassembler table can't tell the difference between some encodings of QADD and CPS. Add some necessary safe guards in CPS decoding as well. llvm-svn: 183610
* ARM: fix VCVT decodingAmaury de la Vieuville2013-06-082-2/+10
| | | | | | UNPRED was reported instead of UNDEF llvm-svn: 183608
* Update code listings in LLVM tutorial.Logan Chien2013-06-086-4569/+12
| | | | | | | | | | | Several LLVM headers are moved. The code listings in LLVM tutorial are not updated yet. This CL removes the code replica in the .rst, and replace them with a literalinclude directive, so that sphinx can include the latest code automatically. llvm-svn: 183607
* Fix a potential bug in r183584.Shuxin Yang2013-06-082-26/+8
| | | | | | | | | | | | | r183584 tries to derive some info from the code *AFTER* a call and apply these derived info to the code *BEFORE* the call, which is not always safe as the call in question may never return, and in this case, the derived info is invalid. Thank Duncan for pointing out this potential bug. rdar://14073661 llvm-svn: 183606
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