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* [X86] Remove CompleteModel tags from CPU targets until we have better error ↵Simon Pilgrim2017-12-125-0/+53
| | | | | | | | | | checking (PR35636) The checks we have for complete models are not great and miss many cases - e.g. in PR35636 it failed to recognise that only the first output (of 2) was actually tagged by the InstRW Raised PR35639 and PR35643 as examples llvm-svn: 320492
* [RISCV][NFC] Formatting fix in RISCVInstrInfo.tdAlex Bradbury2017-12-121-4/+4
| | | | llvm-svn: 320491
* Revert "[InstCombine] Fix PR35618: Instcombine hangs on single minmax load ↵Alexey Bataev2017-12-122-50/+4
| | | | | | | | bitcast." This reverts commit r320488 because of the failed asan buildbots.. llvm-svn: 320490
* [InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.Alexey Bataev2017-12-122-4/+50
| | | | | | | | | | | | | | | | | Summary: If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1, &V2)))), bitcast)`, but the load is used in other instructions, it leads to looping in InstCombiner. Patch adds additional check that all users of the load instructions are stores and then replaces all uses of load instruction by the new one with new type. Reviewers: RKSimon, spatel, majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41072 llvm-svn: 320488
* [RISCV] Implement assembler pseudo instructions for RV32I and RV64IAlex Bradbury2017-12-128-1/+288
| | | | | | | | | | | | | | | | | | | | Adds the assembler pseudo instructions of RV32I and RV64I which can be mapped to a single canonical instruction. The missing pseudo instructions (e.g., call, tail, ...) are marked as TODO. Other things, like for example PCREL_LO, have to be implemented first. Currently, alias emission is disabled by default to keep the patch minimal. Alias emission by default will be enabled in a subsequent patch which also updates all affected tests. Note that this patch should actually break the floating point MC tests. However, the used FileCheck configuration is not tight enought to detect the breakage. Differential Revision: https://reviews.llvm.org/D40902 Patch by Mario Werner. llvm-svn: 320487
* Revert "[InstCombine] Fix PR35618: Instcombine hangs on single minmax load ↵Alexey Bataev2017-12-122-47/+2
| | | | | | | | bitcast." This reverts commit r320483 because of the failed Windows buildbots. llvm-svn: 320485
* [RISCV] MC layer support for the instructions added in the privileged specAlex Bradbury2017-12-123-0/+81
| | | | | | | | | | | | | | | Adds support for the instructions added in the RISC-V privileged ISA (https://content.riscv.org/wp-content/uploads/2017/05/riscv-privileged-v1.10.pdf): uret, sret, mret, wfi, and sfence.vma. Note from the committer: I made very minor formatting changes prior to commit, which didn't seem worth creating another review round-trip for. Differential Revision: https://reviews.llvm.org/D40383 Patch by David Craven. llvm-svn: 320484
* [InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.Alexey Bataev2017-12-122-2/+47
| | | | | | | | | | | | | | | | If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1, &V2)))), bitcast)`, but the load is used in other instructions, it leads to looping in InstCombiner. Patch adds additional check that all users of the load instructions are stores and then replaces all uses of load instruction by the new one with new type. Reviewers: RKSimon, spatel, majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41072 llvm-svn: 320483
* [X86] Recognize constant arrays with special values and replace loads from ↵Ayman Musa2017-12-122-22/+135
| | | | | | | | | | | | | | | | | | | it with subtract and shift instructions, which then will be replaced by X86 BZHI machine instruction. Recognize constant arrays with the following values: 0x0, 0x1, 0x3, 0x7, 0xF, 0x1F, .... , 2^(size - 1) -1 where //size// is the size of the array. the result of a load with index //idx// from this array is equivalent to the result of the following: (0xFFFFFFFF >> (sub 32, idx)) (assuming the array of type 32-bit integer). And the result of an 'AND' operation on the returned value of such a load and another input, is exactly equivalent to the X86 BZHI instruction behavior. See test cases in the LIT test for better understanding. Differential Revision: https://reviews.llvm.org/D34141 llvm-svn: 320481
* [InstComineLoadStoreAlloca] Optimize stores to GEP off null baseAnna Thomas2017-12-122-1/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Currently, in InstCombineLoadStoreAlloca, we have simplification rules for the following cases: 1. load off a null 2. load off a GEP with null base 3. store to a null This patch adds support for the fourth case which is store into a GEP with null base. Since this is UB as well (and directly analogous to the load off a GEP with null base), we can substitute the stored val with undef in instcombine, so that SimplifyCFG can optimize this code into unreachable code. Note: Right now, simplifyCFG hasn't been taught about optimizing this to unreachable and adding an llvm.trap (this is already done for the above 3 cases). Reviewers: majnemer, hfinkel, sanjoy, davide Reviewed by: sanjoy, davide Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41026 llvm-svn: 320480
* [PowerPC] Add branch flag on asm parser-only branch instructionsNemanja Ivanovic2017-12-121-1/+1
| | | | | | | | | | | This flag was missing but it wasn't an issue as nothing depended on it for these asm parser-only instructions. Now that LLDB support is slowly landing, it is important to get this right. Committing on behalf of Leonardo Bianconi. Differential revision: https://reviews.llvm.org/D40846 llvm-svn: 320475
* [PowerPC] Follow-up to r318436 to get the missed CSE opportunitiesNemanja Ivanovic2017-12-126-9/+218
| | | | | | | | | | | | | | | | | | The last of the three patches that https://reviews.llvm.org/D40348 was broken up into. Canonicalize the materialization of constants so that they are more likely to be CSE'd regardless of the bit-width of the use. If a constant can be materialized using PPC::LI, materialize it the same way always. For example: li 4, -1 li 4, 255 li 4, 65535 are equivalent if the uses only use the low byte. Canonicalize it to the first form. Differential Revision: https://reviews.llvm.org/D40348 llvm-svn: 320473
* Revert r320461 - causing ICE in windows buildssSimon Pilgrim2017-12-124-48/+1032
| | | | | | | | | | [X86] Use regular expressions more aggressively to reduce the number of scheduler entries needed for FMA3 instructions. When the scheduler tables are generated by tablegen, the instructions are divided up into groups based on their default scheduling information and how they are referenced by groups for each processor. For any set of instructions that are matched by a specific InstRW line, that group of instructions is guaranteed to not be in a group with any other instructions. So in general, the more InstRW class definitions are created, the more groups we end up with in the generated files. Particularly if a lot of the InstRW lines only match to single instructions, which is true of a large number of the Intel scheduler models. This change alone reduces the number of instructions groups from ~6000 to ~5500. And there's lots more we could do. llvm-svn: 320470
* [dsymutil] Accept line tables up to DWARFv5.Jonas Devlieghere2017-12-125-3/+54
| | | | | | | | | | | This patch removes the hard-coded check for DWARFv2 line tables. Now dsymutil accepts line tables for DWARF versions 2 to 5 (inclusive). Differential revision: https://reviews.llvm.org/D41084 rdar://35968319 llvm-svn: 320469
* Revert r320464 as it breaks gold plugin testsEugene Leviant2017-12-121-0/+14
| | | | llvm-svn: 320467
* Revert r320049, r320014 and r319894Igor Laevsky2017-12-129-91/+5
| | | | | | | They were causing failures of the piglit OpenGL tests with AMD GPUs using the Mesa radeonsi driver. llvm-svn: 320466
* [NFC][SafepointIRVerifier] Add alias for set of available valuesSerguei Katkov2017-12-121-13/+15
| | | | | | | | | | | | | Introduces usage of AvailableValueSet alias name instead of DenseSet<const Value *> for better reading. Patch Author: Daniil Suchkov Reviewers: mkazantsev, anna, apilipenko Reviewed By: anna Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41002 llvm-svn: 320465
* [ThinLTO] Remove unused code from thinLTOInternalizeModuleEugene Leviant2017-12-121-14/+0
| | | | | | Differential revision: https://reviews.llvm.org/D40970 llvm-svn: 320464
* [LV] Ignore the cost of values that will not appear in the vectorized loopDorit Nuzman2017-12-122-1/+82
| | | | | | | | | VecValuesToIgnore holds values that will not appear in the vectorized loop. We should therefore ignore their cost when VF > 1. Differential Revision: https://reviews.llvm.org/D40883 llvm-svn: 320463
* [X86] Use regular expressions more aggressively to reduce the number of ↵Craig Topper2017-12-124-1032/+48
| | | | | | | | | | scheduler entries needed for FMA3 instructions. When the scheduler tables are generated by tablegen, the instructions are divided up into groups based on their default scheduling information and how they are referenced by groups for each processor. For any set of instructions that are matched by a specific InstRW line, that group of instructions is guaranteed to not be in a group with any other instructions. So in general, the more InstRW class definitions are created, the more groups we end up with in the generated files. Particularly if a lot of the InstRW lines only match to single instructions, which is true of a large number of the Intel scheduler models. This change alone reduces the number of instructions groups from ~6000 to ~5500. And there's lots more we could do. llvm-svn: 320461
* [CallSiteSplitting] Don't let debug intrinsics affect optimizationsMikael Holmen2017-12-122-4/+62
| | | | | | | | | | | | | | | | | Summary: This solves PR35616. We don't want the compiler to generate different code when we compile with/without -g, so we now ignore debug intrinsics when determining if the optimization can trigger or not. Reviewers: junbuml Subscribers: davide, JDevlieghere, llvm-commits Differential Revision: https://reviews.llvm.org/D41068 llvm-svn: 320460
* [X86] Use Ld scheduler classes for instructions with folded loads.Craig Topper2017-12-124-73/+73
| | | | llvm-svn: 320459
* [X86] Correct the FMA3 regular expressions in the znver1 scheduler model.Craig Topper2017-12-122-36/+36
| | | | llvm-svn: 320458
* [AMDGPU] Rename Bonaire target to be gfx704; remove gfx800 and make Iceland ↵Tony Tye2017-12-121-11/+7
| | | | | | | | | | | | | | | | and Tonga both use gfx802; update target feature handling Correct committed version to match intended accepted review D40051 id=123417 - Rename Bonaire target to be gfx704. - Eliminate gfx800 and make Iceland and Tonga both use gfx802 as they use the same code. - List target features supported by each processor in the processor table together with the default value. - Add xnack flag to e_flags. - Remove xnack from kernel metadata and kernel descriptor since it is now a whole code object property. Differential Revision: https://reviews.llvm.org/D40051 llvm-svn: 320457
* [llvm-cov] Simplify a test case. NFC.Vedant Kumar2017-12-111-24/+5
| | | | llvm-svn: 320439
* [llvm-cov] Add an option for "export" command to emit only file summary data.Max Moroz2017-12-115-40/+63
| | | | | | | | | | | | | | Summary: That allows to get the same data as produced by "llvm-cov report", but in JSON format, which is better for further processing by end users. Reviewers: vsk Reviewed By: vsk Differential Revision: https://reviews.llvm.org/D41085 llvm-svn: 320435
* Reland "[WebAssembly] Import the linear memory and function table."Sam Clegg2017-12-119-72/+81
| | | | | | Original change: https://reviews.llvm.org/D40875 llvm-svn: 320432
* Revert r318704 - [Sparc] efficient pattern for UINT_TO_FP conversionRichard Trieu2017-12-114-144/+30
| | | | | | | | See bug https://bugs.llvm.org/show_bug.cgi?id=35631 r318704 is giving a fatal error on some code with unsigned to floating point conversions. llvm-svn: 320429
* LSR: Check more intrinsic pointer operandsMatt Arsenault2017-12-115-23/+167
| | | | llvm-svn: 320424
* Revert r320407 "[InstCombine] Fix PR35618: Instcombine hangs on single ↵Hans Wennborg2017-12-112-47/+2
| | | | | | | | | | | | | | | | | | | | | minmax load bitcast." The tests fail (opt asserts) on Windows. > Summary: > If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1, > &V2)))), bitcast)`, but the load is used in other instructions, it leads > to looping in InstCombiner. Patch adds additional check that all users > of the load instructions are stores and then replaces all uses of load > instruction by the new one with new type. > > Reviewers: RKSimon, spatel, majnemer > > Subscribers: llvm-commits > > Differential Revision: https://reviews.llvm.org/D41072 llvm-svn: 320421
* [CodeGen] Improve the consistency of instruction fusion*Evandro Menezes2017-12-111-24/+55
| | | | | | | | | | | When either instruction in a fused pair has no other dependency, besides on the other instruction, make sure that other instructions do not get scheduled between them. Additionally, avoid fusing an instruction more than once along the same dependency chain. Differential revision: https://reviews.llvm.org/D36704 llvm-svn: 320420
* ASAN: Provide reliable debug info for local variables at -O0.Adrian Prantl2017-12-116-5/+73
| | | | | | | | | | | | | | | | | | | | | | The function stack poisioner conditionally stores local variables either in an alloca or in malloc'ated memory, which has the unfortunate side-effect, that the actual address of the variable is only materialized when the variable is accessed, which means that those variables are mostly invisible to the debugger even when compiling without optimizations. This patch stores the address of the local stack base into an alloca, which can be referred to by the debug info and is available throughout the function. This adds one extra pointer-sized alloca to each stack frame (but mem2reg can optimize it away again when optimizations are enabled, yielding roughly the same debug info quality as before in optimized code). rdar://problem/30433661 Differential Revision: https://reviews.llvm.org/D41034 llvm-svn: 320415
* [PowerPC] Partially enable the ISEL expansion pass.Tony Jiang2017-12-116-97/+295
| | | | | | | | | | | The pass to expand ISEL instructions into if-then-else sequences in patch D23630 is currently disabled. This patch partially enable it by always removing the unnecessary ISELs (all registers used by the ISELs are the same one) and folding the ISELs which have the same input registers into unconditional copies. Differential Revision: https://reviews.llvm.org/D40497 llvm-svn: 320414
* [cmake] Pass TARGETS_TO_BUILD through to host tools buildJustin Bogner2017-12-111-1/+6
| | | | | | | | | | | | | | | | | | | | In r319620, the host build was changed to use Native for TARGETS_TO_BUILD because passing semicolons through add_custom_command is surprisingly difficult. However, Native really doesn't make any sense here, and it only works because we don't technically do any codegen in the host tools so pretty well anything will "work". The problem here is that passing something other than the correct value is very fragile - as evidence note how the llvm-config in the host tools acts differently than the target one now, and misreports the targets to build. Similarly, if there is any logic conditional on the targets in tablegen (now or in the future), it will do the wrong thing. To fix this, we need to escape the semicolons in the targets string and pass it through to the child cmake invocation. llvm-svn: 320413
* Ensure moved-from container is cleared on moveGeorge Burgess IV2017-12-112-0/+7
| | | | | | | | | In all cases except for this optimistic attempt to reuse memory, the moved-from TinyPtrVector was left `empty()` at the end of this assignment. Though using a container after it's been moved from can be a bit sketchy, it's probably best to just be consistent here. llvm-svn: 320408
* [InstCombine] Fix PR35618: Instcombine hangs on single minmax load bitcast.Alexey Bataev2017-12-112-2/+47
| | | | | | | | | | | | | | | | | Summary: If we have pattern `store (load(bitcast(select (cmp(V1, V2), &V1, &V2)))), bitcast)`, but the load is used in other instructions, it leads to looping in InstCombiner. Patch adds additional check that all users of the load instructions are stores and then replaces all uses of load instruction by the new one with new type. Reviewers: RKSimon, spatel, majnemer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41072 llvm-svn: 320407
* [Hexagon] Add support for Hexagon V65Krzysztof Parzyszek2017-12-1169-5709/+13168
| | | | llvm-svn: 320404
* [X86] Add LODS schedule testsSimon Pilgrim2017-12-111-6/+103
| | | | llvm-svn: 320403
* [X86] Add CMP/TEST schedule testsSimon Pilgrim2017-12-111-2/+1184
| | | | llvm-svn: 320402
* [X86] Add AND/OR/XOR schedule testsSimon Pilgrim2017-12-111-3/+1926
| | | | llvm-svn: 320400
* [dwarfdump] Fix off-by-one bug in accelerator table extractor.Jonas Devlieghere2017-12-116-10/+16
| | | | | | | | | | | | | | | This fixes a bug where the verifier was complaining about empty accelerator tables. When the table is empty, its size is not a valid offset as it points after the end of the section. This patch also makes the extractor return llvm:Error instead of bool for better error reporting in the verifier. Differential revision: https://reviews.llvm.org/D41063 rdar://35932007 llvm-svn: 320399
* [X86] Add ADD/SUB schedule testsSimon Pilgrim2017-12-111-2/+1285
| | | | llvm-svn: 320397
* [X86] Add ADC/SBB schedule testsSimon Pilgrim2017-12-111-2/+1284
| | | | llvm-svn: 320395
* [X86] Add MOVSLQ schedule testsSimon Pilgrim2017-12-111-1/+97
| | | | llvm-svn: 320392
* Normalize line endings. NFCI.Simon Pilgrim2017-12-111-30/+30
| | | | llvm-svn: 320389
* [GlobalISel] Disable GISel for big endian.Amara Emerson2017-12-114-2/+16
| | | | | | | | | | | | | This is due to PR26161 needing to be resolved before we can fix big endian bugs like PR35359. The work to split aggregates into smaller LLTs instead of using one large scalar will take some time, so in the mean time we'll fall back to SDAG. Some ARM BE tests xfailed for now as a result. Differential Revision: https://reviews.llvm.org/D40789 llvm-svn: 320388
* [X86] Add LWP schedule testsSimon Pilgrim2017-12-112-2/+181
| | | | | | Tag LWP instructions as WriteSystem llvm-svn: 320387
* [X86] Add INT/INTO schedule testsSimon Pilgrim2017-12-112-2/+147
| | | | llvm-svn: 320386
* [X86] Add IN/OUT schedule testsSimon Pilgrim2017-12-111-2/+246
| | | | llvm-svn: 320385
* [X86] Add IDIV schedule testsSimon Pilgrim2017-12-111-1/+164
| | | | llvm-svn: 320384
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