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* Revert r319423: [MC] Function stack size section.Sean Eveson2017-11-309-4575/+4481
| | | | | | I messed up the diff. llvm-svn: 319429
* [ARM GlobalISel] Bail out for byvalDiana Picus2017-11-302-1/+22
| | | | | | | Fallback if we have a byval parameter or argument since we don't support them yet. llvm-svn: 319428
* [CodeGen] Print "%vreg0" as "%0" in both MIR and debug outputFrancis Visoiu Mistrih2017-11-3079-523/+523
| | | | | | | | | | | | | | | | | As part of the unification of the debug format and the MIR format, avoid printing "vreg" for virtual registers (which is one of the current MIR possibilities). Basically: * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/%vreg([0-9]+)/%\1/g" * grep -nr '%vreg' . and fix if needed * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/ vreg([0-9]+)/ %\1/g" * grep -nr 'vreg[0-9]\+' . and fix if needed Differential Revision: https://reviews.llvm.org/D40420 llvm-svn: 319427
* [X86][AVX512] Tag binop/rounding/sae instructions scheduler classesSimon Pilgrim2017-11-301-124/+143
| | | | llvm-svn: 319424
* [MC] Function stack size section.Sean Eveson2017-11-309-4481/+4575
| | | | | | | | | | | | | | | | | | | | | | | | | Summary: Original RFC: http://lists.llvm.org/pipermail/llvm-dev/2017-August/117028.html I wasn't sure who to put as reviewers, so please add/remove people as appropriate. This change adds a '.stack-size' section containing metadata on function stack sizes to output ELF files behind the new -stack-size-section flag. The section contains pairs of function symbol references (8 byte) and stack sizes (unsigned LEB128). The contents of this section can be used to measure changes to stack sizes between different versions of the compiler or a source base. The advantage of having a section is that we can extract this information when examining binaries that we didn't build, and it allows users and tools easy access to that information just by referencing the binary. There is a follow up change to add an option to clang. Thanks. Reviewers: hfinkel, MatzeB Reviewed By: MatzeB Subscribers: thegameg, asb, llvm-commits Differential Revision: https://reviews.llvm.org/D39788 llvm-svn: 319423
* [DAGCombine] Refactor ReduceLoadWidthSam Parker2017-11-301-50/+33
| | | | | | | | | | visitAND attempts to narrow the width of extending loads that are then masked off. ReduceLoadWidth already exists for a similar purpose and handles shifts, so I've moved the code to handle AND nodes there. Differential Revision: https://reviews.llvm.org/D39595 llvm-svn: 319421
* Support generic lowering of vector bswapSerge Guelton2017-11-302-10/+60
| | | | llvm-svn: 319419
* [X86][AVX512] Tag RCP/RSQRT/GETEXP instructions scheduler classesSimon Pilgrim2017-11-303-70/+106
| | | | llvm-svn: 319418
* [dsymutil] Exclude namespace from ifdef in CFBundleJonas Devlieghere2017-11-301-0/+2
| | | | | | Should fix build failure introduced by r319416 on non-darwin hosts. llvm-svn: 319417
* [dsymutil] Upstream getBundleInfo implementationJonas Devlieghere2017-11-306-17/+305
| | | | | | | | | | | | | This patch implements `getBundleInfo`, which uses CoreFoundation to obtain information about the CFBundle. This information is needed to populate the Plist in the dSYM bundle. This change only applies to darwin and is an NFC as far as other platforms are concerned. Differential revision: https://reviews.llvm.org/D40244 llvm-svn: 319416
* Revert rL319407: [SROA] enable splitting for non-whole-alloca loads and stores Hiroshi Inoue2017-11-304-80/+27
| | | | | | This reverts commit rL319407 due to failures in some buildbot. llvm-svn: 319410
* [SystemZ] Bugfix in adjustSubwordCmp.Jonas Paulsson2017-11-302-4/+203
| | | | | | | | | | | | | | | | Csmith generated a program where a store after load to the same address did not get chained after the new load created during DAG legalizing, and so performed an illegal overwrite of the expected value. When the new zero-extending load is created, the chain users of the original load must be updated, which was not done previously. A similar case was also found and handled in lowerBITCAST. Review: Ulrich Weigand https://reviews.llvm.org/D40542 llvm-svn: 319409
* [SROA] enable splitting for non-whole-alloca loads and storesHiroshi Inoue2017-11-304-27/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, SROA splits loads and stores only when they are accessing the whole alloca. This patch relaxes this limitation to allow splitting a load/store if all other loads and stores to the alloca are disjoint to or fully included in the current load/store. If there is no other load or store that crosses the boundary of the current load/store, the current splitting implementation works as is. The whole-alloca loads and stores meet this new condition and so they are still splittable. Here is a simplified motivating example. struct record { long long a; int b; int c; }; int func(struct record r) { for (int i = 0; i < r.c; i++) r.b++; return r.b; } When updating r.b (or r.c as well), LLVM generates redundant instructions on some platforms (such as x86_64, ppc64); here, r.b and r.c are packed into one 64-bit GPR when the struct is passed as a method argument. With this patch, the above example is compiled into only few instructions without loop. Without the patch, unnecessary loop-carried dependency is introduced by SROA and the loop cannot be eliminated by the later optimizers. Differential Revision: https://reviews.llvm.org/D32998 llvm-svn: 319407
* [X86] Optimize avx2 vgatherqps for v2f32 with v2i64 index type.Craig Topper2017-11-302-15/+18
| | | | | | Normal type legalization will widen everything. This requires forcing 0s into the mask register. We can instead choose the form that only reads 2 elements without zeroing the mask. llvm-svn: 319406
* [X86] Make sure we don't remove sign extends of masks with AVX2 masked gathers.Craig Topper2017-11-302-7/+52
| | | | | | We don't use k-registers and instead use the MSB so we need to make sure we sign extend the mask to the msb. llvm-svn: 319405
* [XRay][docs] Update documentation on new default for xray_naive_log=Dean Michael Berris2017-11-302-4/+7
| | | | | | | | | We've recently changed the default for `xray_naive_log=` to be `false` instead of `true` to make it more consistent with the FDR mode logging implementation. This means we will now ask users to explicitly choose which version of the XRay logging is being used. llvm-svn: 319400
* - Removed unused lamba (IsReturnBlock) causing build bots to fail for r319398Graham Yiu2017-11-303-7/+290
| | | | | | - Added lit testcases that were supposed to be part of r319398 llvm-svn: 319399
* With PGO information, we can do more aggressive outlining of cold regions in ↵Graham Yiu2017-11-302-88/+587
| | | | | | | | | | | | the inline candidate function. This contrasts with the scheme of keeping only the 'early return' portion of the inline candidate and outlining the rest of the function as a single function call. Support for outlining multiple regions of each function is added, as well as some basic heuristics to determine which regions are good to outline. Outline candidates limited to regions that are single-entry & single-exit. We also avoid outlining regions that produce live-exit variables, which may inhibit some forms of code motion (like commoning). Fallback to the regular partial inlining scheme is retained when either i) no regions are identified for outlining in the function, or ii) the outlined function could not be inlined in any of its callers. Differential Revision: https://reviews.llvm.org/D38190 llvm-svn: 319398
* [libFuzzer] mention one more trophie in the Linux KernelKostya Serebryany2017-11-301-0/+2
| | | | llvm-svn: 319397
* AMDGPU: Allow negative MUBUF vaddr for gfx9Matt Arsenault2017-11-304-247/+159
| | | | | | | | GFX9 does not enable bounds checking for the resource descriptors used for private access, so it should be OK to use vaddr with a potentially negative value. llvm-svn: 319393
* Check alignment in getSectionContentsAsArray.Rafael Espindola2017-11-302-0/+24
| | | | | | | | While the ArrayRef can technically have unaligned data, it would be extremely surprising if iterating over it caused undefined behavior when a reference to the underlying type was bound. llvm-svn: 319392
* [Coverage] Use the most-recent completed region count (PR35437)Vedant Kumar2017-11-303-1/+35
| | | | | | | | | | | | | | | This is a fix for the coverage segment builder. If multiple regions must be popped off the active stack at once, and more than one of them end at the same location, emit a segment using the count from the most-recent completed region. Fixes PR35437, rdar://35760630 Testing: invoked llvm-cov on a stage2 build of clang, additional unit tests, check-profile llvm-svn: 319391
* LowerTypeTests: Deduplicate code. NFC.Peter Collingbourne2017-11-301-30/+17
| | | | llvm-svn: 319390
* LowerTypeTests: Remove unnecessary cast. NFC.Peter Collingbourne2017-11-301-1/+1
| | | | llvm-svn: 319387
* [X86] Remove some questionable looking code that seems to be looking through ↵Craig Topper2017-11-291-1/+1
| | | | | | | | | | a VZEXT to create a larger VSEXT. If the input the vzext was signed this would do the wrong thing. Not sure how to test this. llvm-svn: 319382
* First step towards more human-friendly PPC assembler output:Joerg Sonnenberger2017-11-294-32/+77
| | | | | | | | | | | | | | - add -ppc-reg-with-percent-prefix option to use %r3 etc as register names - split off logic for Darwinish verbose conditional codes into a helper function - be explicit about Darwin vs AIX vs GNUish assembler flavors Based on the patch from Alexandre Yukio Yamashita Differential Revision: https://reviews.llvm.org/D39016 llvm-svn: 319381
* [WebAssembly] Update test expectations for gcc torture testsSam Clegg2017-11-291-6/+0
| | | | | | | | | I believe these were recently fixed by: https://reviews.llvm.org/rL319186 Differential Revision: https://reviews.llvm.org/D40619 llvm-svn: 319380
* [CodeView] Factor some code out of TypeTableBuilder.Zachary Turner2017-11-293-43/+36
| | | | | | | | | | | This class had some code that would automatically remap type indices before hashing and serializing. The only caller of this method was the TypeStreamMerger anyway, and the method doesn't make general sense, and prevents making certain future improvements to the class. So, factoring this up one level into the TypeStreamMerger where it belongs. llvm-svn: 319377
* [SelectionDAG][X86] Teach promotion legalization for fp_to_sint/fp_to_uint ↵Craig Topper2017-11-293-23/+16
| | | | | | | | | | | | to insert an assertsext/assertzext based on the original type If we put in an assertsext/zext here, we're able to generate better truncate code using pack on pre-avx512 targets. Similar is already done during type legalization. This is the equivalent for op legalization Differential Revision: https://reviews.llvm.org/D40591 llvm-svn: 319368
* [WebAssembly] Fix fptoui lowering boundsDan Gohman2017-11-293-62/+99
| | | | | | | To fully avoid trapping on wasm, fptoui needs a second check to ensure that the operand isn't below the supported range. llvm-svn: 319354
* Add libstd++-4.8 exceptions to ubsan_blacklist.txtSam Clegg2017-11-291-0/+5
| | | | | | Differential Revision: https://reviews.llvm.org/D40589 llvm-svn: 319353
* [Hexagon] Remove HexagonISD::PACKHLKrzysztof Parzyszek2017-11-294-7/+2
| | | | llvm-svn: 319352
* [Hexagon] Create helpers extractVector and insertVector in loweringKrzysztof Parzyszek2017-11-292-139/+144
| | | | llvm-svn: 319351
* [X86][AVX512] Tag RCP/RSQRT/GETEXP instructions scheduler classes (REVERSION)Simon Pilgrim2017-11-293-86/+59
| | | | | | Accidental commit of incomplete patch llvm-svn: 319346
* Make TypeTableBuilder inherit from TypeCollection.Zachary Turner2017-11-295-24/+65
| | | | | | | | | | | | | | A couple of places in LLD were passing references to TypeTableCollections around, which makes it hard to change the implementation at runtime. However, these cases only needed to iterate over the types in the collection, and TypeCollection already provides a handy abstract interface for this purpose. By implementing this interface, we can get rid of the need to pass TypeTableBuilder references around, which should allow us to swap the implementation at runtime in subsequent patches. llvm-svn: 319345
* Fix line endings in llvm-pdbutil.cppZachary Turner2017-11-291-11/+11
| | | | llvm-svn: 319340
* [X86][AVX512] Tag RCP/RSQRT/GETEXP instructions scheduler classesSimon Pilgrim2017-11-293-59/+86
| | | | llvm-svn: 319338
* [X86][AVX512] Tag 3OP (shuffles, double-shifts and GFNI) instructions ↵Simon Pilgrim2017-11-293-222/+237
| | | | | | scheduler classes llvm-svn: 319337
* [ARM][DAG] Revert Disable post-legalization store merge for ARMNirav Dave2017-11-292-31/+22
| | | | | | | | Partially reverting enabling of post-legalization store merge (r319036) for just ARM backend as it is causing incorrect code in some Thumb2 cases. llvm-svn: 319331
* [cmake] Replace -Wall with /W4 in clang-cl options now that -Wall aliases ↵Greg Bedwell2017-11-291-60/+69
| | | | | | | | | | | | | | | -Weverything Instead, reuse the code-path for cl.exe that adds /W4 , which for clang-cl aliases clang's "-Wall -Wextra" which matches what clang-cl's /Wall previously aliased. This should restore the verbosity of a Windows selfhost build back to its previous levels. Differential Revision: https://reviews.llvm.org/D40603 llvm-svn: 319330
* Make check-lit tests respect LLVM_LIT_TOOLS_DIRGreg Bedwell2017-11-293-5/+9
| | | | | | Differential Revision: https://reviews.llvm.org/D40520 llvm-svn: 319329
* [Power9] add more tests for D38287; NFCZaara Syeda2017-11-291-0/+248
| | | | llvm-svn: 319328
* [InstCombine] add tests for select-of-constants; NFCSanjay Patel2017-11-291-0/+33
| | | | | | | | | These are variants of a test that was originally added in: https://reviews.llvm.org/rL75531 ...but removed with: https://reviews.llvm.org/rL159230 llvm-svn: 319327
* [X86][AVX512] Add itinerary argument to all AVX512_maskable_* wrappers. NFCISimon Pilgrim2017-11-291-44/+49
| | | | | | All default to NoItinerary llvm-svn: 319326
* Add opt-viewer testingAdam Nemet2017-11-2915-24/+1186
| | | | | | | | | | | | | | | | | | | | Detects whether we have the Python modules (pygments, yaml) required by opt-viewer and hooks this up to REQUIRES. This fixes https://bugs.llvm.org/show_bug.cgi?id=34129 (the lack of opt-viewer testing). It's also related to https://github.com/apple/swift/pull/12938 and the idea is to expose LLVM_HAVE_OPT_VIEWER_MODULES to the Swift cmake. Differential Revision: https://reviews.llvm.org/D40202 Fixes since the first commit: 1. Disable syntax highlighting as different versions of pygments generate different HTML 2. Use llvm-cxxfilt from the build llvm-svn: 319324
* Reverted r319315 because of unused functions (due to PPR not yet beingSander de Smalen2017-11-295-207/+10
| | | | | | used by any instructions). llvm-svn: 319321
* [X86][AVX512] Tag VPERMILV instruction scheduler classSimon Pilgrim2017-11-292-17/+32
| | | | llvm-svn: 319316
* [AArch64][SVE] Asm: Add SVE predicate register definitions and parsing supportSander de Smalen2017-11-295-10/+207
| | | | | | | | | | | | | | Summary: Patch [1/4] in a series to add parsing of predicates and properly parse SVE ZIP1/ZIP2 instructions. Reviewers: rengolin, kristof.beyls, fhahn, mcrosier, evandro, echristo, efriedma Reviewed By: fhahn Subscribers: aemerson, javed.absar, llvm-commits, tschuett Differential Revision: https://reviews.llvm.org/D40360 llvm-svn: 319315
* [ARM GlobalISel] Fix selecting G_BRCONDDiana Picus2017-11-293-3/+3
| | | | | | | | | | | | | When lowering a G_BRCOND, we generate a TSTri of the condition against 1, which sets the flags, and then a Bcc which branches based on the value of the flags. Unfortunately, we were using the wrong condition code to check whether we need to branch (EQ instead of NE), which caused all our branches to do the opposite of what they were intended to do. This patch fixes the issue by using the correct condition code. llvm-svn: 319313
* [X86][AVX512] Setup unary (PABS/VPLZCNT/VPOPCNT/VPCONFLICT/VMOV*DUP) ↵Simon Pilgrim2017-11-292-55/+84
| | | | | | instruction scheduler classes llvm-svn: 319312
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