| Commit message (Collapse) | Author | Age | Files | Lines |
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and an exception handler. Handle that case.
Also, add an 'Emitted' member to the MCWin64EHUnwindInfo struct. It will be
needed later.
llvm-svn: 131791
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add.with.overflow(X, X)
llvm-svn: 131789
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code. It
is already in GR64 for the same reasons. Since it isn't allocatable it can't cause
any problems.
llvm-svn: 131787
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llvm-svn: 131785
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llvm-svn: 131784
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differ by a dynamic offset, return PartialAlias instead of MayAlias.
See the comment in the code for details. This fixes PR9971.
llvm-svn: 131781
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info in the error message. Per Dan's request.
llvm-svn: 131780
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is needed for an upcoming patch.
llvm-svn: 131772
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RemoveCopyByCommutingDef(). This
actually fixes most of the VerifyCoalescing failures in test-suite.
llvm-svn: 131768
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preparation for reversing StackDirection.
Fixed objects are created in the following order:
1. Incoming arguments passed on stack.
2. va_arg objects (include both arguments that are passed in registers and
pointer to the location of the first va_arg argument).
3. $gp restore slot.
4. Outgoing arguments passed on stack.
5. Pointer to alloca'd space.
llvm-svn: 131767
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llvm-svn: 131765
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llvm-svn: 131764
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llvm-svn: 131763
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llvm-svn: 131760
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passed in register or on the stack.
llvm-svn: 131758
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llvm-svn: 131757
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llvm-svn: 131756
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llvm-svn: 131755
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llvm-svn: 131752
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(this is what used in Android NDK, when architecture is ARMv5)
patch by Koan-Sin Tan
llvm-svn: 131751
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of tBL/tBLX to R_ARM_THM_CALL (ARM ELF 4.7.1.6)
Patch by koan-sin tan.
llvm-svn: 131748
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-strlen should not be called with NULL. Also guarantee that StringRef's Length is 0 if Data is NULL.
-memcmp should not be called with NULL (even if size is 0)
Patch by Matthieu Monrocq!
llvm-svn: 131747
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rdar://problem/8614450
llvm-svn: 131746
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saving and restoring them.
llvm-svn: 131745
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No functionality enabled by default. Use -disable-iv-rewrite.
Extended IVUsers to keep track of the phi that represents the users' IV.
Added the WidenIV transform to replace a narrow IV with a wide IV
by doing a one-for-one replacement of IV users instead of expanding the
SCEV expressions. [sz]exts are removed and truncs are inserted.
llvm-svn: 131744
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super.
llvm-svn: 131743
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optimizations on Win64
llvm-svn: 131740
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llvm-svn: 131739
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There's really nothing to implement. All this really does is swap to a
pseudo-section that later gets written to the unwind info struct. That
needs to be implemented in the object streamers.
llvm-svn: 131734
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llvm-svn: 131730
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llvm-svn: 131724
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preserve
the phikill flag.
llvm-svn: 131717
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llvm-svn: 131716
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with the JALR node. Patch by Sasa Stankovic
llvm-svn: 131714
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llvm-svn: 131711
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This is the first of a series of patches that attempt to simplify handling of
stack frame objects.
llvm-svn: 131710
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llvm-svn: 131709
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llvm-svn: 131708
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similarly for stores. Now "make check" passes with the MachineVerifier forced
on with the VerifyCoalescing option!
llvm-svn: 131705
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llvm-svn: 131689
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foo:
bar = foo
.quad bar
Avoid producing it. Fixes PR9951.
llvm-svn: 131687
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* Remove unnecessary arguments now that ForceExpAbs is a method.
* Use ForceExpAbs in EmitAbsValue.
llvm-svn: 131683
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Fixes rdar://9218925
Fixes PR9601
llvm-svn: 131682
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llvm-svn: 131679
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the root if there is only one such node. This leaves only 2 verifier failures in
the entire test suite when running "make check".
llvm-svn: 131677
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arguments in registers).
llvm-svn: 131676
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text section.
Assume the following bit of annotated assembly:
.section .data.rel.ro,"aw",%progbits
.align 2
.LAlpha:
.long startval(GOTOFF)
.text
.align 2
.type main,%function
.align 4
main: ;;; assume "main" starts at offset 0x20
0x0 push {r11, lr}
0x4 movw r0, :lower16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-4) + 8) = -20
0x8 movt r0, :upper16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-8) + 8) = -16
0xc ... blah
.LBeta:
0x10 add r0, pc, r0
0x14 ... blah
.LGamma:
0x18 add r1, pc, r1
Above snippet results in the following relocs in the .o file for the
first pair of movw/movt instructions
00000024 R_ARM_MOVW_PREL_NC .LAlpha
00000028 R_ARM_MOVT_PREL .LAlpha
And the encoded instructions in the .o file for main: must be
00000020 <main>:
20: e92d4800 push {fp, lr}
24: e30f0fec movw r0, #65516 ; 0xffec i.e. -20
28: e34f0ff0 movt r0, #65520 ; 0xfff0 i.e. -16
However, llc (prior to this commit) generates the following sequence
00000020 <main>:
20: e92d4800 push {fp, lr}
24: e30f0fec movw r0, #65516 ; 0xffec - i.e. -20
28: e34f0fff movt r0, #65535 ; 0xffff - i.e. -1
What has to happen in the ArmAsmBackend is that if the relocation is PC
relative, the 16 bits encoded as part of movw and movt must be both addends,
not addresses. It makes sense to encode addresses by right shifting the value
by 16, but the result is incorrect for PIC.
i.e., the right shift by 16 for movt is ONLY valid for the NON-PCRel case.
This change agrees with what GNU as does, and makes the PIC code run.
MC/ARM/elf-movt.s covers this case.
llvm-svn: 131674
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llvm-svn: 131673
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Fixes PR9934.
We really need to start tblgening the relocation info :-(
llvm-svn: 131669
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llvm-svn: 131668
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