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* Lose the dummiesJakob Stoklund Olesen2010-05-241-22/+0
| | | | llvm-svn: 104564
* Replace the tablegen RegisterClass field SubRegClassList with an alist-like dataJakob Stoklund Olesen2010-05-2413-163/+207
| | | | | | | | | | | structure that represents a mapping without any dependencies on SubRegIndex numbering. This brings us closer to being able to remove the explicit SubRegIndex numbering, and it is now possible to specify any mapping without inventing *_INVALID register classes. llvm-svn: 104563
* Avoid adding duplicate function live-in's.Evan Cheng2010-05-243-2/+21
| | | | llvm-svn: 104560
* Fix an mmx movd encoding.Dan Gohman2010-05-242-4/+36
| | | | llvm-svn: 104552
* MC/X86: Add aliases for CMOVcc variants.Kevin Enderby2010-05-242-0/+143
| | | | llvm-svn: 104549
* Clean up some extra whitespace.Bob Wilson2010-05-241-12/+12
| | | | llvm-svn: 104544
* Thumb2 RSBS instructions were being printed without the 'S' suffix.Bob Wilson2010-05-242-6/+13
| | | | | | | Fix it by changing the T2I_rbin_s_is multiclass to handle the CPSR output and 'S' suffix in the same way as T2I_bin_s_irs. llvm-svn: 104531
* Do not emit line number entries for unknown debug values.Devang Patel2010-05-241-0/+3
| | | | | | This fixes recent regression in store.exp from gdb testsuite. llvm-svn: 104524
* LR is in GPR, not tGPR even in Thumb1 mode.Evan Cheng2010-05-242-4/+3
| | | | llvm-svn: 104518
* Add SubRegIndex defs to PowerPC. It looks like the CR subregister indices areJakob Stoklund Olesen2010-05-241-0/+7
| | | | | | never used. llvm-svn: 104517
* Use SubRegIndex in SystemZ.Jakob Stoklund Olesen2010-05-243-17/+10
| | | | | | Anton, please review the change to SystemZAsmPrinter.cpp. It could be a bug. llvm-svn: 104515
* SubRegIndex'ize MipsJakob Stoklund Olesen2010-05-243-17/+10
| | | | llvm-svn: 104514
* SubRegIndex'ize MSP430Jakob Stoklund Olesen2010-05-241-1/+4
| | | | llvm-svn: 104513
* Fix a few places that depended on the numeric value of subreg indices.Jakob Stoklund Olesen2010-05-243-8/+19
| | | | | | Add assertions in places that depend on consecutive indices. llvm-svn: 104510
* Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enumsJakob Stoklund Olesen2010-05-2410-199/+186
| | | | | | from ARMRegisterInfo.h llvm-svn: 104508
* Rename X86 subregister indices to something shorter.Jakob Stoklund Olesen2010-05-248-106/+96
| | | | | | Use the tablegen-produced enums. llvm-svn: 104493
* Add the SubRegIndex TableGen class.Jakob Stoklund Olesen2010-05-2411-57/+94
| | | | | | | This is the beginning of purely symbolic subregister indices, but we need a bit of jiggling before the explicit numeric indices can be completely removed. llvm-svn: 104492
* Encode the Caml frametable by following what the comment says: the number of ↵Nicolas Geoffray2010-05-241-5/+22
| | | | | | | | descriptors is first emitted, and StackOffsets are emitted in 16 bits. llvm-svn: 104488
* Apply timeouts and memory limits in more places. In particular, whenDuncan Sands2010-05-243-21/+40
| | | | | | | | bugpoint does "Running the code generator to test for a crash" this gets you a crash if llc goes into an infinite loop or uses up vast amounts of memory. llvm-svn: 104485
* llvm-mc: Use EmitIntValue where possible, which makes the API calls from the ↵Daniel Dunbar2010-05-231-3/+6
| | | | | | AsmParser and CodeGen line up better. llvm-svn: 104467
* llvm-mc: Use AddBlankLine in asm parser. This makes transliteration match ↵Daniel Dunbar2010-05-231-0/+9
| | | | | | the input much more closely, and also makes the API calls from the AsmParser and CodeGen line up better. llvm-svn: 104466
* MC: Add an MCLoggingStreamer, for use in debugging integrated-as mismatches.Daniel Dunbar2010-05-235-2/+229
| | | | llvm-svn: 104463
* VDUP doesn't support vectors with 64-bit elements.Bob Wilson2010-05-231-2/+2
| | | | llvm-svn: 104455
* MC/X86: Subdivide immediates a bit more, so that we properly recognize ↵Daniel Dunbar2010-05-224-38/+195
| | | | | | | | | | | immediates based on the width of the target instruction. For example: addw $0xFFFF, %ax should match the same as addw $-1, %ax but we used to match it to the longer encoding. llvm-svn: 104453
* tblgen/AsmMatcher: Change AsmOperandClass to allow a list of superclasses ↵Daniel Dunbar2010-05-223-15/+19
| | | | | | instead of just one. llvm-svn: 104452
* MC/X86: Add alias for setz, setnz, jz, jnz.Daniel Dunbar2010-05-222-1/+22
| | | | llvm-svn: 104435
* Trivial change to dump() function for SparseBitVectorJohn Mosby2010-05-221-6/+10
| | | | llvm-svn: 104433
* Implement @llvm.returnaddress. rdar://8015977.Evan Cheng2010-05-2222-32/+185
| | | | llvm-svn: 104421
* Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit.Jim Grosbach2010-05-228-3/+63
| | | | | | | Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match longjmp. llvm-svn: 104419
* This test is darwin only. Make it so(tm).Eric Christopher2010-05-221-1/+1
| | | | llvm-svn: 104418
* Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented byBob Wilson2010-05-224-31/+119
| | | | | | | | copying VFP subregs. This exposed a bunch of dead code in the *spill-q.ll tests, so I tweaked those tests to keep that code from being optimized away. Radar 7872877. llvm-svn: 104415
* Add full bss data support for darwin tls variables.Eric Christopher2010-05-223-3/+53
| | | | llvm-svn: 104414
* Collect variable information during endFunction() instead of beginFunction().Devang Patel2010-05-221-12/+12
| | | | llvm-svn: 104412
* Add a new section and accessor for TLS data.Eric Christopher2010-05-221-0/+7
| | | | llvm-svn: 104411
* Clean up extra whitespace.Bob Wilson2010-05-211-1/+0
| | | | llvm-svn: 104410
* Make this LookAheadLimit, not the uninitialized LookAheadLeft.Eric Christopher2010-05-211-1/+1
| | | | | | Evan please verify! llvm-svn: 104408
* add a noteChris Lattner2010-05-211-0/+15
| | | | llvm-svn: 104404
* Expand on comment.Eric Christopher2010-05-211-1/+2
| | | | llvm-svn: 104396
* Added retl for 32-bit x86 and added retq for 64-bit x86.Kevin Enderby2010-05-213-0/+12
| | | | llvm-svn: 104394
* Fix comment and whitespace.Eric Christopher2010-05-211-2/+2
| | | | llvm-svn: 104392
* expand on the llvm ir bitcode dox. Patch by Peter Housel!Chris Lattner2010-05-211-7/+339
| | | | llvm-svn: 104391
* Allow machine cse to cse instructions which define physical registers. ↵Evan Cheng2010-05-211-27/+81
| | | | | | Controlled by option -machine-cse-phys-defs. llvm-svn: 104385
* Fix section attribute name.Eric Christopher2010-05-211-1/+1
| | | | llvm-svn: 104381
* Change CodeGen/ARM/2009-11-02-NegativeLane.ll to use 16-bit vector elementsBob Wilson2010-05-212-7/+14
| | | | | | | | so that it will continue to test what it was meant to test when I commit a separate change for better support of BUILD_VECTOR and VECTOR_SHUFFLE for Neon. Fix a DAG combiner crash exposed by this test change. llvm-svn: 104380
* - Change MachineInstr::findRegisterDefOperandIdx so it can also look for defsEvan Cheng2010-05-218-28/+43
| | | | | | | | | | that are aliases of the specified register. - Rename modifiesRegister to definesRegister since it's looking a def of the specific register or one of its super-registers. It's not looking for def of a sub-register or alias that could change the specified register. - Added modifiesRegister to look for defs of aliases. llvm-svn: 104377
* Add MachineInstr::readsWritesVirtualRegister() to determine if an instructionJakob Stoklund Olesen2010-05-212-12/+26
| | | | | | | | | | reads or writes a register. This takes partial redefines and undef uses into account. Don't actually use it yet. That caused miscompiles. llvm-svn: 104372
* SimplifyDevang Patel2010-05-211-44/+23
| | | | llvm-svn: 104338
* Previous commit message should refer to 104308.Dale Johannesen2010-05-211-1/+1
| | | | llvm-svn: 104337
* Fix two bugs in 104348:Dale Johannesen2010-05-211-3/+9
| | | | | | | Case where MMX is disabled wasn't handled right. MMX->MMX bitconverts are Legal. llvm-svn: 104336
* added an assertion to MCObjectWriter::WriteBytes to catch misuse of the ↵Nathan Jeffords2010-05-211-0/+2
| | | | | | | | ZeroFillSize parameter If the size of the string is greater than the zero fill size, the function will attempt to write a very large string of zeros to the object file (~4GB on 32 bit platforms). This assertion will catch the scenario and crash the program before the write occurs. llvm-svn: 104334
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