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* [mips][ias] Correct ELF eflags when Octeon is the target.Daniel Sanders2016-05-125-27/+59
| | | | | | | | | | Reviewers: sdardis Subscribers: petarj, mpf, dsanders, spetrovic, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D18899 llvm-svn: 269283
* [mips][ias] Handle N64 compound relocations and R_MIPS_SUB in ↵Daniel Sanders2016-05-123-15/+51
| | | | | | | | | | | | | | | | | | | needsRelocateWithSymbol() Summary: This eliminates the default case for N64 that was left out of r269047. The change to R_MIPS_SUB is needed in this patch to make this testable since %lo(%neg(%gp_rel(foo))) and %hi(%neg(%gp_rel(foo))) remain the only ways to get a compound relocation from the assembler. Reviewers: sdardis, rafael Subscribers: dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D20097 llvm-svn: 269280
* [WebAssembly] Fast-isel support for calls, arguments, and selects.Dan Gohman2016-05-125-56/+333
| | | | llvm-svn: 269273
* [PowerPC] Fix a DAG replacement bug in PPCTargetLowering::DAGCombineExtBoolTruncHal Finkel2016-05-122-10/+57
| | | | | | | | | | | | | | | While promoting nodes in PPCTargetLowering::DAGCombineExtBoolTrunc, it is possible for one of the nodes to be replaced by another. To make sure we do not visit the deleted nodes, and to make sure we visit the replacement nodes, use a list of HandleSDNodes to track the to-be-promoted nodes during the promotion process. The same fix has been applied to the analogous code in PPCTargetLowering::DAGCombineTruncBoolExt. Fixes PR26985. llvm-svn: 269272
* [SCCP] Resolve shifts beyond the bitwidth to undefDavid Majnemer2016-05-123-0/+115
| | | | | | | | | Shifts beyond the bitwidth are undef but SCCP resolved them to zero. Instead, DTRT and resolve them to undef. This reimplements the transform which caused PR27712. llvm-svn: 269269
* AMDGPU: Fix getIntegerAttribute type and error messageMatt Arsenault2016-05-122-4/+6
| | | | llvm-svn: 269268
* [Layout] Add a new test case for optimal rotationXinliang David Li2016-05-121-0/+43
| | | | | | Enabled by -force-precise-rotation-cost option llvm-svn: 269267
* [Layout] Add a new option (NFC)Xinliang David Li2016-05-121-1/+7
| | | | | | | | | | Currently cost based loop rotation algo can only be turned on with two conditions: the function has real profile data, and -precise-rotation-cost flag is turned on. This is not convenient for developers to experiment when profile is not available. Add a new option to force the new rotation algorithm -force-precise-rotation-cost llvm-svn: 269266
* AMDGPU: Fix breaking IR on instructions with multiple pointer operandsMatt Arsenault2016-05-124-8/+401
| | | | | | | | | | | | | The promote alloca pass would attempt to promote an alloca with a select, icmp, or phi user, even though the other operand was from a non-promotable source, producing a select on two different pointer types. Only do this if we know that both operands derive from the same alloca. In the future we should be able to relax this to an alloca which will also be promoted. llvm-svn: 269265
* [obj2yaml] Adding Error/Expected to macho2yamlChris Bieneman2016-05-123-11/+45
| | | | | | I figure if I'm adding Mach support I may as well use the new fancy Error model. llvm-svn: 269264
* [AArch64] Add support for unscaled narrow stores in getUsefulBitsForUse.Chad Rosier2016-05-122-0/+40
| | | | llvm-svn: 269263
* Appease MSVC with curly bracesSanjoy Das2016-05-121-1/+2
| | | | llvm-svn: 269262
* All llvm.deoptimize declarations must use the same calling conventionSanjoy Das2016-05-1210-53/+108
| | | | | | | | | | | | | | | | | This new verifier rule lets us unambigously pick a calling convention when creating a new declaration for `@llvm.experimental.deoptimize.<ty>`. It is also congruent with our lowering strategy -- since all calls to `@llvm.experimental.deoptimize` are lowered to calls to `__llvm_deoptimize`, it is reasonable to enforce a unique calling convention. Some of the tests that were breaking this verifier rule have had to be split up into different .ll files. The inliner was violating this rule as well, and has been fixed to avoid producing invalid IR. llvm-svn: 269261
* [AArch64] Remove floating-point narrow stores from getUsefulBitsForUse.Chad Rosier2016-05-121-2/+0
| | | | | | | While not impossible, it's unlikely we'd be performing bitwise operations on FP values. llvm-svn: 269260
* SDAG: Implement Select instead of SelectImpl in ARMDAGToDAGISelJustin Bogner2016-05-121-258/+347
| | | | | | | | | | | | This is a large change, but it's pretty mechanical: - Where we were returning a node before, call ReplaceNode instead. - Where we would return null to fall back to another selector, rename the method to try* and return a bool for success. - Where we were calling SelectNodeTo, just return afterwards. Part of llvm.org/pr26808. llvm-svn: 269258
* SDAG: Clean up dangling nodes in ARMISelDAGToDAG::SelectImplJustin Bogner2016-05-121-1/+7
| | | | | | | | | When we convert to the void Select interface, leaving unreferenced nodes around won't be allowed anymore. Part of llvm.org/pr26808. llvm-svn: 269256
* [profile] profile writing cleanupXinliang David Li2016-05-111-34/+16
| | | | | | | | Do not precompute value counts for all sites. This eliminates one more use of dynamic allocation in profiler writer. llvm-svn: 269253
* Revert "[SCCP] Partially propagate informations when the input is not fully ↵Davide Italiano2016-05-112-4/+0
| | | | | | | | defined." This reverts commit r269105 as it caused PR27712. llvm-svn: 269252
* [ThinLTO] Don't re-analyze callee at same threshold unnecessarilyTeresa Johnson2016-05-111-1/+1
| | | | | | | | | This should just be a compile-time change. Correct the check for whether we have already analyzed the callee when making summary based decisions. There is no need to reprocess one at the same threshold as when it was last processed. llvm-svn: 269251
* Fix a bug when hoist spill to a BB with landingpad successor.Wei Mi2016-05-112-6/+72
| | | | | | | | | | | | | | | This is to fix the bug in https://llvm.org/bugs/show_bug.cgi?id=27612. When spill is hoisted to a BB with landingpad successor, and if the VNI of the spill reg lives into the landingpad successor, the spill should be inserted before the call which may throw exception. InsertPointAnalysis is used to compute the safe insert point. http://reviews.llvm.org/D20027 is a preparing patch for this patch. Differential Revision: http://reviews.llvm.org/D19884. llvm-svn: 269249
* [NFC] Extract LastSplitPoint computation from SplitAnalysis to a new classWei Mi2016-05-112-64/+101
| | | | | | | | | | | | InsertPointAnalysis. Because both split and spill hoisting want to use LastSplitPoint computation result, extract the LastSplitPoint computation from SplitAnalysis class which also contains a bunch of other analysises only related to split. Differential Revision: http://reviews.llvm.org/D20027. llvm-svn: 269248
* SDAG: Use ReplaceNode here, not ReplaceUsesJustin Bogner2016-05-111-1/+1
| | | | | | | | | This was a typo in an earlier commit - there's no point in keeping the old node around here. Noticed by Meador Inge. Thanks! llvm-svn: 269245
* Initial add for MachO support for yaml2objChris Bieneman2016-05-114-1/+30
| | | | | | | | Adding the initial files for adding MachO support to yaml2obj. Passing a MachO file will result in an error. I will be implementing obj2yaml and yaml2obj for MachO in parallel so that one can be used to test the other. llvm-svn: 269244
* Initial add for MachO support for obj2yamlChris Bieneman2016-05-116-2/+48
| | | | | | | | Adding the initial files for adding MachO support to obj2yaml. Passing a MachO file will result in a new not_implemented error. I will be implementing obj2yaml and yaml2obj for MachO in parallel so that one can be used to test the other. llvm-svn: 269243
* regenerate checksSanjay Patel2016-05-111-4/+13
| | | | llvm-svn: 269241
* MachineVerifier: Fix error reporting.Matthias Braun2016-05-111-4/+10
| | | | | | | Do not use getVRegDef() to print "the definition" of a vreg. If there are multiple or none the function will fail. llvm-svn: 269239
* cleanup: do not recompute size for preallocated bufferXinliang David Li2016-05-111-2/+5
| | | | llvm-svn: 269238
* SDAG: Add a helper to replace and remove a node during ISelJustin Bogner2016-05-112-7/+8
| | | | | | | | | It's very common to want to replace a node and then remove it since it's dead, especially as we port backends from the SDNode *Select API to the void Select one. This helper makes this sequence a bit less verbose. llvm-svn: 269236
* SDAG: Have SelectNodeTo replace uses if it CSE's instead of morphing a nodeJustin Bogner2016-05-112-9/+8
| | | | | | | | It's awkward to force callers of SelectNodeTo to figure out whether the node was morphed or CSE'd. Update uses here instead of requiring callers to (sometimes) do it. llvm-svn: 269235
* [ThinLTO] Fix Windows debug failure in new iteratorTeresa Johnson2016-05-111-2/+13
| | | | | | | | | | | | This fixes a debug assert on Windows from the new iterator implementation added in r269059. The Windows std::vector iterator operator== checks in debug mode that the containers being iterated over are the same, which they may not be. Fixed by checking that we are iterating over the same container before comparing the container iterators. llvm-svn: 269232
* [AArch64] Improve getUsefulBitsForUse for narrow stores.Chad Rosier2016-05-112-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | For narrow stores (e.g., strb, srth) we know the upper bits of the register are unused/not useful. In some cases we can use this information to eliminate unnecessary instructions. For example, without this patch we generate (from the 2nd test case): ldr w8, [x0] and w8, w8, #0xfff0 bfxil w8, w2, #16, #4 strh w8, [x1] and after the patch the 'and' is removed: ldr w8, [x0] bfxil w8, w2, #16, #4 strh w8, [x1] ret During the lowering of the bitfield insert instruction the 'and' is eliminated because we know the upper 16-bits that are masked off are unused and the lower 4-bits that are masked off are overwritten by the insert itself. Therefore, the 'and' is unnecessary. Differential Revision: http://reviews.llvm.org/D20175 llvm-svn: 269226
* fix documentation comments; NFCSanjay Patel2016-05-111-41/+35
| | | | llvm-svn: 269225
* [ProfileData] Use SoftInstrProfErrors to count soft errors, NFCVedant Kumar2016-05-113-62/+115
| | | | | | Differential Revision: http://reviews.llvm.org/D20082 llvm-svn: 269222
* [X86][AVX512] Fixed VPERMILPD/VPERMILPS shuffle comments.Simon Pilgrim2016-05-113-14/+14
| | | | | | Fixed incorrect operands indices used to access src registers llvm-svn: 269221
* Return a StringRef from getSection.Rafael Espindola2016-05-1110-19/+20
| | | | | | This is similar to how getName is handled. llvm-svn: 269218
* Fix build breakage in DebugInfoCodeviewZachary Turner2016-05-111-1/+1
| | | | llvm-svn: 269217
* Refactor CodeView type records to use common code.Zachary Turner2016-05-1111-728/+1458
| | | | | | | Differential Revision: http://reviews.llvm.org/D20138 Reviewed By: rnk llvm-svn: 269216
* SDAG: Minor cleanup in X86Justin Bogner2016-05-111-7/+6
| | | | | | | | Don't bother returning a result we don't use here. I've also renamed this from selectGather to tryGather to better indicate that it may not do anything. llvm-svn: 269215
* [SCEVExpander] Fix a failed cast<> assertionSanjoy Das2016-05-112-43/+117
| | | | | | | | | SCEVExpander::replaceCongruentIVs assumes the backedge value of an SCEV-analysable PHI to always be an instruction, when this is not necessarily true. For now address this by bailing out of the optimization if the backedge value of the PHI is a non-Instruction. llvm-svn: 269213
* [SCEVExpander] Don't break SSA in replaceCongruentIVsSanjoy Das2016-05-112-2/+42
| | | | | | | | | | | | `SCEVExpander::replaceCongruentIVs` bypasses `hoistIVInc` if both the original and the isomorphic increments are PHI nodes. Doing this can break SSA if the isomorphic increment is not dominated by the original increment. Get rid of the bypass, and let `hoistIVInc` do the right thing. Fixes PR27232 (compile time crash/hang). llvm-svn: 269212
* [SCEV] Be more aggressive around proving no-wrapSanjoy Das2016-05-112-4/+81
| | | | | | | | | | | | | | | ... for AddRec's in loops for which SCEV is unable to compute a max tripcount. This is not a problem for "normal" loops[0] that don't have guards or assumes, but helps in cases where we have guards or assumes in the loop that can be used to constrain incoming values over the backedge. This partially fixes PR27691 (we still don't handle the NUW case). [0]: for "normal" loops, in the cases where we'd be able to prove no-wrap via isKnownPredicate, we'd also be able to compute a max tripcount. llvm-svn: 269211
* [X86][SSE] Avoid repeatedly calling MCInst::getNumOperands(). NFCI.Simon Pilgrim2016-05-111-49/+49
| | | | llvm-svn: 269209
* AMDGPU: Split private memory testsJan Vesely2016-05-113-24/+57
| | | | | | | | | | Reenable R600 testing reviewer: arsenm Differential Revision: http://reviews.llvm.org/D20031 llvm-svn: 269207
* fix typos in comments; NFCSanjay Patel2016-05-111-41/+40
| | | | llvm-svn: 269206
* [NFC] Remove some dead code:Filipe Cabecinhas2016-05-114-24/+0
| | | | | | | DbgInfoIntrinsic::StripCast() is dead since r79977 The only function that creates Comdat objects seems to be in Module, and always creates them using the default constructor. llvm-svn: 269204
* [WebAssembl] Implement enough of fast-isel to run the comparison tests.Dan Gohman2016-05-113-98/+391
| | | | llvm-svn: 269203
* Use an emplace_back for consistency, NFCVedant Kumar2016-05-111-1/+1
| | | | llvm-svn: 269199
* [BasicAA] Compare GEP indices based on value (Fix PR27418)Vedant Kumar2016-05-112-1/+10
| | | | | | | | | | | | Equivalent GEP indices with different types are treated as different indices altogether, leading to an incorrect AA result. Fix the issue by comparing indices based on their values. Thanks to Mikael Holmén for reporting the issue! Differential Revision: http://reviews.llvm.org/D19935 llvm-svn: 269197
* [mips][ias] Work around incorrect microMIPS relocation evaluation exposed by ↵Daniel Sanders2016-05-112-0/+25
| | | | | | | | | | | | | | | r268900 microMIPS has a special case that is not correctly implemented in LLVM. If we have a symbol 'foo' which is equivalent to '.text+0x10'. The value of an R_MICROMIPS_LO16 relocation using 'foo' is 'foo+0x11' and not 'foo+0x10'. The in-place addend should therefore be 0x11. Work around this by partially reverting the effect of r268900 by keeping the symbol when the STO_MIPS_MICROMIPS flag is set. This fixes SingleSource/Regression/C/PR640 for microMIPS. llvm-svn: 269196
* [X86][AVX512] Regenerate intrinsics testSimon Pilgrim2016-05-112-83/+133
| | | | llvm-svn: 269193
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