summaryrefslogtreecommitdiffstats
path: root/llvm
Commit message (Collapse)AuthorAgeFilesLines
* ScalarEvolution: Fix handling of AddRecs in isKnownPredicateJustin Bogner2014-05-232-12/+54
| | | | | | | | | | | | | ScalarEvolution::isKnownPredicate() can wrongly reduce a comparison when both the LHS and RHS are SCEVAddRecExprs. This checks that both LHS and RHS are guarded in the case when both are SCEVAddRecExprs. The test case is against indvars because I could not find a way to directly test SCEV. Patch by Sanjay Patel! llvm-svn: 209487
* [Graph Writer] Limit the length of the graph name because Windows can't ↵Michael J. Spencer2014-05-221-1/+4
| | | | | | | | | | | | | handle it. Windows can't handle paths longer than 260 code points without \\?\. Even with \\?\ it can't handle path components longer than 255 code points. So limit graph names to the arbitrary length of 140. Random characters are still added to the end, so it's ok if graph names collide. Differential Revision: http://reviews.llvm.org/D3883 llvm-svn: 209483
* Make these bool bitfields.Eric Christopher2014-05-221-7/+7
| | | | llvm-svn: 209481
* [RuntimeDyld] Teach RuntimeDyldMachO how to handle scattered VANILLA relocs onLang Hames2014-05-222-9/+61
| | | | | | | | | | | | | | | | | | | | i386. This fixes two more MCJIT regression tests on i386: ExecutionEngine/MCJIT/2003-05-06-LivenessClobber.ll ExecutionEngine/MCJIT/2013-04-04-RelocAddend.ll The implementation of processScatteredVANILLA is tasteless (*ba-dum-ching*), but I'm working on a substantial tidy-up of RuntimeDyldMachO that should improve things. This patch also fixes a type-o in RuntimeDyldMachO::processSECTDIFFRelocation, and teaches that method to skip over the PAIR reloc following the SECTDIFF. <rdar://problem/16961886> llvm-svn: 209478
* Update some AliasAnalysis pass docs for getAdjustedAnalysisPointer.Eric Christopher2014-05-221-0/+14
| | | | | | Patch by George Burgess. llvm-svn: 209467
* R600: Add definition for flat address space ID.Matt Arsenault2014-05-222-4/+5
| | | | | | | | Use 4 since that's probably what it will be for spir. Move ADDRESS_NONE to the end to keep the constant_buffer_* values unchanged, since apparently a bunch of r600 tests use those directly. llvm-svn: 209463
* R600: Try to convert BFE back to standard bit ops when possible.Matt Arsenault2014-05-225-11/+297
| | | | | | | This allows existing DAG combines to work on them, and then we can re-match to BFE if necessary during instruction selection. llvm-svn: 209462
* R600: Add dag combine for BFEMatt Arsenault2014-05-226-2/+829
| | | | llvm-svn: 209461
* R600: Implement ComputeNumSignBitsForTargetNode for BFEMatt Arsenault2014-05-223-0/+45
| | | | llvm-svn: 209460
* R600: Implement computeMaskedBitsForTargetNode for BFEMatt Arsenault2014-05-221-1/+29
| | | | llvm-svn: 209459
* R600: Expand mul24 for GPUs without itMatt Arsenault2014-05-226-16/+35
| | | | llvm-svn: 209458
* R600: Expand mad24 for GPUs without itMatt Arsenault2014-05-226-1/+38
| | | | llvm-svn: 209457
* R600: Add intrinsics for mad24Matt Arsenault2014-05-229-3/+67
| | | | llvm-svn: 209456
* Return false if we're not going to do anything.Eric Christopher2014-05-221-1/+1
| | | | llvm-svn: 209455
* R600/SI: Move instruction pattern to instruction definitionMatt Arsenault2014-05-221-6/+3
| | | | llvm-svn: 209454
* Remove LLVMContextImpl::optimizationRemarkEnabledFor.Diego Novillo2014-05-225-105/+75
| | | | | | | | | | | | | | | | Summary: This patch moves the handling of -pass-remarks* over to lib/DiagnosticInfo.cpp. This allows the removal of the optimizationRemarkEnabledFor functions from LLVMContextImpl, as they're not needed anymore. Reviewers: qcolombet Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D3878 llvm-svn: 209453
* [X86] Improve the lowering of BITCAST from MVT::f64 to MVT::v4i16/MVT::v8i8.Andrea Di Biagio2014-05-224-100/+195
| | | | | | | | | | | | | This patch teaches the x86 backend how to efficiently lower ISD::BITCAST dag nodes from MVT::f64 to MVT::v4i16 (and vice versa), and from MVT::f64 to MVT::v8i8 (and vice versa). This patch extends the logic from revision 208107 to also handle MVT::v4i16 and MVT::v8i8. Also, this patch correctly propagates Undef values when performing the widening of a vector (example: when widening from v2i32 to v4i32, the upper 64bits of the resulting vector are 'undef'). llvm-svn: 209451
* ARM64: remove '#' from annotation of add/sub immediateTim Northover2014-05-221-1/+1
| | | | | | | The full string used to be "// =#12" for example, which looks too busy. llvm-svn: 209443
* Add support for missed and analysis optimization remarks.Diego Novillo2014-05-2212-92/+387
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This adds two new diagnostics: -pass-remarks-missed and -pass-remarks-analysis. They take the same values as -pass-remarks but are intended to be triggered in different contexts. -pass-remarks-missed is used by LLVMContext::emitOptimizationRemarkMissed, which passes call when they tried to apply a transformation but couldn't. -pass-remarks-analysis is used by LLVMContext::emitOptimizationRemarkAnalysis, which passes call when they want to inform the user about analysis results. The patch also: 1- Adds support in the inliner for the two new remarks and a test case. 2- Moves emitOptimizationRemark* functions to the llvm namespace. 3- Adds an LLVMContext argument instead of making them member functions of LLVMContext. Reviewers: qcolombet Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D3682 llvm-svn: 209442
* Segmented stacks: omit __morestack call when there's no frame.Tim Northover2014-05-225-18/+77
| | | | | | Patch by Florian Zeitz llvm-svn: 209436
* ARM64: these work tooTim Northover2014-05-221-2/+0
| | | | llvm-svn: 209430
* Yes they doTim Northover2014-05-221-1/+0
| | | | llvm-svn: 209429
* ARM64: model pre/post-indexed operations properly.Tim Northover2014-05-229-336/+241
| | | | | | | | | | We should be keeping track of the writeback on these instructions, otherwise we're relying on LLVM's stupidity for correct code. Fortunately, the MC layer can now handle all required constraints, which means we can get rid of the CodeGen only PseudoInsts too. llvm-svn: 209426
* ARM64: separate load/store operands to simplify assemblerTim Northover2014-05-2215-2702/+2537
| | | | | | | | | | | | | | | | | | | This changes ARM64 to use separate operands for each component of an address, and look for separate '[', '$Rn, ..., ']' tokens when parsing. This allows us to do away with quite a bit of special C++ code to handle monolithic "addressing modes" in the MC components. The more incremental matching of the assembler operands also allows for better diagnostics when LLVM is presented with invalid input. Most of the complexity here is with the register-offset instructions, which were extremely dodgy beforehand: even when the instruction used wM, LLVM's model had xM as an operand. We papered over this discrepancy before, but that approach doesn't work now so I split them into separate X and W variants. llvm-svn: 209425
* [mips] Make unalignedload.ll test stricter and easier to modify for ↵Daniel Sanders2014-05-221-12/+29
| | | | | | | | | | | | | | | | | | | | | | MIPS32r6/MIPS64r6 Summary: * Split into two functions, one to test each struct. * R0 and R2 must be defined by an lw with a %got reference to the correct symbol. * Test for $4 (first argument) where appropriate instead of accepting any register. * Test that the two lbu's are correctly combined into $4 Depends on D3844 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3845 llvm-svn: 209424
* [mips] Change lwl and lwr in inlineasm_constraint.ll to lwDaniel Sanders2014-05-221-3/+3
| | | | | | | | | | | | | | | | | Summary: lwl and lwr are not available in MIPS32r6/MIPS64r6. The purpose of the test is to check that the '$1' expands to '0($x)' rather than to test something related to the lwl or lwr instructions so we can simply switch to lw. Depends on D3842 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3844 llvm-svn: 209423
* [mips] Use addiu in inline assembly tests since addi is not available in all ↵Daniel Sanders2014-05-2210-42/+42
| | | | | | | | | | | | | | | | | | | | | ISA's Summary: This patch is necessary so that they do not fail on MIPS32r6/MIPS64r6 when -integrated-as is enabled by default and we correctly detect the host CPU. No functional change since these tests are testing the behaviour of the constraint used for the third operand rather than the mnemonic. Depends on D3842 Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3843 llvm-svn: 209421
* Extend sys::getHostCPUFeatures to work on AArch64 platformsBradley Smith2014-05-221-1/+37
| | | | llvm-svn: 209420
* [mips][mips64r6] addi is not available on MIPS32r6/MIPS64r6Daniel Sanders2014-05-224-2/+30
| | | | | | | | | | | | Summary: Depends on D3787. Tablegen will raise an assertion without it. Reviewers: zoran.jovanovic, jkolek, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3842 llvm-svn: 209419
* [mips][mips64r6] Test that paired single instructions are invalidDaniel Sanders2014-05-222-1/+44
| | | | | | | | | | | | | | Summary: These emit the 'unknown instruction' instead of the correct error because they have not been implemented in LLVM for any MIPS ISA. Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3841 llvm-svn: 209418
* [mips][mips64r6] Add b[on]vcDaniel Sanders2014-05-2210-53/+683
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This required me to implement the disassembler for MIPS64r6 since the encodings are ambiguous with other instructions. This in turn revealed a few assembly/disassembly bugs which I have fixed. * da[ht]i only take two operands according to the spec, not three. * DecodeBranchTarget2[16] correctly handles wider immediates than simm16 * Also made non-functional change to DecodeBranchTarget and DecodeBranchTargetMM to keep implementation style consistent between them. * Difficult encodings are handled by a custom decode method on the most general encoding in the group. This method will convert the MCInst to a different opcode if necessary. DecodeBranchTarget is not currently the inverse of getBranchTargetOpValue so disassembling some branch instructions emit incorrect output. This seems to affect branches with delay slots on all MIPS ISA's. I've left this bug for now and temporarily removed the check for the immediate on bc[12]eqz/bc[12]nez in the MIPS32r6/MIPS64r6 tests. jialc and jic crash the disassembler for some reason. I've left these instructions commented out for the moment. Depends on D3760 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3761 llvm-svn: 209415
* ARM64: assert if we see i64 -> i64 extend in the DAG.Tim Northover2014-05-221-4/+2
| | | | | | | | Should be no change in behaviour, but it makes the intended functionality a bit clearer and means we only have to reason about real extend operations. llvm-svn: 209409
* AArch64/ARM64: enable more AArch64 tests.Tim Northover2014-05-223-6/+9
| | | | llvm-svn: 209408
* MC: initialise MCAsmParser variableSaleem Abdulrasool2014-05-221-2/+2
| | | | | | | Properly initialise HadError to false during construction. Detected as use-of-uninitialised variable by MSan! llvm-svn: 209393
* Remove unused variable.Eric Christopher2014-05-221-1/+0
| | | | llvm-svn: 209391
* ARM: introduce llvm.arm.undefined intrinsicSaleem Abdulrasool2014-05-225-5/+24
| | | | | | | | | | | | This intrinsic permits the emission of platform specific undefined sequences. ARM has reserved the 0xde opcode which takes a single integer parameter (ignored by the CPU). This permits the operating system to implement custom behaviour on this trap. The llvm.arm.undefined intrinsic is meant to provide a means for generating the target specific behaviour from the frontend. This is particularly useful for Windows on ARM which has made use of a series of these special opcodes. llvm-svn: 209390
* R600/SI: Match fp_to_uint / uint_to_fp for f64Matt Arsenault2014-05-223-2/+25
| | | | llvm-svn: 209388
* MC: formalise some assertions into proper errorsSaleem Abdulrasool2014-05-228-8/+61
| | | | | | | | | Now that clang can be used as an assembler via the IAS, invalid assembler inputs would cause the assertions to trigger. Although we cannot recover from the errors here, nor provide caret diagnostics, attempt to handle them slightly more gracefully by reporting a fatal error. llvm-svn: 209387
* Override runOnMachineFunction for ARMISelDAGToDAG so that we canEric Christopher2014-05-221-0/+7
| | | | | | reset the subtarget on each function. llvm-svn: 209386
* Override runOnMachineFunction for X86ISelDAGToDAG so that we canEric Christopher2014-05-221-0/+7
| | | | | | reset the subtarget on each function. llvm-svn: 209384
* Avoid using subtarget features when adding X86 specific passes toEric Christopher2014-05-225-14/+17
| | | | | | the pass pipeline. llvm-svn: 209382
* Remove extra local variable.Eric Christopher2014-05-221-2/+1
| | | | llvm-svn: 209381
* Rename createGlobalBaseRegPass -> createX86GlobalBaseRegPass to makeEric Christopher2014-05-223-4/+4
| | | | | | it obvious that it's a target specific pass. llvm-svn: 209380
* Fix typo.Eric Christopher2014-05-225-5/+5
| | | | llvm-svn: 209377
* Avoid using subtarget features when initializing the pass pipelineEric Christopher2014-05-222-12/+17
| | | | | | on PPC. llvm-svn: 209376
* Reset the subtarget for DAGToDAG on every iteration of runOnMachineFunction.Eric Christopher2014-05-225-47/+47
| | | | | | | This required updating the generated functions and TD file accordingly to be pointers rather than const references. llvm-svn: 209375
* Reset the subtarget for DAGToDAG on every iteration of runOnMachineFunction.Eric Christopher2014-05-221-1/+2
| | | | llvm-svn: 209374
* Sort includes.Eric Christopher2014-05-221-1/+1
| | | | llvm-svn: 209373
* DebugInfo: Simplify dead variable collection slightly.David Blaikie2014-05-221-3/+1
| | | | | | | | constructSubprogramDIE was already called for every subprogram in every CU when the module was started - there's no need to call it again at module finalization. llvm-svn: 209372
* Fix a bug in SCEV's backedge taken count computation from my prior fix in Jan.Andrew Trick2014-05-222-8/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This has to do with the trip count computation for loops with multiple exits, which is quite subtle. Most passes just ask for a single trip count number, so we must be conservative assuming any exit could be taken. Normally, we rely on the "exact" trip count, which was correctly given as "unknown". However, SCEV also gives a "max" back-edge taken count. The loops max BE taken count is conservatively a maximum over the max of each exit's non-exiting iterations count. Note that some exit tests can be skipped so the max loop back-edge taken count can actually exceed the max non-exiting iterations for some exits. However, when we know the loop *latch* cannot be skipped, we can directly use its max taken count disregarding other exits. I previously took the minimum here without checking whether the other exit could be skipped. The correct, and simpler thing to do here is just to directly use the loop latch's max non-exiting iterations as the loops max back-edge count. In the problematic test case, the first loop exit had a max of zero non-exiting iterations, but could be skipped. The loop latch was known not to be skipped but had max of one non-exiting iteration. We incorrectly claimed the loop back-edge could be taken zero times, when it is actually taken one time. Fixes Loop %for.body.i: <multiple exits> Unpredictable backedge-taken count. Loop %for.body.i: max backedge-taken count is 1. llvm-svn: 209358
OpenPOWER on IntegriCloud