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* ELFRelocationEntry::operator<(): Try to stabilize the order. r_offset was ↵NAKAMURA Takumi2013-05-151-1/+8
| | | | | | | | | | | | | | | insufficient to sort Relocs. It should fix llvm/test/CodeGen/ARM/ehabi-mc-compact-pr*.ll on some hosts. RELOCATION RECORDS FOR [.ARM.exidx]: 0 R_ARM_PREL31 .text 0 R_ARM_NONE __aeabi_unwind_cpp_pr0 FIXME: I am not sure of the directions of extra comparators, in Type and Index. For now, they are different from the direction in r_offset. llvm-svn: 181864
* LoopVectorize: Fix commentsArnold Schwaighofer2013-05-151-4/+4
| | | | | | No functionality change. llvm-svn: 181862
* LoopVectorize: Hoist conditional loads if possibleArnold Schwaighofer2013-05-152-3/+171
| | | | | | | | | | | | InstCombine can be uncooperative to vectorization and sink loads into conditional blocks. This prevents vectorization. Undo this optimization if there are unconditional memory accesses to the same addresses in the loop. radar://13815763 llvm-svn: 181860
* Speed up Value::isUsedInBasicBlock() for long use lists.Jakob Stoklund Olesen2013-05-141-14/+13
| | | | | | | | | | | | | | | | This is expanding Ben's original heuristic for short basic blocks to also work for longer basic blocks and huge use lists. Scan the basic block and the use list in parallel, terminating the search when the shorter list ends. In almost all cases, either the basic block or the use list is short, and the function returns quickly. In one crazy test case with very long use chains, CodeGenPrepare runs 400x faster. When compiling ARMDisassembler.cpp it is 5x faster. <rdar://problem/13840497> llvm-svn: 181851
* Fix two typoSylvestre Ledru2013-05-142-2/+2
| | | | llvm-svn: 181848
* ExceptionDemo: Corresponding to r181820, SectionMemoryManager should belong ↵NAKAMURA Takumi2013-05-141-2/+2
| | | | | | to RTDyldMemoryManager. llvm-svn: 181844
* Object: Fix Mach-O relocation printing.Ahmed Bougacha2013-05-142-2/+38
| | | | | | | | | There were two problems that made llvm-objdump -r crash: - for non-scattered relocations, the symbol/section index is actually in the (aptly named) symbolnum field. - sections are 1-indexed. llvm-svn: 181843
* ARM ISel: Don't create illegal types during LowerMULArnold Schwaighofer2013-05-142-25/+56
| | | | | | | | | | | | | | | | | The transformation happening here is that we want to turn a "mul(ext(X), ext(X))" into a "vmull(X, X)", stripping off the extension. We have to make sure that X still has a valid vector type - possibly recreate an extension to a smaller type. In case of a extload of a memory type smaller than 64 bit we used create a ext(load()). The problem with doing this - instead of recreating an extload - is that an illegal type is exposed. This patch fixes this by creating extloads instead of ext(load()) sequences. Fixes PR15970. radar://13871383 llvm-svn: 181842
* GlobalOpt: fix an issue where CXAAtExitFn points to a deleted function.Manman Ren2013-05-142-3/+9
| | | | | | | | | | | CXAAtExitFn was set outside a loop and before optimizations where functions can be deleted. This patch will set CXAAtExitFn inside the loop and after optimizations. Seg fault when running LTO because of accesses to a deleted function. rdar://problem/13838828 llvm-svn: 181838
* Revert previous patch, it's actually on under Wall.Eric Christopher2013-05-141-2/+1
| | | | llvm-svn: 181837
* Add -Wreorder to the list of C++ warnings.Eric Christopher2013-05-141-1/+2
| | | | | | | This built clean with clang, but if we see false positives on the bots then we'll revert and turn it into a compiler specific check. llvm-svn: 181836
* Make getCompileUnit non-const and return the current DIE if itEric Christopher2013-05-142-3/+3
| | | | | | | happens to be a compile unit. Noticed on inspection and tested via calling on a newly created compile unit. No functional change. llvm-svn: 181835
* Add 'CHECK-DAG' supportMichael Liao2013-05-144-23/+306
| | | | | | Refer to 'FileCheck.rst'f for details of 'CHECK-DAG'. llvm-svn: 181827
* Refactor string checking. No functionality change.Michael Liao2013-05-141-62/+94
| | | | llvm-svn: 181824
* Implement the PowerPC system call (sc) instruction.Bill Schmidt2013-05-145-1/+30
| | | | | | Instruction added at request of Roman Divacky. Tested via asm-parser. llvm-svn: 181821
* SectionMemoryManager shouldn't be a JITMemoryManager. Previously, the Filip Pizlo2013-05-147-74/+57
| | | | | | | | | | | | | | | | | EngineBuilder interface required a JITMemoryManager even if it was being used to construct an MCJIT. But the MCJIT actually wants a RTDyldMemoryManager. Consequently, the SectionMemoryManager, which is meant for MCJIT, derived from the JITMemoryManager and then stubbed out a bunch of JITMemoryManager methods that weren't relevant to the MCJIT. This patch fixes the situation: it teaches the EngineBuilder that RTDyldMemoryManager is a supertype of JITMemoryManager, and that it's appropriate to pass a RTDyldMemoryManager instead of a JITMemoryManager if we're using the MCJIT. This allows us to remove the stub methods from SectionMemoryManager, and make SectionMemoryManager a direct subtype of RTDyldMemoryManager. llvm-svn: 181820
* Hexagon: Pass to replace tranfer/copy instructions into combine instructionJyotsna Verma2013-05-147-6/+724
| | | | | | where possible. llvm-svn: 181817
* Reapply "Subtract isn't commutative, fix this for MMX psub." withEric Christopher2013-05-142-7/+220
| | | | | | | a somewhat randomly chosen cpu that will minimize cpu specific differences on bots. llvm-svn: 181814
* Temporarily revert "Subtract isn't commutative, fix this for MMX psub."Eric Christopher2013-05-142-220/+7
| | | | | | It's causing failures on the atom bot. llvm-svn: 181812
* Fix __clear_cache declaration.Rafael Espindola2013-05-141-1/+1
| | | | | | This fixes the build with gcc in gnu++98 and gnu++11 mode. llvm-svn: 181811
* Subtract isn't commutative, fix this for MMX psub.Eric Christopher2013-05-142-7/+220
| | | | | | Patch by Andrea DiBiagio. llvm-svn: 181809
* Recognize sparc64 as an alias for sparcv9 triples.Jakob Stoklund Olesen2013-05-142-3/+3
| | | | | | Patch by Brad Smith! llvm-svn: 181808
* Hexagon: Add patterns to generate 'combine' instructions.Jyotsna Verma2013-05-142-0/+167
| | | | llvm-svn: 181805
* Hexagon: ArePredicatesComplement should not restrict itself to TFRs.Jyotsna Verma2013-05-142-5/+63
| | | | llvm-svn: 181803
* Add bitcast to store of personality function.Kai Nacke2013-05-141-1/+3
| | | | | | | | | | The personality function is user defined and may have an arbitrary result type. The code assumes always i8*. This results in an assertion failure if a different type is used. A bitcast to i8* is added to prevent this failure. Reviewed by: Renato Golin, Bob Wilson llvm-svn: 181802
* Fix ARM FastISel tests, as a first step to enabling ARM FastISelDerek Schuff2013-05-1418-168/+143
| | | | | | | | | | | | | | | | | | | | | ARM FastISel is currently only enabled for iOS non-Thumb1, and I'm working on enabling it for other targets. As a first step I've fixed some of the tests. Changes to ARM FastISel tests: - Different triples don't generate the same relocations (especially movw/movt versus constant pool loads). Use a regex to allow either. - Mangling is different. Use a regex to allow either. - The reserved registers are sometimes different, so registers get allocated in a different order. Capture the names only where this occurs. - Add -verify-machineinstrs to some tests where it works. It doesn't work everywhere it should yet. - Add -fast-isel-abort to many tests that didn't have it before. - Split out the VarArg test from fast-isel-call.ll into its own test. This simplifies test setup because of --check-prefix. Patch by JF Bastien llvm-svn: 181801
* PPC32: Fix stack collision between FP and CR save areas.Bill Schmidt2013-05-142-4/+9
| | | | | | | | | | | | | | | | | The changes to CR spill handling missed a case for 32-bit PowerPC. The code in PPCFrameLowering::processFunctionBeforeFrameFinalized() checks whether CR spill has occurred using a flag in the function info. This flag is only set by storeRegToStackSlot and loadRegFromStackSlot. spillCalleeSavedRegisters does not call storeRegToStackSlot, but instead produces MI directly. Thus we don't see the CR is spilled when assigning frame offsets, and the CR spill ends up colliding with some other location (generally the FP slot). This patch sets the flag in spillCalleeSavedRegisters for PPC32 so that the CR spill is properly detected and gets its own slot in the stack frame. llvm-svn: 181800
* Hexagon: Test case to check if branch probabilities are properly reflected inJyotsna Verma2013-05-141-0/+79
| | | | | | the jump instructions in the form of taken/not-taken hint. llvm-svn: 181799
* Hexagon: Remove dead-code after unconditional return from addPreSched2.Jyotsna Verma2013-05-141-3/+0
| | | | llvm-svn: 181797
* R600/SI: Add processor type for Hainan asicTom Stellard2013-05-142-1/+3
| | | | | | | | | | Patch by: Alex Deucher Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> NOTE: This is a candidate for the 3.3 branch. llvm-svn: 181792
* Get the unittests compiling when building with cmake and the settingDuncan Sands2013-05-142-1/+6
| | | | | | -DLLVM_ENABLE_THREADS=false. llvm-svn: 181788
* Declare __clear_cache.Rafael Espindola2013-05-141-0/+1
| | | | | | | | GCC declares __clear_cache in the gnu modes (-std=gnu++98, -std=gnu++11), but not in the strict modes (-std=c++98, -std=c++11). This patch declares it and therefore fixes the build when using one of the strict modes. llvm-svn: 181785
* [SystemZ] Add disassembler supportRichard Sandiford2013-05-14353-7/+7189
| | | | llvm-svn: 181777
* R600/SI: Add lit test coverage for the remaining patterns added recentlyMichel Danzer2013-05-146-11/+111
| | | | | Reviewed-by: Christian König <christian.koenig@amd.com> llvm-svn: 181775
* [SystemZ] Add extra testscases for r181773Richard Sandiford2013-05-1424-0/+384
| | | | | | Forgot to svn add these... llvm-svn: 181774
* [SystemZ] Rework handling of constant PC-relative operandsRichard Sandiford2013-05-1431-130/+425
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GNU assembler treats things like: brasl %r14, 100 in the same way as: brasl %r14, .+100 rather than as a branch to absolute address 100. We implemented this in LLVM by creating an immediate operand rather than the usual expr operand, and by handling immediate operands specially in the code emitter. This was undesirable for (at least) three reasons: - the specialness of immediate operands was exposed to the backend MC code, rather than being limited to the assembler parser. - in disassembly, an immediate operand really is an absolute address. (Note that this means reassembling printed disassembly can't recreate the original code.) - it would interfere with any assembly manipulation that we might try in future. E.g. operations like branch shortening can change the relative position of instructions, but any code that updates sym+offset addresses wouldn't update an immediate "100" operand in the same way as an explicit ".+100" operand. This patch changes the implementation so that the assembler creates a "." label for immediate PC-relative operands, so that the operand to the MCInst is always the absolute address. The patch also adds some error checking of the offset. llvm-svn: 181773
* [SystemZ] Remove bogus isAsmParserOnlyRichard Sandiford2013-05-141-28/+22
| | | | | | | | | | Marking instructions as isAsmParserOnly stops them from being disassembled. However, in cases where separate asm and codegen versions exist, we actually want to disassemble to the asm ones. No functional change intended. llvm-svn: 181772
* [SystemZ] Match operands to fields by name rather than by orderRichard Sandiford2013-05-143-57/+79
| | | | | | | | | | | | | | | | | | | | | | | | The SystemZ port currently relies on the order of the instruction operands matching the order of the instruction field lists. This isn't desirable for disassembly, where the two are matched only by name. E.g. the R1 and R2 fields of an RR instruction should have corresponding R1 and R2 operands. The main complication is that addresses are compound operands, and as far as I know there is no mechanism to allow individual suboperands to be selected by name in "let Inst{...} = ..." assignments. Luckily it doesn't really matter though. The SystemZ instruction encoding groups all address fields together in a predictable order, so it's just as valid to see the entire compound address operand as a single field. That's the approach taken in this patch. Matching by name in turn means that the operands to COPY SIGN and CONVERT TO FIXED instructions can be given in natural order. (It was easier to do this at the same time as the rename, since otherwise the intermediate step was too confusing.) No functional change intended. llvm-svn: 181771
* [SystemZ] Match operands to fields by name rather than by orderRichard Sandiford2013-05-145-312/+326
| | | | | | | | | | | | | | | | | | | | | | | | The SystemZ port currently relies on the order of the instruction operands matching the order of the instruction field lists. This isn't desirable for disassembly, where the two are matched only by name. E.g. the R1 and R2 fields of an RR instruction should have corresponding R1 and R2 operands. The main complication is that addresses are compound operands, and as far as I know there is no mechanism to allow individual suboperands to be selected by name in "let Inst{...} = ..." assignments. Luckily it doesn't really matter though. The SystemZ instruction encoding groups all address fields together in a predictable order, so it's just as valid to see the entire compound address operand as a single field. That's the approach taken in this patch. Matching by name in turn means that the operands to COPY SIGN and CONVERT TO FIXED instructions can be given in natural order. (It was easier to do this at the same time as the rename, since otherwise the intermediate step was too confusing.) No functional change intended. llvm-svn: 181769
* Removed trailing whitespace.Michael Gottesman2013-05-141-4/+4
| | | | llvm-svn: 181760
* Fix typo.Reed Kotler2013-05-141-1/+1
| | | | llvm-svn: 181759
* Removed an unnamed namespace and forgot to make two of the functions insideReed Kotler2013-05-141-3/+5
| | | | | | "static". llvm-svn: 181754
* This is the first of three patches which creates stubs used forReed Kotler2013-05-142-0/+1303
| | | | | | | | | | | | | | | | | | | | | | | Mips16/32 floating point interoperability. When Mips16 code calls external functions that would normally have some of its parameters or return values passed in floating point registers, it needs (Mips32) helper functions to do this because while in Mips16 mode there is no ability to access the floating point registers. In Pic mode, this is done with a set of predefined functions in libc. This case is already handled in llvm for Mips16. In static relocation mode, for efficiency reasons, the compiler generates stubs that the linker will use if it turns out that the external function is a Mips32 function. (If it's Mips16, then it does not need the helper stubs). These stubs are identically named and the linker knows about these tricks and will not create multiple copies and will delete them if they are not needed. llvm-svn: 181753
* StackColoring: don't clear an instruction's mem operand if the underlyingAkira Hatanaka2013-05-142-0/+44
| | | | | | | object is a PseudoSourceValue and PseudoSourceValue::isConstant returns true (i.e., points to memory that has a constant value). llvm-svn: 181751
* Assert that DIEEntries are constructed with non-null DIEsDavid Blaikie2013-05-141-1/+3
| | | | | | | This just brings a crash a little further forward from DWARF emission to DIE construction to make errors easier to diagnose. llvm-svn: 181748
* LoopVectorize: Handle loops with multiple forward inductionsArnold Schwaighofer2013-05-142-17/+70
| | | | | | | | | | | | We used to give up if we saw two integer inductions. After this patch, we base further induction variables on the chosen one like we do in the reverse induction and pointer induction case. Fixes PR15720. radar://13851975 llvm-svn: 181746
* [objc-arc-opts] Added debug statements when we set and unset whether a ↵Michael Gottesman2013-05-141-0/+2
| | | | | | pointer is known positive. llvm-svn: 181745
* [objc-arc-opts] In the presense of an alloca unconditionally remove RR pairs ↵Michael Gottesman2013-05-132-5/+294
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | if and only if we are both KnownSafeBU/KnownSafeTD rather than just either or. In the presense of a block being initialized, the frontend will emit the objc_retain on the original pointer and the release on the pointer loaded from the alloca. The optimizer will through the provenance analysis realize that the two are related (albiet different), but since we only require KnownSafe in one direction, will match the inner retain on the original pointer with the guard release on the original pointer. This is fixed by ensuring that in the presense of allocas we only unconditionally remove pointers if both our retain and our release are KnownSafe (i.e. we are KnownSafe in both directions) since we must deal with the possibility that the frontend will emit what (to the optimizer) appears to be unbalanced retain/releases. An example of the miscompile is: %A = alloca retain(%x) retain(%x) <--- Inner Retain store %x, %A %y = load %A ... DO STUFF ... release(%y) call void @use(%x) release(%x) <--- Guarding Release getting optimized to: %A = alloca retain(%x) store %x, %A %y = load %A ... DO STUFF ... release(%y) call void @use(%x) rdar://13750319 llvm-svn: 181743
* Move a couple more statistics inside '#ifndef NDEBUG'.Matt Beaumont-Gay2013-05-131-1/+1
| | | | | | Suppresses an unused-variable warning in -Asserts builds. llvm-svn: 181733
* Mips assembler: Assembler macro ADDIU $rs,immJack Carter2013-05-132-1/+4
| | | | | | | | | | | | | | This patch adds alias for addiu instruction which enables following syntax: addiu $rs,imm The macro is translated as: addiu $rs,$rs,imm Contributer: Vladimir Medic llvm-svn: 181729
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