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* [RewriteStatepointsForGC] Missed review comment from 234651 & build fixPhilip Reames2015-04-101-3/+4
| | | | | | After submitting 234651, I noticed I hadn't responded to a review comment by mjacob. This patch addresses that comment and fixes a Release only build problem due to an unused variable. llvm-svn: 234653
* [RewriteStatepointsForGC] Preprocess the IR to remove unreachable blocks and ↵Philip Reames2015-04-102-6/+99
| | | | | | | | | | | | | | | single entry phis Two related small changes: Various dominance based queries about liveness can get confused if we're talking about unreachable blocks. To avoid reasoning about such cases, just remove them before rewriting statepoints. Remove single entry phis (likely left behind by LCSSA) to reduce the number of live values. Both of these are motivated by http://reviews.llvm.org/D8674 which will be submitted shortly. Differential Revision: http://reviews.llvm.org/D8675 llvm-svn: 234651
* [RewriteStatepointsForGC] Limited support for vectors of pointersPhilip Reames2015-04-102-25/+311
| | | | | | | | | | | | This patch adds limited support for inserting explicit relocations when there's a vector of pointers live over the statepoint. This doesn't handle the case where the vector contains a mix of base and non-base pointers; that's future work. The current implementation just scalarizes the vector over the gc.statepoint before doing the explicit rewrite. An alternate approach would be to plumb the vector all the way though the backend lowering, but doing that appears challenging. In particular, the size of the indirect spill slot is currently assumed to be sizeof(pointer) throughout the backend. In practice, this is enough to allow running the SLP and Loop vectorizers before RewriteStatepointsForGC. Differential Revision: http://reviews.llvm.org/D8671 llvm-svn: 234647
* [InstCombine][CodeGenPrep] Create llvm.uadd.with.overflow in CGP.Sanjoy Das2015-04-106-101/+199
| | | | | | | | | | | | | | | | | | | Summary: This change moves creating calls to `llvm.uadd.with.overflow` from InstCombine to CodeGenPrep. Combining overflow check patterns into calls to the said intrinsic in InstCombine inhibits optimization because it introduces an intrinsic call that not all other transforms and analyses understand. Depends on D8888. Reviewers: majnemer, atrick Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8889 llvm-svn: 234638
* Avoid spewing binary to stdout in some filetype=obj testsReid Kleckner2015-04-101-10/+10
| | | | llvm-svn: 234627
* use update_llc_test_checks.py to tighten checkingSanjay Patel2015-04-101-94/+103
| | | | | | | | test features, not CPUs remove unnecessary cruft llvm-svn: 234622
* Remember if lseek works in this FD.Rafael Espindola2015-04-102-1/+6
| | | | | | It will be used in clang in a sec. llvm-svn: 234619
* DebugInfo: Stop leaking temporaries in DIBuilder::createCompileUnit()Duncan P. N. Exon Smith2015-04-102-14/+15
| | | | | | | | | | | Stop leaking temporary nodes from `DIBuilder::createCompileUnit()`. `replaceAllUsesWith()` doesn't delete the nodes, so we need to delete them "manually" (well, `TempMDTuple` does that for us). Similarly, stop leaking the temporary nodes used for variables of subprograms. llvm-svn: 234617
* Have one raw_fd_ostream constructor forward to the other.Rafael Espindola2015-04-101-24/+18
| | | | | | | This fixes some odd behavior differences between the two. In particular, the version that takes a FD no longer unconditionally sets stdout to binary. llvm-svn: 234615
* [FS] Report errors from llvm::sys::fs::rename on WindowsReid Kleckner2015-04-101-0/+1
| | | | | | | | | | Previously we would always report success, which is pretty bogus. I'm too lazy to write a test where rename will portably fail on all platforms. I'm just trying to fix breakage introduced by r234597, which happened to tickle this. llvm-svn: 234611
* [WinEH] Try to make outlining invokes work a little betterReid Kleckner2015-04-103-2/+96
| | | | | | | | WinEH currently turns invokes into calls. Long term, we will reconsider this, but for now, make sure we remap the operands and clone the successors of the new terminator. llvm-svn: 234608
* [CallSite] Use the injected base class name. NFC.Benjamin Kramer2015-04-101-14/+10
| | | | llvm-svn: 234606
* [PowerPC] Prefetching should also consider depth > 1 loopsHal Finkel2015-04-102-2/+71
| | | | | | | Iterating over loops from the LoopInfo instance only provides top-level loops. We need to search the whole tree of loops to find the inner ones. llvm-svn: 234603
* [CallSite] Make construction from Value* (or Instruction*) explicit.Benjamin Kramer2015-04-1017-33/+34
| | | | | | | | | | | | | | | | | | | CallSite roughly behaves as a common base CallInst and InvokeInst. Bring the behavior closer to that model by making upcasts explicit. Downcasts remain implicit and work as before. Following dyn_cast as a mental model checking whether a Value *V isa CallSite now looks like this: if (auto CS = CallSite(V)) // think dyn_cast instead of: if (CallSite CS = V) This is an extra token but I think it is slightly clearer. Making the ctor explicit has the advantage of not accidentally creating nullptr CallSites, e.g. when you pass a Value * to a function taking a CallSite argument. llvm-svn: 234601
* [mips] [IAS] Improve comments in MipsAsmParser::expandLoadImm. NFC.Toma Tabacu2015-04-101-7/+5
| | | | llvm-svn: 234595
* [AArch64] Changes some SchedAlias to WriteRes for Cortex-A57.Chad Rosier2015-04-101-3/+8
| | | | | | | | | | | | Using SchedAliases is convenient and works well for latency and resource lookup for instructions. However, this creates an entry in AArch64WriteLatencyTable with a WriteResourceID of 0, breaking any SchedReadAdvance since the lookup will fail. http://reviews.llvm.org/D8043 Patch by Dave Estes <cestes@codeaurora.org>! llvm-svn: 234594
* [AArch64] Adjusts Cortex-A57 machine model to handle zero shift.Chad Rosier2015-04-101-0/+9
| | | | | | | http://reviews.llvm.org/D8043 Patch by Dave Estes <cestes@codeaurora.org>! llvm-svn: 234593
* Microoptimize DenseMap::clear.Benjamin Kramer2015-04-101-3/+5
| | | | | | | | Cache NumEntries locally, it's only used in an assert and using the member variable prevents the compiler from eliminating the tombstone check for types with trivial destructors. No functionality change intended. llvm-svn: 234589
* Reduce dyn_cast<> to isa<> or cast<> where possible.Benjamin Kramer2015-04-1022-64/+60
| | | | | | No functional change intended. llvm-svn: 234586
* [mips] [IAS] Make the mips-expansions-bad.s test more readable. NFC.Toma Tabacu2015-04-101-3/+5
| | | | | | | Move the check lines below the code lines and change the indentation from 8 spaces to 2 spaces. llvm-svn: 234584
* [lib/Fuzzer] Section: How good is my fuzzer?Kostya Serebryany2015-04-101-0/+15
| | | | llvm-svn: 234571
* [lib/Fuzzer] explain compatibility with AFLKostya Serebryany2015-04-101-0/+10
| | | | llvm-svn: 234570
* Divergence analysis for GPU programsJingyue Wu2015-04-1014-1/+642
| | | | | | | | | | | | | | | | | | | Summary: Some optimizations such as jump threading and loop unswitching can negatively affect performance when applied to divergent branches. The divergence analysis added in this patch conservatively estimates which branches in a GPU program can diverge. This information can then help LLVM to run certain optimizations selectively. Test Plan: test/Analysis/DivergenceAnalysis/NVPTX/diverge.ll Reviewers: resistor, hfinkel, eliben, meheff, jholewinski Subscribers: broune, bjarke.roune, madhur13490, tstellarAMD, dberlin, echristo, jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D8576 llvm-svn: 234567
* [WinEHPrepare] Don't rely on the order of IRDavid Majnemer2015-04-103-7/+19
| | | | | | | | | | The IPToState table must be emitted after we have generated labels for all functions in the table. Don't rely on the order of the list of globals. Instead, utilize WinEHFuncInfo to tell us how many catch handlers we expect to outline. Once we know we've visited all the catch handlers, emit the cppxdata. llvm-svn: 234566
* [PowerPC] Don't crash on PPC32 i64 fp_to_uint on modern coresHal Finkel2015-04-102-0/+24
| | | | | | | | | | When we have an instruction for this (and, thus, don't generate a runtime call), we need to custom type legalize this (in a trivial way, just as we do for fp_to_sint). Fixes PR23173. llvm-svn: 234561
* [AArch64] Promote f16 operations to f32.Ahmed Bougacha2015-04-104-120/+867
| | | | | | | | | | | | | | | | | | | | For the most common ones (such as fadd), we already did the promotion. Do the same thing for all the others. Currently, we'll just crash/assert on all these operations, as there's no hardware or libcall support whatsoever. f16 (half) is specified as an interchange - not arithmetic - format, and is expected to be promoted to single-precision for arithmetic operations. While there, teach the legalizer about promoting some of the (mostly floating-point) operations that we never needed before. Differential Revision: http://reviews.llvm.org/D8648 See related discussion on the thread for: http://reviews.llvm.org/D8755 llvm-svn: 234550
* Add LLVM support for remaining integer divide and permute instructions from ↵Nemanja Ivanovic2015-04-0911-61/+291
| | | | | | | | | | | ISA 2.06 This is the patch corresponding to review: http://reviews.llvm.org/D8406 It adds some missing instructions from ISA 2.06 to the PPC back end. llvm-svn: 234546
* Simplify use of formatted_raw_ostream.Rafael Espindola2015-04-0913-98/+78
| | | | | | | | | | | | | | | formatted_raw_ostream is a wrapper over another stream to add column and line number tracking. It is used only for asm printing. This patch moves the its creation down to where we know we are printing assembly. This has the following advantages: * Simpler lifetime management: std::unique_ptr * We don't compute column and line number of object files :-) llvm-svn: 234535
* [CodeGen] Combine concat_vector of trunc'd scalar to scalar_to_vector.Ahmed Bougacha2015-04-093-3/+33
| | | | | | | | | | | | | | We already do: concat_vectors(scalar, undef) -> scalar_to_vector(scalar) When the scalar is legal. When it's not, but is a truncated legal scalar, we can also do: concat_vectors(trunc(scalar), undef) -> scalar_to_vector(scalar) Which is equivalent, since the upper lanes are undef anyway. While there, teach the combine to look at more than 2 operands. Differential Revision: http://reviews.llvm.org/D8883 llvm-svn: 234530
* [AArch64][FastISel] Fix integer extend optimization.Juergen Ributzka2015-04-092-5/+25
| | | | | | | | | | | | | | The integer extend optimization tries to fold the extend into the load instruction. This requires us to identify if the extend has already been emitted or not and act accordingly on it. The check that was originally performed for this was not sufficient. Besides checking the ValueMap for a mapped register we also need to check if the virtual register has already an associated machine instruction that defines it. This fixes rdar://problem/20470788. llvm-svn: 234529
* Remove duplicated code and consolidate initializers.Eric Christopher2015-04-092-15/+5
| | | | llvm-svn: 234525
* clang-format bits of code to make a followup patch easy to read.Rafael Espindola2015-04-0911-26/+16
| | | | llvm-svn: 234519
* Revert "Refactoring and enhancement to FMA combine."Rafael Espindola2015-04-093-522/+181
| | | | | | This reverts commit r234513. It was failing on the bots. llvm-svn: 234518
* Define a function with "... llvm::func...".Rafael Espindola2015-04-091-6/+5
| | | | | | | | | | | | Using this instead of namespace llvm { func... } Has the advantage that the build fails with a compiler error if it gets out of sync with the .h file. llvm-svn: 234515
* Refactoring and enhancement to FMA combine.Olivier Sallenave2015-04-093-181/+522
| | | | llvm-svn: 234513
* IR: Preserve use-list order by default in bitcodeDuncan P. N. Exon Smith2015-04-091-3/+3
| | | | | | | Pull the `-preserve-*-use-list-order` flags out of "experimental" mode, and preserve use-list order by default when serializing to bitcode. llvm-svn: 234510
* Use a raw_svector_ostream instead of a raw_string_ostream.Rafael Espindola2015-04-091-6/+8
| | | | | | It saves a bit of copying. llvm-svn: 234507
* Don't repeat name in comment. NFC.Rafael Espindola2015-04-094-24/+22
| | | | llvm-svn: 234506
* [NFC] add more comments for SLSRJingyue Wu2015-04-091-0/+5
| | | | llvm-svn: 234505
* Misc cleanup. NFC.Rafael Espindola2015-04-092-7/+7
| | | | | | These were lost when I reverted the raw_ostream changes. llvm-svn: 234504
* clang-format. NFC.Rafael Espindola2015-04-091-2/+2
| | | | llvm-svn: 234502
* clang-format this constructor.Rafael Espindola2015-04-091-8/+4
| | | | llvm-svn: 234501
* Don't repeat names in comments.Rafael Espindola2015-04-091-30/+25
| | | | llvm-svn: 234498
* Use implicit calls to parent constructor. NFC.Rafael Espindola2015-04-091-3/+3
| | | | llvm-svn: 234497
* This reverts commit r234460 and r234461.Rafael Espindola2015-04-0914-86/+51
| | | | | | | | | Revert "Add classof implementations to the raw_ostream classes." Revert "Use the cast machinery to remove dummy uses of formatted_raw_ostream." The underlying issue can be fixed without classof. llvm-svn: 234495
* [ARM] support for Cortex-R4/R4FJaved Absar2015-04-095-12/+81
| | | | | | | | | Currently, llvm (backend) doesn't know cortex-r4, even though it is the default target for armv7r. Using "--target=armv7r-arm-none-eabi" provokes 'cortex-r4' is not a recognized processor for this target' by llvm. This patch adds support for cortex-r4 and, very closely related, r4f. llvm-svn: 234486
* Nothing inherits from the asm streamer.Rafael Espindola2015-04-091-3/+1
| | | | | | Make that explicit and remove protected: llvm-svn: 234484
* [mips] Refactor saved-registers bitmask creation in ↵Toma Tabacu2015-04-091-20/+11
| | | | | | | | | | | | | | | | | | | MipsAsmPrinter::printSavedRegsBitmask. NFC. Summary: Make the code more readable by fusing the for-loops together and explicitly checking for each register class. Also, this version is more straightforward because it doesn't assume that FPU registers always come before CPU registers in the CalleeSavedInfo vector. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8033 llvm-svn: 234475
* [AArch64] Add support for dynamic stack alignmentKristof Beyls2015-04-095-43/+663
| | | | | | Differential Revision: http://reviews.llvm.org/D8876 llvm-svn: 234471
* [AArch64] Remove redundant -march option. Also fix a think-o from r234462.Lang Hames2015-04-092-2/+2
| | | | llvm-svn: 234467
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