| Commit message (Collapse) | Author | Age | Files | Lines |
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llvm-svn: 129040
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llvm-svn: 129039
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folded comparisons, just like ADD and SUB.
llvm-svn: 129038
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llvm-svn: 129036
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values also.
llvm-svn: 129035
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llvm-svn: 129034
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The ARM disassembler should reject invalid (type, align) encodings as invalid instructions.
So, instead of:
Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------
vst2.32 {d0, d2}, [r3, :256], r3
we now have:
Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------
mc-input.txt:1:1: warning: invalid instruction encoding
0xb3 0x9 0x3 0xf4
^
llvm-svn: 129033
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llvm-svn: 129032
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blocks with interference.
llvm-svn: 129030
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Without any positive bias, there is nothing for the spill placer to to. It will
spill everywhere.
llvm-svn: 129029
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llvm-svn: 129028
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Since these "Advanced SIMD and VFP" instructions have more specfic encoding bits
specified, if coproc == 10 or 11, we should reject the insn as invalid.
rdar://problem/9239922
rdar://problem/9239596
llvm-svn: 129027
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llvm-svn: 129025
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llvm-svn: 129024
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If there are no positive nodes, the algorithm can be aborted early.
llvm-svn: 129021
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addConstraints, and finish.
This will allow us to abort the algorithm early if it is determined to be futile.
llvm-svn: 129020
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llvm-svn: 129019
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Also set the encoding bits (for A8.6.303, A8.6.328, A8.6.329) Inst{3-0} = 0b0000,
in class NVLaneOp.
rdar://problem/9240648
llvm-svn: 129015
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llvm-svn: 129012
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Change the test to force a sign extension and expose the problem again.
llvm-svn: 129011
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Keep track of llvm.dbg.value intrinsics with non null values.
llvm-svn: 129010
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This takes the linking of libxul on linux from 6m54.931s to 5m39.840s.
llvm-svn: 129009
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llvm-svn: 129008
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llvm-svn: 129006
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llvm-svn: 129002
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test fail (without the fix). Thanks Dan.
llvm-svn: 128999
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llvm-svn: 128997
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llvm-svn: 128996
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DenseMap.
llvm-svn: 128994
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improvements are welcome, please commit any changes directly to SVN.
llvm-svn: 128992
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llvm-svn: 128990
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llvm-svn: 128988
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llvm-svn: 128986
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About 90% of the relevant blocks are live-through without uses, and the only
information required about them is their number. This saves memory and enables
later optimizations that need to look at only the use-blocks.
llvm-svn: 128985
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Add more complete sanity check for LdStFrm instructions where if IBit (Inst{25})
is 1, Inst{4} should be 0. Otherwise, we should reject the insn as invalid.
rdar://problem/9239347
rdar://problem/9239467
llvm-svn: 128977
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llvm-svn: 128974
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Start teaching the runtime Dyld interface to use the memory manager API
for allocating space. Rather than mapping directly into the MachO object,
we extract the payload for each object and copy it into a dedicated buffer
allocated via the memory manager. For now, just do Segment64, so this works
on x86_64, but not yet on ARM.
llvm-svn: 128973
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llvm-svn: 128970
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llvm-svn: 128969
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llvm-svn: 128968
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imp-def of CPSR it was adding.
llvm-svn: 128965
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llvm-svn: 128964
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llvm-svn: 128963
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llvm-svn: 128962
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Treat the landing pad as a normal successor when that happens.
llvm-svn: 128961
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llvm-svn: 128959
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illegal register
encodings for DisassembleArithMiscFrm().
rdar://problem/9238659
llvm-svn: 128958
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llvm-svn: 128955
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it already is.
llvm-svn: 128954
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llvm-svn: 128953
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