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* t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to ↵Evan Cheng2010-05-193-6/+41
| | | | | | hoist more loads during machine LICM. llvm-svn: 104115
* Use 'adr' for LEApcrel and LEApcrel. Mark LEApcrel re-materializable.Evan Cheng2010-05-191-12/+4
| | | | llvm-svn: 104114
* Update autoconf/automake versions in the documentation to match the versions ↵Tobias Grosser2010-05-191-2/+2
| | | | | | used in Autogen.sh llvm-svn: 104113
* MC/X86: Lower MOV{8,16,32,64}{rm,mr} to fixed-register forms, as appropriate.Daniel Dunbar2010-05-191-9/+50
| | | | llvm-svn: 104112
* Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These ↵Evan Cheng2010-05-195-35/+37
| | | | | | do not have other un-modeled side effects. llvm-svn: 104111
* Target instruction selection should copy memoperands.Evan Cheng2010-05-191-3/+11
| | | | llvm-svn: 104110
* MC/X86: Strip spurious operands from CALL64r as we do for CALL64pcrel32, toDaniel Dunbar2010-05-191-6/+8
| | | | | | avoid same prefix byte problem as in r104062. llvm-svn: 104108
* Mark a few more pattern-less instructions with neverHasSideEffects. This is ↵Evan Cheng2010-05-193-0/+12
| | | | | | especially important on instructions like t2LEApcreal which are prime candidate for machine LICM. llvm-svn: 104102
* Add a comment explaining why this code uses Append mode.Dan Gohman2010-05-191-0/+4
| | | | llvm-svn: 104095
* Intrinsics which do a vector compare (results are all zero or all ones) are ↵Evan Cheng2010-05-192-6/+88
| | | | | | | | | | modeled as icmp / fcmp + sext. This is turned into a vsetcc by dag combine (yes, not a good long term solution). The targets can then isel the vsetcc to the appropriate instruction. The trouble arises when the result of a vector cmp + sext is then and'ed with all ones. Instcombine will turn it into a vector cmp + zext, dag combiner will miss turning it into a vsetcc and hell breaks loose after that. Teach dag combine to turn a vector cpm + zest into a vsetcc + and 1. This fixes rdar://7923010. llvm-svn: 104094
* Factor out the code for picking integer arithmetic with immediateDan Gohman2010-05-191-15/+32
| | | | | | | opcodes into a helper function. This fixes a few places in the code which were not properly selecting the 8-bit-immediate opcodes. llvm-svn: 104091
* Add a test to make sure that we're lowering the shift amount correctly.Eric Christopher2010-05-191-0/+22
| | | | llvm-svn: 104090
* Add a comment.Dan Gohman2010-05-181-0/+1
| | | | llvm-svn: 104089
* Fix the predicate which checks for non-sensical formulae which haveDan Gohman2010-05-181-4/+5
| | | | | | constants in registers which partially cancel out their immediate fields. llvm-svn: 104088
* Factor out the code for recomputing an LSRUse's Regs set after someDan Gohman2010-05-181-17/+40
| | | | | | | of its formulae have been removed into a helper function, and also teach it how to update the RegUseTracker. llvm-svn: 104087
* Fix a crash when debugging the coalescer. DebugValue instructions are notBob Wilson2010-05-181-4/+13
| | | | | | in the coalescer's instruction map. llvm-svn: 104086
* Factor out code for estimating search space complexity into a helperDan Gohman2010-05-181-22/+26
| | | | | | function. llvm-svn: 104082
* Add some more debug output.Dan Gohman2010-05-181-0/+1
| | | | llvm-svn: 104080
* Factor out the code for deleting a formula from an LSRUse intoDan Gohman2010-05-181-4/+9
| | | | | | a helper function. llvm-svn: 104079
* Make some debug output more informative.Dan Gohman2010-05-181-2/+3
| | | | llvm-svn: 104078
* Print an error message in Formula::print if the HasBaseReg flagDan Gohman2010-05-181-0/+7
| | | | | | | is inconsistent with the BaseRegs field. It's not print's job to assert on an invalid condition, but it can make one more obvious. llvm-svn: 104077
* Rename RegUseTracker's RegUses member to RegUsesMap to avoidDan Gohman2010-05-181-7/+7
| | | | | | confusion with LSRInstance's RegUses member. llvm-svn: 104076
* Remember to update VirtRegLastUse when spilling without killing before a call.Jakob Stoklund Olesen2010-05-182-0/+47
| | | | llvm-svn: 104074
* Teach mode load folding and unfolding code about CMP32ri8 and friends.Dan Gohman2010-05-181-3/+9
| | | | llvm-svn: 104068
* Don't eliminate frame pointers from leaf functions if "--disable-fp-elim" isBill Wendling2010-05-181-1/+1
| | | | | | specified. llvm-svn: 104066
* When converting a test to a cmp to fold a load, use the cmp that has anDan Gohman2010-05-182-3/+71
| | | | | | 8-bit immediate field rather than one with a wider immediate field. llvm-svn: 104064
* Quick test to make sure we're emitting the tbss section correctly.Eric Christopher2010-05-181-0/+114
| | | | llvm-svn: 104063
* make mcinstlower remove all but the first operand to CALL64pcrel32.Chris Lattner2010-05-181-1/+11
| | | | | | | | | | | | The register use operands (e.g. the first argument is passed in a register) is currently being modeled as a normal register use, instead of correctly being an implicit use. This causes the operand to get propagated onto the mcinst, which was causing the encoder to emit a rex prefix byte, which generates an invalid call. This fixes rdar://7998435 llvm-svn: 104062
* Sink dag combine's post index load / store code that swap base ptr and index ↵Evan Cheng2010-05-183-5/+40
| | | | | | into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649 llvm-svn: 104060
* Implement EmitTBSSSymbol for MachOStreamer.Eric Christopher2010-05-181-5/+7
| | | | | | Fixes build failure as well. llvm-svn: 104059
* Fix enum to address array bounds regression.mike-m2010-05-181-1/+1
| | | | llvm-svn: 104058
* Make EmitTBSSSymbol take a section argument so that we can find it later.Eric Christopher2010-05-184-11/+18
| | | | | | Fix up callers and users. llvm-svn: 104057
* Properly handle multiple definitions of a virtual register in the sameJakob Stoklund Olesen2010-05-181-21/+41
| | | | | | | | | | | | | | | instruction. This can happen on ARM: >> %reg1035:5<def>, %reg1035:6<def> = VLD1q16 %reg1028, 0, pred:14, pred:%reg0 Regs: Q0=%reg1032* R0=%reg1028* R1=%reg1029* R2 R3=%reg1031* Killing last use: %reg1028 Allocating %reg1035 from QPR Assigning %reg1035 to Q1 << %D2<def>, %D3<def> = VLD1q16 %R0<kill>, 0, pred:14, pred:%reg0, %Q1<imp-def> llvm-svn: 104056
* Test passed on ppc, to my surprise; if it workedDale Johannesen2010-05-181-2/+0
| | | | | | there it may work everywhere... llvm-svn: 104053
* Continuously refine the register class of REG_SEQUENCE def with all the ↵Evan Cheng2010-05-181-2/+3
| | | | | | source registers and sub-register indices. llvm-svn: 104051
* Fix PR7162: Use source register classes and sub-indices to determine the ↵Evan Cheng2010-05-182-4/+44
| | | | | | correct register class of the definitions of REG_SEQUENCE. llvm-svn: 104050
* Testcase for llvm-gcc checkin 104042.Dale Johannesen2010-05-181-0/+19
| | | | llvm-svn: 104043
* Incorporate Daniel's suggestion and use !isdigit(CurPtr[0]) and notKevin Enderby2010-05-181-1/+1
| | | | | | | CurPtr[0] == '\n' when testing the character after a "0b" when looking to see if it part of a something like "jmp 0b". llvm-svn: 104039
* Fixed the problem with a branch to "0b" that was not parsed by llvm-mcKevin Enderby2010-05-182-13/+15
| | | | | | | correctly. The Lexer was incorrectly eating the newline casusing it to branch to address 0. Updated the test case to use a "0:" label and a branch to "0b". llvm-svn: 104038
* Teach the machine code verifier to use getSubRegisterRegClass().Jakob Stoklund Olesen2010-05-181-2/+5
| | | | | | The old approach was wrong. It had an off-by-one error. llvm-svn: 104034
* MC/Mach-O: Implement support for setting indirect symbol table offset in ↵Daniel Dunbar2010-05-183-3/+203
| | | | | | | | section header. Also, create symbol data for LHS of assignment, to match 'as' symbol ordering better. llvm-svn: 104033
* MC/Mach-O: Remove some FIXMEs.Daniel Dunbar2010-05-181-7/+3
| | | | llvm-svn: 104032
* MC/Mach-O: Fail faster/harder when we see .file, which isn't yet supported.Daniel Dunbar2010-05-181-2/+2
| | | | llvm-svn: 104031
* MC/X86: Implement custom lowering to make sure we match things likeDaniel Dunbar2010-05-182-0/+94
| | | | | | | | X86::ADC32ri $0, %eax to X86::ADC32i32 $0 llvm-svn: 104030
* llc (et al): Add support for --show-encoding and --show-inst.Daniel Dunbar2010-05-181-1/+13
| | | | llvm-svn: 104029
* Usage of O_NONBLOCK in bjam is now confirmed as a bug and fixed upstream.Dan Gohman2010-05-181-4/+7
| | | | | | Update the comment. llvm-svn: 104021
* Simplify MCContext::(Next|Get)InstanceBenjamin Kramer2010-05-181-24/+8
| | | | | | | - Allocate MCLabels in the context so they don't leak. - Avoid duplicated densemap lookup. llvm-svn: 104020
* Replace FIRST_* and LAST_* macros with a generic STMT_RANGE macroAlexis Hunt2010-05-181-20/+27
| | | | | | Also rename ABSTRACT to ABSTRACT_STMT llvm-svn: 104018
* FIX PR7158. SimplifyVBinOp was asserting when it fails to constant fold (op ↵Evan Cheng2010-05-182-7/+25
| | | | | | (build_vector), (build_vector)). llvm-svn: 104004
* ARMBaseRegisterInfo::estimateRSStackSizeLimit() could return prematurely with aJakob Stoklund Olesen2010-05-171-16/+17
| | | | | | | | | | | | | | | too large limit. The function would return immediately when finding an addrmode 3/5 instruction. It needs to keep scanning in case there is an addrmode 6 instruction which drops the limit to 0. A test case is very difficult to produce because it will only fail when the scavenger is used. rdar://problem/7894847 llvm-svn: 103995
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