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* Use VLD1 in NEON extenting-load patterns instead of VLDR.Tim Northover2012-04-262-58/+65
| | | | | | | On some cores it's a bad idea for performance to mix VFP and NEON instructions and since these patterns are NEON anyway, the NEON load should be used. llvm-svn: 155630
* Test commit.Tim Northover2012-04-261-2/+0
| | | | llvm-svn: 155626
* Enable detection of AVX and AVX2 support through CPUID. Add AVX/AVX2 to ↵Craig Topper2012-04-262-13/+9
| | | | | | corei7-avx, core-avx-i, and core-avx2 cpu names. llvm-svn: 155618
* Teach the reassociate pass to fold chains of multiplies with repeatedChandler Carruth2012-04-262-10/+346
| | | | | | | | | | | | | | | | | elements to minimize the number of multiplies required to compute the final result. This uses a heuristic to attempt to form near-optimal binary exponentiation-style multiply chains. While there are some cases it misses, it seems to at least a decent job on a very diverse range of inputs. Initial benchmarks show no interesting regressions, and an 8% improvement on SPASS. Let me know if any other interesting results (in either direction) crop up! Credit to Richard Smith for the core algorithm, and helping code the patch itself. llvm-svn: 155616
* Specify cpu to unbreak tests.Evan Cheng2012-04-2616-17/+17
| | | | llvm-svn: 155604
* If triple is armv7 / thumbv7 and a CPU is specified, do not automatically assumeEvan Cheng2012-04-264-14/+30
| | | | | | | | | | the feature set of v7a. This comes about if the user specifies something like -arch armv7 -mcpu=cortex-m3. We shouldn't be generating instructions such as uxtab in this case. rdar://11318438 llvm-svn: 155601
* Don't forget to reset 'first operand' flag when we're setting the ↵Bill Wendling2012-04-261-5/+8
| | | | | | MDNodeOperand value. llvm-svn: 155599
* Try to fix llvm-arm-linux builder with -mcpu.Jakob Stoklund Olesen2012-04-251-1/+1
| | | | llvm-svn: 155589
* Trivial change to make the test use -mcpu=generic so as to avoidPreston Gurd2012-04-251-1/+1
| | | | | | a failure if run on an Intel Atom with post RA instruction scheduling. llvm-svn: 155587
* Reapply the SmallMap patch with a fix.Benjamin Kramer2012-04-255-0/+1124
| | | | | | Comparing ~0UL with an unsigned will always return false when long is 64 bits long. llvm-svn: 155568
* Print IV chain numbers while collecting them.Jakob Stoklund Olesen2012-04-251-4/+5
| | | | llvm-svn: 155567
* Remove more dead code.Jakob Stoklund Olesen2012-04-253-24/+0
| | | | llvm-svn: 155566
* Unify internal representation of ARM instructions with a register ↵Richard Barton2012-04-252-4/+10
| | | | | | right-shifted by #32. These are stored as shifts by #0 in the MCInst and correctly marshalled when transforming from or to assembly representation. llvm-svn: 155565
* Revert "First implementation of:"Eric Christopher2012-04-255-1124/+0
| | | | | | | | This reverts commit 76271a3366731d4c372fdebcd8d3437e6e09a61b. as it's breaking the bots. llvm-svn: 155562
* First implementation of:Stepan Dyatkovskiy2012-04-255-0/+1124
| | | | | | | | | | | - FlatArrayMap. Very simple map container that uses flat array inside. - MultiImplMap. Map container interface, that has two modes, one for small amount of elements and one for big amount. - SmallMap. SmallMap is DenseMap compatible MultiImplMap. It uses FlatArrayMap for small mode, and DenseMap for big mode. Also added unittests for new classes and update for ProgrammersManual. For more details about new classes see ProgrammersManual and comments in sourcecode. llvm-svn: 155557
* Simplify LiveIntervals::getApproximateInstructionCount().Jakob Stoklund Olesen2012-04-251-2/+1
| | | | | | | This function is only used for a heuristic during -join-physregs. It doesn't need floating point. llvm-svn: 155554
* Remove a dead function.Jakob Stoklund Olesen2012-04-251-6/+0
| | | | llvm-svn: 155553
* Remove the -disable-cross-class-join option.Jakob Stoklund Olesen2012-04-251-13/+4
| | | | | | | | Cross-class joins have been normal and fully supported for a while now. With TableGen generating the getMatchingSuperRegClass() hook, they are unlikely to cause problems again. llvm-svn: 155552
* Cross-class joining is winning.Jakob Stoklund Olesen2012-04-251-66/+0
| | | | | | | | | | | | Remove the heuristic for disabling cross-class joins. The greedy register allocator can handle the narrow register classes, and when it splits a live range, it can pick a larger register class. Benchmarks were unaffected by this change. <rdar://problem/11302212> llvm-svn: 155551
* Add ifdef around getSubtargetFeatureName in tablegen output file so that ↵Craig Topper2012-04-252-3/+8
| | | | | | only targets that want the function get it. This prevents other targets from getting an unused function warning. llvm-svn: 155538
* Use vector_shuffles instead of target specific unpack nodes for AVX ↵Craig Topper2012-04-251-18/+20
| | | | | | ZERO_EXTEND/ANY_EXTEND combine. These will be converted to target specific nodes during lowering. This is more consistent with other code. llvm-svn: 155537
* openbsd doesn't support soname, patch by Brad Smith!Chris Lattner2012-04-251-0/+3
| | | | llvm-svn: 155536
* Actually delete now-empty file.Chandler Carruth2012-04-251-0/+0
| | | | llvm-svn: 155532
* Reverting r155468. Chris and Chandler have convinced me that it's dangerous andLang Hames2012-04-252-103/+0
| | | | | | | | in poor taste. Talking through some alternate solutions with Chandler. llvm-svn: 155530
* Do not use $gp as a dedicated global register if the target ABI is not O32. Akira Hatanaka2012-04-253-7/+8
| | | | llvm-svn: 155522
* typo in declaration from earlier todayAndrew Trick2012-04-251-1/+1
| | | | llvm-svn: 155519
* Simplify the known retain count tracking; use a boolean state insteadDan Gohman2012-04-251-41/+34
| | | | | | | of a precise count. Also, move RRInfo's Partial field into PtrState, now that it won't increase the size. llvm-svn: 155513
* Build custom predecessor and successor lists for each basic block.Dan Gohman2012-04-241-115/+101
| | | | | | | | These lists exclude invoke unwind edges and loop backedges which are being ignored. This makes it easier to ignore them consistently. llvm-svn: 155500
* ARM: improved assembler diagnostics for missing CPU features.Jim Grosbach2012-04-245-35/+83
| | | | | | | | | | | When an instruction match is found, but the subtarget features it requires are not available (missing floating point unit, or thumb vs arm mode, for example), issue a diagnostic that identifies what the feature mismatch is. rdar://11257547 llvm-svn: 155499
* Fix a naughty header include that breaks "installed" builds.Andrew Trick2012-04-242-6/+16
| | | | llvm-svn: 155486
* ConstantFoldSelectInstruction swapped the operands of the select.Nadav Rotem2012-04-242-1/+14
| | | | | | Fix 12592. Patch by Matt Pharr. llvm-svn: 155480
* Fix the testcase. We do expect two vblendw on XMMs.Nadav Rotem2012-04-241-5/+6
| | | | llvm-svn: 155477
* Add a testcase for 155440Nadav Rotem2012-04-241-0/+13
| | | | llvm-svn: 155475
* MachineBasicBlock::SplitCriticalEdge() should follow LLVM IR variant and ↵Evan Cheng2012-04-242-0/+76
| | | | | | refuse to break edge to EH landing pad. rdar://11300144 llvm-svn: 155470
* Add support for llvm.arm.neon.vmull* intrinsics to InstCombine. This fixesLang Hames2012-04-242-0/+103
| | | | | | <rdar://problem/11291436>. llvm-svn: 155468
* Fix a crash on valid (if UB) bitcode that is produced for some globalChandler Carruth2012-04-242-3/+16
| | | | | | | | | | | | | | | | | | | | | constants in C++11 mode. I have no idea why it required such particular circumstances to get here, the code seems clearly to rely upon unchecked assumptions. Specifically, when we decide to form an index into a struct type, we may have gone through (at least one) zero-length array indexing round, which would have left the offset un-adjusted, and thus not necessarily valid for use when indexing the struct type. This is just an canonicalization step, so the correct thing is to refuse to canonicalize nonsensical GEPs of this form. Implemented, and test case added. Fixes PR12642. Pair debugged and coded with Richard Smith. =] I credit him with most of the debugging, and preventing me from writing the wrong code. llvm-svn: 155466
* ARM: Nuke remnant bogus code.Jim Grosbach2012-04-241-2/+0
| | | | | | | | r154362 was supposed to delete this bit, but obviously didn't. rdar://11305594 llvm-svn: 155465
* Related to PR1255. Let's begin. I'll commit classes that corresponds to our ↵Stepan Dyatkovskiy2012-04-242-0/+524
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | latest PR1255 discussion posts in llvm-commits. Strategy. 0. Implement new classes. Classes doesn't affect anything. They still work with ConstantInt base values at this stage. 1. Fictitious replacement of current ConstantInt case values with ConstantRangesSet. Case ranges set will still hold single value, and ConstantInt *getCaseValue() will return it. But additionally implement new method in SwitchInst that allows to work with case ranges. Currenly I think it should be some wrapper that returns either single value or ConstantRangesSet object. 2. Step-by-step replacement of old "ConstantInt* getCaseValue()" with new alternative. Modify algorithms for all passes that works with SwitchInst. But don't modify LLParser and BitcodeReader/Writer. Still hold single value in each ConstantRangesSet object. On this stage some parts of LLVM will use old-style methods, and some ones new-style. 3. After all getCaseValue() usages will removed and whole LLVM and its clients will work in new style - modify LLParser, Reader and Writer. Remove getCaseValue(). 4. Replace ConstantInt*-based case ranges set items with APInt ones. Currently we are on Zero Stage: New classes. ConstantRangesSet. I selected ConstantArrays as case ranges set "holder" object (it is a temporary decision, I'll explain why below). The array items are may be ConstantVectors with single item, and ConstantVectors with two items (that means single number and range respectively). The ConstantInt will used as basic value representation. It will replaced with APInt then. Of course ConstantArray and ConstantVector will go away after ConstantInt => APInt replacement. New class mandatory features: - bool isSatisfies(ConstantInt *V) method (need better name?). Returns true if the given value satisfies this case. - Case's ranges and values enumeration. In some passes we need to analize each case (SwitchLowering for example). Factory + unified clusterify. I also propose to implement the factory that allows to build case object with user friendly way. I called it CRSBuilder by now. Currenly I implemented the factory that allows add,remove pairs of range+successor. It also allows add existing ConstantRangesSet decompiling it to separated ranges. Factory can emit either clusters set (single case range + successor) or the set of "ConstantRangesSet + Successor" pairs. So you can use it either as builder for new cases set for SwitchInst, or for clusterification of existing cases set. Just call Factory.optimize() and it emits optimized and sorted clusters collection for you! I tested clusterification on SelectionDAGBuilder - it works fine. Don't worry it was not included in this patch. Just new classes. Factory is a template. There are two params: SuccessorClass and IsReadonly. So you can specify what successor you need (BB or MBB). And you can also restrict your factory to use values in read-only mode (SelectionDAGBuilder need IsReadonly=true). Read-only factory couldn't build the cases ranges. llvm-svn: 155464
* AVX: Add additional vbroadcast replacement sequences for integers.Nadav Rotem2012-04-241-3/+30
| | | | | | | Remove the v2f64 patterns because it does not match any vbroadcast instruction. llvm-svn: 155461
* cmake: new fileAndrew Trick2012-04-241-0/+1
| | | | llvm-svn: 155460
* misched: DAG builder must special case earlyclobberAndrew Trick2012-04-241-0/+9
| | | | llvm-svn: 155459
* misched: try (not too hard) to place debug values where they belongAndrew Trick2012-04-241-0/+25
| | | | llvm-svn: 155458
* misched: ignore debug values during schedulingAndrew Trick2012-04-241-6/+31
| | | | llvm-svn: 155457
* misched: DAG builder support for tracking register pressure within the ↵Andrew Trick2012-04-244-7/+65
| | | | | | | | | current scheduling region. The DAG builder is a convenient place to do it. Hopefully this is more efficient than a separate traversal over the same region. llvm-svn: 155456
* RegisterPressure: A utility for computing register pressure within aAndrew Trick2012-04-242-0/+718
| | | | | | | | | | | | | | | | | | MachineInstr sequence. This uses the new target interface for tracking register pressure using pressure sets to model overlapping register classes and subregisters. RegisterPressure results can be tracked incrementally or stored at region boundaries. Global register pressure can be deduced from local RegisterPressure results if desired. This is an early, somewhat untested implementation. I'm working on testing it within the context of a register pressure reducing MachineScheduler. llvm-svn: 155454
* Add missing test cases for ARM VLD3 (single 3-element structure to all lanes)Kevin Enderby2012-04-242-0/+38
| | | | | | instructions. llvm-svn: 155453
* Add missing test cases for ARM VLD4 (single 4-element structure to all lanes)Kevin Enderby2012-04-242-0/+49
| | | | | | instructions. llvm-svn: 155444
* AVX2: The BLENDPW instruction selects between vectors of v16i16 using an i8Nadav Rotem2012-04-241-6/+0
| | | | | | | immediate. We can't use it here because the shuffle code does not check that the lower part of the word is identical to the upper part. llvm-svn: 155440
* Refactor Thumb ITState handling in ARM Disassembler to more efficiently use ↵Richard Barton2012-04-241-31/+69
| | | | | | its vector llvm-svn: 155439
* AVX: We lower VECTOR_SHUFFLE and BUILD_VECTOR nodes into vbroadcast instructionsNadav Rotem2012-04-242-5/+83
| | | | | | | | | using the pattern (vbroadcast (i32load src)). In some cases, after we generate this pattern new users are added to the load node, which prevent the selection of the blend pattern. This commit provides fallback patterns which perform in-vector broadcast (using in-vector vbroadcast in AVX2 and pshufd on AVX1). llvm-svn: 155437
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