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* [TableGen][GlobalISel] Optimize MatchTable for faster instruction selectionQuentin Colombet2017-12-182-93/+370
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | *** Context *** Prior to this patchw, the table generated for matching instruction was straight forward but highly inefficient. Basically, each pattern generates its own set of self contained checks and actions. E.g., TableGen generated: // First pattern CheckNumOperand 3 CheckOpcode G_ADD ... Build ADDrr // Second pattern CheckNumOperand 3 CheckOpcode G_ADD ... Build ADDri // Third pattern CheckNumOperand 3 CheckOpcode G_SUB ... Build SUBrr *** Problem *** Because of that generation, a *lot* of check were redundant between each pattern and were checked every single time until we reach the pattern that matches. E.g., Taking the previous table, let say we are matching a G_SUB, that means we were going to check all the rules for G_ADD before looking at the G_SUB rule. In particular we are going to do: check 3 operands; PASS check G_ADD; FAIL ; Next rule check 3 operands; PASS (but we already knew that!) check G_ADD; FAIL (well it is still not true) ; Next rule check 3 operands; PASS (really!!) check G_SUB; PASS (at last :P) *** Proposed Solution *** This patch introduces a concept of group of rules (GroupMatcher) that share some predicates and only get checked once for the whole group. This patch only creates groups with one nesting level. Conceptually there is nothing preventing us for having deeper nest level. However, the current implementation is not smart enough to share the recording (aka capturing) of values. That limits its ability to do more sharing. For the given example the current patch will generate: // First group CheckOpcode G_ADD // First pattern CheckNumOperand 3 ... Build ADDrr // Second pattern CheckNumOperand 3 ... Build ADDri // Second group CheckOpcode G_SUB // Third pattern CheckNumOperand 3 ... Build SUBrr But if we allowed several nesting level, it could create a sub group for the checknumoperand 3. (We would need to call optimizeRules on the rules within a group.) *** Result *** With only one level of nesting, the instruction selection pass is up to 4x faster. For instance, one instruction now takes 500 checks, instead of 24k! With more nesting we could get in the tens I believe. Differential Revision: https://reviews.llvm.org/D39034 rdar://problem/34670699 llvm-svn: 321017
* Fix more inconsistent line endings. NFC.Dimitry Andric2017-12-1810-67/+67
| | | | llvm-svn: 321016
* [X86] Minor formatting fix to getHostCPUFeatures. NFCCraig Topper2017-12-181-2/+1
| | | | llvm-svn: 321015
* [MachineOutliner] Recommit r320229Jessica Paquette2017-12-182-60/+190
| | | | | | | LR was undefined entering outlined functions that contain calls. This made the machine verifier unhappy when expensive checks were enabled. This fixes that. llvm-svn: 321014
* [PPC] Also disable the pre-emit version of reg+reg to reg+imm transformation.Benjamin Kramer2017-12-184-4/+4
| | | | | | This has the same issue as the early pass disabled in r321010. llvm-svn: 321013
* [cmake] Update experimental target error messageDon Hinton2017-12-181-2/+6
| | | | | | | | | | | | | | Summary: Update this error message indicate this test only ensures experimental targets were passed via LLVM_EXPERIMENTAL_TARGETS_TO_BUILD. Originally, this test validated all targets, but in r184923, it was moved after the LLVMBUILDTOOL test, which also validates all targets, making that part of the test redundant. Differential Revision: https://reviews.llvm.org/D41273 llvm-svn: 321012
* Recommit "[DWARFv5] Dump an MD5 checksum in the line-table header."Paul Robinson2017-12-187-27/+87
| | | | | | | | | | | Adds missing support for DW_FORM_data16. Update of r320852/r320886, fixing the unittest again, this time use a raw char string for the test data. Differential Revision: https://reviews.llvm.org/D41090 llvm-svn: 321011
* [PPC] Disable reg+reg to reg+imm transformation.Benjamin Kramer2017-12-181-1/+1
| | | | | | It creates invalid instructions. PR35688. llvm-svn: 321010
* Fix inconsistent line endings in HexagonVectorLoopCarriedReuse.cpp. NFC.Dimitry Andric2017-12-181-7/+7
| | | | llvm-svn: 321009
* [Hexagon] Higher versions of HVX imply presence of lower versionsKrzysztof Parzyszek2017-12-181-6/+6
| | | | | | | The code in Hexagon_MC::completeHVXFeatures wasn't setting all HVX- related features correctly. llvm-svn: 321008
* [IR] Support the new TBAA metadata format in IR verifierIvan A. Kosarev2017-12-182-36/+114
| | | | | | Differential Revision: https://reviews.llvm.org/D40438 llvm-svn: 321007
* Fix inconsistent line endings in ARCDisassembler.cpp. NFC.Dimitry Andric2017-12-181-3/+3
| | | | llvm-svn: 321006
* i[Hexagon] ANY_EXTEND_VECTOR_INREG should be Custom, not Legal in r321004Krzysztof Parzyszek2017-12-181-1/+2
| | | | llvm-svn: 321005
* [Hexagon] Generate HVX code for vector sign-, zero- and any-extendsKrzysztof Parzyszek2017-12-187-0/+168
| | | | | | Implement any-extend as zero-extend. llvm-svn: 321004
* [X86] Regenerate test to improve codegen testing for D41350Simon Pilgrim2017-12-181-15/+75
| | | | llvm-svn: 321003
* [Hexagon] Prefer to widen HVX vectors instead of promotingKrzysztof Parzyszek2017-12-182-0/+14
| | | | llvm-svn: 321002
* Removed unused DominanceFrontierMatt Arsenault2017-12-181-3/+0
| | | | llvm-svn: 321001
* [ThinLTO] Make distributed indexes test more robustTeresa Johnson2017-12-181-7/+7
| | | | | | | | | Modify test so that it passes in the reverse-iteration bot. We use DenseMap instead of std::map for the summaries to emit into distributed index files. The iteration order is not defined, but it is deterministic, which is good enough. llvm-svn: 321000
* [PGO] add MST min edge selection heuristic to ensure non-zero entry countXinliang David Li2017-12-1810-21/+102
| | | | | | Differential Revision: http://reviews.llvm.org/D41059 llvm-svn: 320998
* [YAML] Add support for non-printable charactersFrancis Visoiu Mistrih2017-12-1817-76/+245
| | | | | | | | | | | | | | | | | | | | | | | | | | | | LLVM IR function names which disable mangling start with '\01' (https://www.llvm.org/docs/LangRef.html#identifiers). When an identifier like "\01@abc@" gets dumped to MIR, it is quoted, but only with single quotes. http://www.yaml.org/spec/1.2/spec.html#id2770814: "The allowed character range explicitly excludes the C0 control block allowed), the surrogate block #xD800-#xDFFF, #xFFFE, and #xFFFF." http://www.yaml.org/spec/1.2/spec.html#id2776092: "All non-printable characters must be escaped. [...] Note that escape sequences are only interpreted in double-quoted scalars." This patch adds support for printing escaped non-printable characters between double quotes if needed. Should also fix PR31743. Differential Revision: https://reviews.llvm.org/D41290 llvm-svn: 320996
* [IR] Add MDBuilder helpers for the new TBAA metadata formatIvan A. Kosarev2017-12-182-4/+49
| | | | | | | | | | | The new helpers are supposed to be used in clang to generate TBAA information in the new format proposed in this thread: http://lists.llvm.org/pipermail/llvm-dev/2017-November/118748.html Differential Revision: https://reviews.llvm.org/D39956 llvm-svn: 320993
* [AArch64][SVE] Asm: Improve diagnostics further when +sve is not specifiedSander de Smalen2017-12-188-76/+80
| | | | | | | | | | | | | | Summary: Patch [4/4] in a series to add parsing of predicates and properly parse SVE ZIP1/ZIP2 instructions. This patch further improves diagnostic messages for when the SVE feature is not specified. Reviewers: rengolin, fhahn, olista01, echristo, efriedma Reviewed By: fhahn Subscribers: sdardis, aemerson, javed.absar, tschuett, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D40363 llvm-svn: 320992
* Reland "[mips] Fix the target specific instruction verifier"Simon Dardis2017-12-1827-50/+111
| | | | | | | | | | | | | Fix an off by one error in the bounds checking for 'dinsu' and update the ranges in the test comments so that they are accurate. This version has the correct commit message. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D41183 llvm-svn: 320991
* [Memcpy Loop Lowering] Remove the fixed int8 lowering.Sean Fertile2017-12-187-197/+73
| | | | | | | | Switch over to the lowering that uses target supplied operand types. Differential Revision: https://reviews.llvm.org/D41201 llvm-svn: 320989
* [TableGen][AsmMatcherEmitter] Only choose specific diagnostic for enabled ↵Sander de Smalen2017-12-1830-223/+228
| | | | | | | | | | | | | | | | | | | | | | | instruction Summary: When emitting a diagnostic for an invalid operand, a specific diagnostic should only be reported when the instruction being matched is actually enabled by the feature flags. Patch [3/4] in a series to add parsing of predicates and properly parse SVE ZIP1/ZIP2 instructions. This patch fixes bogus diagnostic messages for when the SVE feature is not specified. Reviewers: rengolin, craig.topper, olista01, sdardis, stoklund Reviewed By: olista01, sdardis Subscribers: fhahn, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D40362 llvm-svn: 320986
* [LVI] Support for ashr in LVIMax Kazantsev2017-12-182-0/+28
| | | | | | | | | | Enhance LVI to analyze the ‘ashr’ binary operation. This leverages the infrastructure in ConstantRange for the ashr operation. Patch by Surya Kumari Jangala! Differential Revision: https://reviews.llvm.org/D40886 llvm-svn: 320983
* [ARM GlobalISel] Fix G_(UN)MERGE_VALUES handling after r319524Diana Picus2017-12-181-9/+5
| | | | | | | | | r319524 has made more G_MERGE_VALUES/G_UNMERGE_VALUES pairs legal than are supported by the rest of the pipeline. Restrict that to only the cases that we can currently handle: packing 32-bit values into 64-bit ones, when we have hardware FP. llvm-svn: 320980
* Constexprify LaneBitmask factory methods.Benjamin Kramer2017-12-181-3/+3
| | | | | | This avoids global constructors when they're used in a global constant. llvm-svn: 320979
* [ConstantRange] Support for ashr in ConstantRange computationMax Kazantsev2017-12-183-0/+87
| | | | | | | | | | | Extend the ConstantRange implementation to compute the range of possible values resulting from an arithmetic right shift operation. There will be a follow up patch to leverage this constant range infrastructure in LazyValueInfo. Patch by Surya Kumari Jangala! Differential Revision: https://reviews.llvm.org/D40881 llvm-svn: 320976
* Revert "[mips] Fix the target specific instruction verifier"Simon Dardis2017-12-1827-111/+50
| | | | | | This reverts commit r320974. The commit message lacked the Differential Revison: line. llvm-svn: 320975
* [mips] Fix the target specific instruction verifierSimon Dardis2017-12-1827-50/+111
| | | | | | | | | | | Fix an off by one error in the bounds checking for 'dinsu' and update the ranges in the test comments so that they are accurate. Reviewers: atanasyan https://reviews.llvm.org/D41183 llvm-svn: 320974
* [AArch64][SVE] Asm: Add ZIP1/ZIP2 instructions (predicate/data vectors)Sander de Smalen2017-12-186-0/+362
| | | | | | | | | | | | | | Summary: Patch [2/4] in a series to add parsing of predicates and properly parse SVE ZIP1/ZIP2 instructions. Reviewers: rengolin, kristof.beyls, fhahn, mcrosier, evandro Reviewed By: fhahn Subscribers: aemerson, javed.absar, llvm-commits, tschuett Differential Revision: https://reviews.llvm.org/D40361 llvm-svn: 320973
* [AArch64][SVE] Asm: Add SVE predicate register definitions and parsing supportSander de Smalen2017-12-185-10/+207
| | | | | | | | | | | | | | Summary: Patch [1/4] in a series to add parsing of predicates and properly parse SVE ZIP1/ZIP2 instructions. Reviewers: rengolin, kristof.beyls, fhahn, mcrosier, evandro, echristo, efriedma Reviewed By: fhahn Subscribers: aemerson, javed.absar, llvm-commits, tschuett Differential Revision: https://reviews.llvm.org/D40360 llvm-svn: 320970
* [ThinLTO] Remove unused codeEugene Leviant2017-12-181-14/+0
| | | | | | | This is a re-commit of r320464, after patch for gold plugin was landed. llvm-svn: 320968
* AArch64: work around how Cyclone handles "movi.2d vD, #0".Tim Northover2017-12-188-23/+69
| | | | | | | | | | | For Cylone, the instruction "movi.2d vD, #0" is executed incorrectly in some rare circumstances. Work around the issue conservatively by avoiding the instruction entirely. This patch changes CodeGen so that problematic instructions are never generated, and the AsmParser so that an equivalent instruction is used (with a warning). llvm-svn: 320965
* [TargetLibraryInfo] Discard library functions with incorrectly sized integersIgor Laevsky2017-12-182-3/+19
| | | | | | Differential Revision: https://reviews.llvm.org/D41184 llvm-svn: 320964
* [ARM] Adjust test checksSam Parker2017-12-181-2/+2
| | | | | | Correct the CHECK-LABELS of a couple of dag combine tests. llvm-svn: 320963
* [DAGCombine] Move AND nodes to multiple load leavesSam Parker2017-12-182-378/+472
| | | | | | | | | | | | | Search from AND nodes to find whether they can be propagated back to loads, so that the AND and load can be combined into a narrow load. We search through OR, XOR and other AND nodes and all bar one of the leaves are required to be loads or constants. The exception node then needs to be masked off meaning that the 'and' isn't removed, but the loads(s) are narrowed still. Differential Revision: https://reviews.llvm.org/D41177 llvm-svn: 320962
* [NFC][CodeGen][ExpandMemCmp] Fix documentation.Clement Courbet2017-12-181-3/+2
| | | | llvm-svn: 320960
* [X86] Use mattr instead of mcpu in some of the cost model tests.Craig Topper2017-12-184-39/+33
| | | | | | | | Based on the names of the check lines, features seems more appropriate that cpu. Spotted while prototyping my patch to make 512-bit vectors illegal on SKX sometimes. llvm-svn: 320959
* [SROA] Disable non-whole-alloca splits by defaultHiroshi Inoue2017-12-184-60/+23
| | | | | | | This patch introduce a switch to control splitting of non-whole-alloca slices with default off. The switch will be default on again after fixing an issue reported in PR35657. llvm-svn: 320958
* [X86] Fix mistake that I made when splitting up the setOperationAction calls ↵Craig Topper2017-12-181-2/+2
| | | | | | | | recently. The block I moved things that need BWI and 512-bit or VLX is incorrectly qualified with just hasBWI || hasVLX. Here I've qualified it with hasBWI && (hasAVX512 || hasVLX) where the hasAVX512 will be replaced with allowing 512-bit vectors in an upcoming patch. llvm-svn: 320957
* [CGP] Fix the handling select inst in complex addressing modeSerguei Katkov2017-12-182-2/+23
| | | | | | | | | | | | | | | When we put the value in select placeholder we must pass the value through simplification tracker due to the value might be already simplified and erased. This is a fix for PR35658. Reviewers: john.brawn, uabelho Reviewed By: john.brawn Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41251 llvm-svn: 320956
* [x86] add tests for finite libcall lowering (PR35672); NFCSanjay Patel2017-12-181-0/+52
| | | | llvm-svn: 320955
* Re-commit "Properly handle multi-element and dynamically sized allocas in ↵Bjorn Steinbrink2017-12-173-5/+24
| | | | | | | | | getPointerDereferenceableBytes()"" llvm-clang-x86_64-expensive-checks-win is still broken, so the failure seems unrelated. llvm-svn: 320953
* [X86] Add test cases that show cases where buildvector of extract and ↵Craig Topper2017-12-171-0/+676
| | | | | | | | inserts should be turned into fmsubadd. This is a follow up to the fmaddsub support added in r320950. Hopefully in the future we can fix lowering to handle this fmsubadd too. llvm-svn: 320951
* [X86] Make the code that creates fmaddsub from build_vector of extracts and ↵Craig Topper2017-12-172-6/+284
| | | | | | | | | | | | | | | | | | | inserts functional and add tests. Summary: We had no tests for this and we couldn't do the optimization because of a bad use count check. We need to know how many non-undef pieces of the build vector were filled in and ensure our use count is equal to that. But on the shuffle combine version we need the use count to be 2. The missing coverage was noticed during the review of D40335. Reviewers: RKSimon, zvi, spatel Reviewed By: RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D41133 llvm-svn: 320950
* [X86] Regenerate truncated rotation tests + add missing 32-bit checksSimon Pilgrim2017-12-171-8/+41
| | | | llvm-svn: 320949
* use uint32_tSam Clegg2017-12-171-2/+2
| | | | llvm-svn: 320947
* [WebAssembly] Export some more info on wasm funtionsSam Clegg2017-12-173-6/+9
| | | | | | | | | | | | | Summary: These fields are useful for lld's gc-sections support Also remove an unused field. Subscribers: jfb, dschuff, jgravelle-google, aheejin, sunfish Differential Revision: https://reviews.llvm.org/D41320 llvm-svn: 320946
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