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* ARM64: make sure first argument to INSERT_SUBVECTOR has right type.Tim Northover2014-04-022-4/+9
| | | | | | | | Again, coalescing and other optimisations swiftly made the MachineInstrs consistent again, but when compiled at -O0 a bad INSERT_SUBREGISTER was produced. llvm-svn: 205423
* ARM64: convert fp16 narrowing ISel to pseudo-instructionTim Northover2014-04-024-15/+16
| | | | | | | | The previous attempt was fine with optimisations, but was actually rather cavalier with its types. When compiled at -O0, it produced invalid COPY MachineInstrs. llvm-svn: 205422
* Mark FPB as a reserved register when needed.Job Noorman2014-04-022-1/+15
| | | | llvm-svn: 205421
* Work around gold bug http://sourceware.org/PR16794.Rafael Espindola2014-04-023-3/+8
| | | | llvm-svn: 205416
* Remove duplicated DMB instructionsRenato Golin2014-04-025-0/+178
| | | | | | | | | ARM specific optimiztion, finding places in ARM machine code where 2 dmbs follow one another, and eliminating one of them. Patch by Reinoud Elhorst. llvm-svn: 205409
* Added isTargetWindowsMSVC(), renamed isTargetMingw() to isTargetWindowsGNU()Yaron Keren2014-04-022-10/+24
| | | | | | | | | and isTargetCygwin() to isTargetWindowsCygwin() to be consistent with the four Windows environments in Triple.h. Suggestion by Saleem Abdulrasool! llvm-svn: 205393
* [LoopVectorizer] Count dependencies of consecutive pointers as uniformsHal Finkel2014-04-023-0/+65
| | | | | | | | | | | | | | | | | | | | | For the purpose of calculating the cost of the loop at various vectorization factors, we need to count dependencies of consecutive pointers as uniforms (which means that the VF = 1 cost is used for all overall VF values). For example, the TSVC benchmark function s173 has: ... %3 = add nsw i64 %indvars.iv, 16000 %arrayidx8 = getelementptr inbounds %struct.GlobalData* @global_data, i64 0, i32 0, i64 %3 ... and we must realize that the add will be a scalar in order to correctly deduce it to be profitable to vectorize this on PowerPC with VSX enabled. In fact, all dependencies of a consecutive pointer must be a scalar (uniform), and so we simply need to add all consecutive pointers to the worklist that currently detects collects uniforms. Fixes PR19296. llvm-svn: 205387
* Adjust comments regarding non-relocated abbrev offset in debug_info.dwoDavid Blaikie2014-04-022-2/+4
| | | | | | | | I'm not sure the comment in the implementation really adds a lot of value (it's clear that we emit zero when no symbol is provided, but it doesn't explain why we would do that). Happy to iterate. llvm-svn: 205386
* Split debug_loc and debug_loc.dwo emission into two separate functionsDavid Blaikie2014-04-022-21/+32
| | | | | | Based on code review feedback from Eric Christopher on r204697 llvm-svn: 205385
* DebugInfo: Introduce DebugLocList to encapsulate a list of DebugLocEntries ↵David Blaikie2014-04-025-12/+39
| | | | | | | | | | | | and an MC Label to refer to them This removes the magic-number-esque code creating/retrieving the same label for a debug_loc entry from two places and removes the last small piece of reusable logic from emitDebugLoc so that there will be less duplication when refactoring it into two functions (one for debug_loc, the other for debug_loc.dwo). llvm-svn: 205382
* [ARM64][CollectLOH] Add some comments to explain how the LOHsQuentin Colombet2014-04-022-1/+60
| | | | | | | framework works (for the compiler part), since the design document is not available. llvm-svn: 205379
* Add a doxygen comment to DebugLocEntry::Merge.Adrian Prantl2014-04-011-0/+3
| | | | llvm-svn: 205374
* DebugLocEntry: Actually merge the loc entry when returning true.David Blaikie2014-04-012-18/+38
| | | | | | | | | | Seems we didn't have any test coverage for merging... awesome. So I added some - but hit an llvm-objdump bug while I was there. I'm choosing not to shave that yak right now. Code review feedback/bug catch by Adrian Prantl in r205360. llvm-svn: 205373
* Fix accidental fallthrough in DebugLocEntry::hasSameValueOrLocationDavid Blaikie2014-04-011-5/+10
| | | | | | | | | | No test case (this would invoke UB by examining uninitialized members, etc, at best - and this code is apparently untested anyway - I'm about to fix that) Code review feedback from Adrian Prantl on r205360. llvm-svn: 205367
* Remove unused function DebugLocEntry::isEmptyDavid Blaikie2014-04-011-3/+0
| | | | llvm-svn: 205365
* Refactor out the comparison of the location/value in a DebugLocEntryDavid Blaikie2014-04-011-18/+19
| | | | llvm-svn: 205364
* Add inequality operator for MachineLocation.David Blaikie2014-04-011-0/+5
| | | | | | Fixes the build I broke in r205360 llvm-svn: 205361
* DebugInfo: Split DebugLocEntry into its own file.David Blaikie2014-04-012-85/+113
| | | | | | | It seems big enough that it deserves its own file - but it is header only, so there's no need for another cpp file, etc. llvm-svn: 205360
* Add a comment about the DIDescriptor class hierarchy.Adrian Prantl2014-04-012-2/+11
| | | | llvm-svn: 205358
* DwarfDebug: Prevent DebugLocEntry merging from coalescing two differentAdrian Prantl2014-04-012-2/+109
| | | | | | | | constants into only the first one. rdar://14874886. llvm-svn: 205357
* [PowerPC] Add some missing VSX bitcast patternsHal Finkel2014-04-012-0/+16
| | | | llvm-svn: 205352
* If isKnownWindowsMSVCEnvironment then getOS == Triple::Win32 andYaron Keren2014-04-012-3/+2
| | | | | | Environment == Triple::MSVC so it will never be MinGW or Cygwin. llvm-svn: 205349
* Implement X86TTI::getUnrollingPreferencesHal Finkel2014-04-014-10/+197
| | | | | | | | | | | | | | | | | | | | | | | | | | | This provides an initial implementation of getUnrollingPreferences for x86. getUnrollingPreferences is used by the generic (concatenation) unroller, which is distinct from the unrolling done by the loop vectorizer. Many modern x86 cores have some kind of uop cache and loop-stream detector (LSD) used to efficiently dispatch small loops, and taking full advantage of this requires unrolling small loops (small here means 10s of uops). These caches also have limits on the number of taken branches in the loop, and so we also cap the loop unrolling factor based on the maximum "depth" of the loop. This is currently calculated with a partial DFS traversal (partial because it will stop early if the path length grows too much). This is still an approximation, and one that is both conservative (because it does not account for branches eliminated via block placement) and optimistic (because it is only recording the maximum depth over minimum paths). Nevertheless, because the loops that fit in these uop caches are so small, it is not clear how much the details matter. The original set of patches posted for review produced the following test-suite performance results (from the TSVC benchmark) at that time: ControlLoops-dbl - 13% speedup ControlLoops-flt - 15% speedup Reductions-dbl - 7.5% speedup llvm-svn: 205348
* Add some additional fields to TTI::UnrollingPreferencesHal Finkel2014-04-012-4/+25
| | | | | | | | | | | | | | | | | | | In preparation for an upcoming commit implementing unrolling preferences for x86, this adds additional fields to the UnrollingPreferences structure: - PartialThreshold and PartialOptSizeThreshold - Like Threshold and OptSizeThreshold, but used when not fully unrolling. These are necessary because we need different thresholds for full unrolling from those used when partially unrolling (the full unrolling thresholds are generally going to be larger). - MaxCount - A cap on the unrolling factor when partially unrolling. This can be used by a target to prevent the unrolled loop from exceeding some resource limit independent of the loop size (such as number of branches). There should be no functionality change for any in-tree targets. llvm-svn: 205347
* Use TopTTI->getGEPCost from within getUserCostHal Finkel2014-04-011-4/+4
| | | | | | | | | | | The implementation of getUserCost had duplicated (and hard-coded) the default logic in getGEPCost. Instead, it is better to use getGEPCost directly, which limits the default logic to the implementation of one function, and allows targets to override the behavior. No functionality change intended. llvm-svn: 205346
* [mips] Add Octeon cnMips instructions mtmX and mtpXKai Nacke2014-04-013-0/+31
| | | | | | | | | Adds the Octeon cnMips instructions "load multiplier register MPLx" and "load product register Px". Includes tests. Reviews by: Daniel.Sanders@imgtec.com llvm-svn: 205343
* Support segmented stacks on Win64Reid Kleckner2014-04-012-5/+59
| | | | | | | Identical to Win32 method except the GS segment register is used for TLS instead of FS and pvArbitrary is at TEB offset 0x28 instead of 0x14. llvm-svn: 205342
* Fix missing RUN line in testMatt Arsenault2014-04-011-0/+1
| | | | llvm-svn: 205341
* isTargetWindows() renamed to isTargetKnownWindowsMSVC()Yaron Keren2014-04-016-16/+16
| | | | | | | | to reflect its current functionality. Based on Takumi NAKAMURA suggestion. llvm-svn: 205338
* Make isSetCCEquivalent respect the TargetBooleanContentsMatt Arsenault2014-04-012-19/+51
| | | | llvm-svn: 205336
* Add helpers for checking if a value is a target boolean constant.Matt Arsenault2014-04-012-0/+56
| | | | llvm-svn: 205335
* DebugInfo: Factor out common functionality for rendering debug_loc and ↵David Blaikie2014-04-012-10/+17
| | | | | | | | | debug_loc.dwo location list entries In preparation for refactoring this function into two, one for debug_loc, one for debug_loc.dwo. llvm-svn: 205324
* Cleanup remaining use of removed variable to fix the buildDavid Blaikie2014-04-011-1/+1
| | | | llvm-svn: 205323
* Simplify debug_loc.dwo handling slightly.David Blaikie2014-04-013-8/+3
| | | | llvm-svn: 205322
* ARM: rename ARMle/ARMbe with ARMLE/ARMBE, and Thumble/Thumbbe with ↵Christian Pirker2014-04-0110-114/+114
| | | | | | ThumbLE/ThumbBE llvm-svn: 205317
* ARM: teach LLVM that Cortex-A7 is very similar to A8.Tim Northover2014-04-013-9/+11
| | | | llvm-svn: 205314
* Attempting to fix r205124, which had failed asserts when built with MSVC.Aaron Ballman2014-04-011-1/+1
| | | | | | Suggestion from Yaron Keren. llvm-svn: 205313
* ARM: add cyclone CPU with ZeroCycleZeroing feature.Tim Northover2014-04-016-6/+115
| | | | | | | | The Cyclone CPU is similar to swift for most LLVM purposes, but does have two preferred instructions for zeroing a VFP register. This teaches LLVM about them. llvm-svn: 205309
* [mips] Renamed ParseAnyRegisterWithoutDollar to MatchAnyRegisterWithoutDollarDaniel Sanders2014-04-011-8/+14
| | | | | | | | | This is for consistency with other functions. The Parse* functions consume tokens and the Match* functions don't. No functional change. llvm-svn: 205305
* Fixing an MSVC warning about widening the result of a 32-bit shift ↵Aaron Ballman2014-04-011-1/+1
| | | | | | implicitly. No functional change intended. llvm-svn: 205304
* ARM64: add intrinsic for pmull (p64 x p64 = p128) operations.Tim Northover2014-04-013-2/+31
| | | | llvm-svn: 205302
* Fixing warnings in the MSVC build. No functional changes intended.Aaron Ballman2014-04-015-42/+42
| | | | llvm-svn: 205301
* [mips] Extend ParseJumpTarget to support the full symbol expression syntax.Daniel Sanders2014-04-012-27/+20
| | | | | | | | | | | | | | | | Summary: This should fix the issues the D3222 caused in lld. Testcase is based on the one that failed in the buildbot. Depends on D3233 Reviewers: matheusalmeida, vmedic Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3234 llvm-svn: 205298
* [mips] Use AsmLexer::peekTok() to resolve the conflict between $reg and $symDaniel Sanders2014-04-011-15/+10
| | | | | | | | | | | | | | | Summary: Parsing registers no longer consume the $ token before it's confirmed whether it really has a register or not, therefore it's no longer impossible to match symbols if registers were tried first. Depends on D3232 Reviewers: matheusalmeida, vmedic Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3233 llvm-svn: 205297
* [mips] Hoist Parser.Lex() calls out of MatchAnyRegisterNameWithoutDollar()Daniel Sanders2014-04-011-9/+8
| | | | | | | | | | | | | | | Summary: No functional change Depends on D3222 Reviewers: matheusalmeida, vmedic Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3232 llvm-svn: 205295
* ARM64: add patterns for more lane-wise ld1/st1 operations.Tim Northover2014-04-014-139/+268
| | | | llvm-svn: 205294
* ARM64: fix bug in ld3r (1d) SelectionDAG.Tim Northover2014-04-012-1/+32
| | | | llvm-svn: 205293
* [mips] Rewrite MipsAsmParser and MipsOperand.Daniel Sanders2014-04-0123-1069/+929
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Highlights: - Registers are resolved much later (by the render method). Prior to that point, GPR32's/GPR64's are GPR's regardless of register size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register size or FR mode. Numeric registers can be anything. - All registers are parsed the same way everywhere (even when handling symbol aliasing) - One consequence is that all registers can be specified numerically almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing but that can be easily resolved. - Removes the need for the hasConsumedDollar hack - Parenthesis and Bracket suffixes are handled generically - Micromips instructions are parsed directly instead of going through the standard encodings first. - rdhwr accepts all 32 registers, and the following instructions that previously xfailed now work: ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d, c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1 - Diagnostics involving registers point at the correct character (the $) - There's only one kind of immediate in MipsOperand. LSA immediates are handled by the predicate and renderer. Lowlights: - Hardcoded '$zero' in the div patterns is handled with a hack. MipsOperand::isReg() will return true for a k_RegisterIndex token with Index == 0 and getReg() will return ZERO for this case. Note that it doesn't return ZERO_64 on isGP64() targets. - I haven't cleaned up all of the now-unused functions. Some more of the generic parser could be removed too (integers and relocs for example). - insve.df needed a custom decoder to handle the implicit fourth operand that was needed to make it parse correctly. The difficulty was that the matcher expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this. Reviewers: matheusalmeida, vmedic Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3222 llvm-svn: 205292
* Recover TableGen/LangRef, make it officialRenato Golin2014-04-015-1307/+911
| | | | | | | | | | | | | Making the new TableGen documentation official and marking the old file as "Moved". Also, reverting the original LangRef as the normative formal description of the language, while keeping the "new" LangRef as LangIntro for the less inlcined to reading language grammars. We should remove TableGenFundamentals.rst one day, but for now, just a warning that it moved will have to do, while we make sure there are no more links to it from elsewhere. llvm-svn: 205289
* [x86] Do not convert to cmp32 for Atom arch by Sergey OkunevAlexey Volkov2014-04-012-4/+42
| | | | | | Differential Revision: http://llvm-reviews.chandlerc.com/D2824 llvm-svn: 205288
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