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* Add tests to document current InstCombine behavior for clamp pattern.Nikolai Bozhenov2017-06-281-0/+500
| | | | | | | | | | | | | | | | | | | Summary: This commit adds the tests for clamp pattern as a prerequisite of D33186 to make the impact of that fix more clear and also to document current behavior. Reviewers: spatel, jmolloy Reviewed By: spatel Subscribers: n.bozhenov, llvm-commits Patch by Andrei Elovikov <andrei.elovikov@intel.com> Differential Revision: https://reviews.llvm.org/D34350 llvm-svn: 306524
* [DebugInfo] - Removed trailing whitespaces. NFC.George Rimar2017-06-281-68/+68
| | | | llvm-svn: 306518
* Recommit "[ELF] - Add ability for DWARFContextInMemory to exit early when ↵George Rimar2017-06-284-11/+81
| | | | | | | | | | | | | | | | | | | | | any error happen." With fix in include folder character case: #include "llvm/Codegen/AsmPrinter.h" -> #include "llvm/CodeGen/AsmPrinter.h" Original commit message: Change introduces error reporting policy for DWARFContextInMemory. New callback provided by client is able to handle error on it's side and return Halt or Continue. That allows to either keep current behavior when parser prints all errors but continues parsing object or implement something very different, like stop parsing on a first error and report an error in a client style. Differential revision: https://reviews.llvm.org/D34328 llvm-svn: 306517
* [ARM] Make -mcpu=generic schedule for an in-order core (Cortex-A8).Kristof Beyls2017-06-2848-414/+406
| | | | | | | | | | | | | | | | The benchmarking summarized in http://lists.llvm.org/pipermail/llvm-dev/2017-May/113525.html showed this is beneficial for a wide range of cores. As is to be expected, quite a few small adaptations are needed to the regressions tests, as the difference in scheduling results in: - Quite a few small instruction schedule differences. - A few changes in register allocation decisions caused by different instruction schedules. - A few changes in IfConversion decisions, due to a difference in instruction schedule and/or the estimated cost of a branch mispredict. llvm-svn: 306514
* Revert r306512 "[ELF] - Add ability for DWARFContextInMemory to exit early ↵George Rimar2017-06-284-81/+11
| | | | | | | | | | | | | | | | | when any error happen." It broke BB: [13/106] 13 0.022 Generating VCSRevision.h [25/106] 24 1.209 Building CXX object unittests/DebugInfo/DWARF/CMakeFiles/DebugInfoDWARFTests.dir/DWARFDebugInfoTest.cpp.o FAILED: unittests/DebugInfo/DWARF/CMakeFiles/DebugInfoDWARFTests.dir/DWARFDebugInfoTest.cpp.o /home/bb/bin/g++ -DGTEST_HAS_RTTI=0 -DLLVM_BUILD_GLOBAL_ISEL -D_DEBUG -D_GNU_SOURCE -D__STDC_CONSTANT_MACROS -D__STDC_FORMAT_MACROS -D__STDC_LIMIT_MACROS -Iunittests/DebugInfo/DWARF -I../llvm-project/llvm/unittests/DebugInfo/DWARF -Iinclude -I../llvm-project/llvm/include -I../llvm-project/llvm/utils/unittest/googletest/include -I../llvm-project/llvm/utils/unittest/googlemock/include -fPIC -fvisibility-inlines-hidden -m32 -std=c++11 -Wall -W -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wno-missing-field-initializers -pedantic -Wno-long-long -Wno-maybe-uninitialized -Wdelete-non-virtual-dtor -Wno-comment -ffunction-sections -fdata-sections -O3 -UNDEBUG -Wno-variadic-macros -fno-exceptions -fno-rtti -MD -MT unittests/DebugInfo/DWARF/CMakeFiles/DebugInfoDWARFTests.dir/DWARFDebugInfoTest.cpp.o -MF unittests/DebugInfo/DWARF/CMakeFiles/DebugInfoDWARFTests.dir/DWARFDebugInfoTest.cpp.o.d -o unittests/DebugInfo/DWARF/CMakeFiles/DebugInfoDWARFTests.dir/DWARFDebugInfoTest.cpp.o -c ../llvm-project/llvm/unittests/DebugInfo/DWARF/DWARFDebugInfoTest.cpp ../llvm-project/llvm/unittests/DebugInfo/DWARF/DWARFDebugInfoTest.cpp:18:37: fatal error: llvm/Codegen/AsmPrinter.h: No such file or directory #include "llvm/Codegen/AsmPrinter.h" ^ compilation terminated. llvm-svn: 306513
* [ELF] - Add ability for DWARFContextInMemory to exit early when any error ↵George Rimar2017-06-284-11/+81
| | | | | | | | | | | | | | | | happen. Change introduces error reporting policy for DWARFContextInMemory. New callback provided by client is able to handle error on it's side and return Halt or Continue. That allows to either keep current behavior when parser prints all errors but continues parsing object or implement something very different, like stop parsing on a first error and report an error in a client style. Differential revision: https://reviews.llvm.org/D34328 llvm-svn: 306512
* [InstCombine] Add test case demonstrating that we don't handle icmp eq ↵Craig Topper2017-06-281-0/+21
| | | | | | (trunc (lshr(X, cst1)), cst->icmp (and X, mask), cst when the shift type is larger than 64-bits. NFC llvm-svn: 306510
* Revert r306508 "[InstCombine] Add test case demonstrating that we don't ↵Craig Topper2017-06-282-22/+0
| | | | | | | | handle icmp eq (trunc (lshr(X, cst1)), cst->icmp (and X, mask), cst when the shift type is larger than 64-bits. NFC" I accidentally had a extra change in there. llvm-svn: 306509
* [InstCombine] Add test case demonstrating that we don't handle icmp eq ↵Craig Topper2017-06-282-0/+22
| | | | | | (trunc (lshr(X, cst1)), cst->icmp (and X, mask), cst when the shift type is larger than 64-bits. NFC llvm-svn: 306508
* Add missing library dependency to fix build break in llvm-lto2Hiroshi Inoue2017-06-282-1/+2
| | | | | | | | | error message CMakeFiles/llvm-lto2.dir/llvm-lto2.cpp.o: In function `dumpSymtab(int, char**)': llvm-lto2.cpp:(.text._ZL10dumpSymtabiPPc+0x238): undefined reference to `llvm::getBitcodeFileContents(llvm::MemoryBufferRef)' collect2: error: ld returned 1 exit status llvm-svn: 306507
* [IRCE][NFC] Better get SCEV for 1 in calculateSubRangesMax Kazantsev2017-06-281-3/+3
| | | | | | | | | A slightly more efficient way to get constant, we avoid resolving in getSCEV and excessive invocations, and we don't create a ConstantInt if 'true' branch is taken. Differential Revision: https://reviews.llvm.org/D34672 llvm-svn: 306503
* Revert "[DAG] Fold FrameIndex offset into BaseIndexOffset analysis. NFCI."Nirav Dave2017-06-283-25/+28
| | | | | | This reverts commit r306498 which appears to cause a compilrt-rt test failures llvm-svn: 306501
* [AMDGPU] Add pattern for v_alignbit_b32 with immediateStanislav Mekhanoshin2017-06-285-19/+48
| | | | | | | | If immediate in shift is less than 32 we can use alignbit too. Differential Revision: https://reviews.llvm.org/D34729 llvm-svn: 306500
* Allow to truncate left shift with non-constant shift amountStanislav Mekhanoshin2017-06-283-79/+86
| | | | | | | | | | | That is pretty common for clang to produce code like (shl %x, (and %amt, 31)). In this situation we can still perform trunc (shl) into shl (trunc) conversion given the known value range of shift amount. Differential Revision: https://reviews.llvm.org/D34723 llvm-svn: 306499
* [DAG] Fold FrameIndex offset into BaseIndexOffset analysis. NFCI.Nirav Dave2017-06-283-28/+25
| | | | | | | Pull FrameIndex comparision reasoning from DAGCombiner::isAlias to general BaseIndexOffset. llvm-svn: 306498
* Inlining: Don't re-map simplified cloned instructions.Kyle Butt2017-06-281-4/+5
| | | | | | | | | | | | | When simplifying an instruction that has been re-mapped, it should never simplify to an instruction in the original function. In the edge case where we are inlining a function into itself, the existing code led to incorrect behavior. Replace the incorrect code with an assert verifying that we never expect simplification to produce an instruction in the old function, unless the functions are the same. Differential Revision: https://reviews.llvm.org/D33850 llvm-svn: 306495
* [TableGen] Improve Debug Output for --debug-only=subtarget-emitter NFCIJoel Jones2017-06-282-0/+8
| | | | | | | | | Add headers for each section of output, with white space and "+++" to improve readability. Differential Revision: https://reviews.llvm.org/D34713 llvm-svn: 306492
* Add missing library dependency.Peter Collingbourne2017-06-281-1/+1
| | | | llvm-svn: 306491
* [COFF, ARM64] Add support for Windows ARM64 COFF formatMandeep Singh Grang2017-06-2716-5/+249
| | | | | | | | | | | | | | | | Summary: This is the llvm part of the initial implementation to support Windows ARM64 COFF format. I will gradually add more functionality in subsequent patches. Reviewers: ruiu, rnk, t.p.northover, compnerd Reviewed By: ruiu, compnerd Subscribers: aemerson, mgorny, javed.absar, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D34705 llvm-svn: 306490
* Object: Teach irsymtab::read() to try to use the irsymtab that we wrote to disk.Peter Collingbourne2017-06-276-9/+89
| | | | | | | | Fixes PR27551. Differential Revision: https://reviews.llvm.org/D33974 llvm-svn: 306488
* Bitcode: Write the irsymtab to disk.Peter Collingbourne2017-06-2717-11/+138
| | | | | | Differential Revision: https://reviews.llvm.org/D33973 llvm-svn: 306487
* Object: Add version and producer fields to the irsymtab header. NFCI.Peter Collingbourne2017-06-272-0/+30
| | | | | | | | | These will be necessary in order to handle upgrades from old bitcode files. Differential Revision: https://reviews.llvm.org/D33972 llvm-svn: 306486
* [CGP] add specialization for memcmp expansion with only one basic blockSanjay Patel2017-06-275-163/+134
| | | | llvm-svn: 306485
* [NewPM/Inliner] Reduce threshold for cold callsites in the non-PGO caseEaswaran Raman2017-06-273-44/+120
| | | | | | Differential Revision: https://reviews.llvm.org/D34312 llvm-svn: 306484
* GlobalISel: add some more sanity-checking to MachineInstrBuilder. NFC.Tim Northover2017-06-271-1/+15
| | | | llvm-svn: 306481
* [AArch64] Inline callee if its target-features are a subset of the callerFlorian Hahn2017-06-273-0/+57
| | | | | | | | | | | | | | | | | | | Summary: Similar to X86, it should be safe to inline callees if their target-features are a subset of the caller. This change matches GCC's inlining behavior with respect to attributes [1]. [1] https://gcc.gnu.org/onlinedocs/gcc/AArch64-Function-Attributes.html#AArch64-Function-Attributes Reviewers: kristof.beyls, javed.absar, rengolin, t.p.northover Reviewed By: t.p.northover Subscribers: aemerson, eraman, llvm-commits Differential Revision: https://reviews.llvm.org/D34698 llvm-svn: 306478
* [EarlyCSE][MemorySSA] Enable MemorySSA in function-simplification pass of ↵Geoff Berry2017-06-274-4/+6
| | | | | | EarlyCSE. llvm-svn: 306477
* [Analysis] Revert r306472 changes in LoopInfo headers to fix broken builds.Eugene Zelenko2017-06-273-120/+69
| | | | llvm-svn: 306476
* [GISel]: Add G_FEXP, G_FEXP2 opcodesAditya Nandakumar2017-06-275-0/+50
| | | | | | | Also add IRTranslator support. https://reviews.llvm.org/D34710 llvm-svn: 306475
* clang-format a file.Rafael Espindola2017-06-271-59/+64
| | | | | | | It had a few inconsistent indentations that made a followup patch hard to read. llvm-svn: 306474
* re-commit r306336: Enable vectorizer-maximize-bandwidth by default.Dehao Chen2017-06-2712-68/+77
| | | | | | Differential Revision: https://reviews.llvm.org/D33341 llvm-svn: 306473
* [Analysis] Fix some Clang-tidy modernize-use-using and Include What You Use ↵Eugene Zelenko2017-06-277-238/+318
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 306472
* [CGP] eliminate a sub instruction in memcmp expansionSanjay Patel2017-06-276-146/+120
| | | | | | | | | | | | | | | | | | | | | | As noted in D34071, there are some IR optimization opportunities that could be handled by normal IR passes if this expansion wasn't happening so late in CGP. Regardless of that, it seems wasteful to knowingly produce suboptimal IR here, so I'm proposing this change: %s = sub i32 %x, %y %r = icmp ne %s, 0 => %r = icmp ne %x, %y Changing the predicate to 'eq' mimics what InstCombine would do, so that's just an efficiency improvement if we decide this expansion should happen sooner. The fact that the PowerPC backend doesn't eliminate the 'subf.' might be something for PPC folks to investigate separately. Differential Revision: https://reviews.llvm.org/D34416 llvm-svn: 306471
* GlobalISel: verify that a COPY is trivial when created.Tim Northover2017-06-273-6/+11
| | | | | | | | | | | | Without this check, COPY instructions can actually be one of the generic casts in disguise. That's confusing and bad. At some point during ISel this restriction has to be relaxed since the fully selected instructions will usually use COPY for those purposes. Right now I think it's possible that relaxation occurs during RegBankSelect (hence the change there). I'm not convinced that's where it belongs long-term though. llvm-svn: 306470
* Clean up a test caseXinliang David Li2017-06-271-34/+41
| | | | llvm-svn: 306468
* Create a PHI value when merging with a known undef live-inKrzysztof Parzyszek2017-06-272-8/+54
| | | | | | Differential Revision: https://reviews.llvm.org/D34640 llvm-svn: 306466
* [WebAssembly] Only run WebAssembly objdump tests if it is enabled as a targetSam Clegg2017-06-271-0/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D34712 llvm-svn: 306464
* [AArch64] Performance enhancements for Cavium ThunderX2 T99Joel Jones2017-06-272-166/+1059
| | | | | | | | | | | | | | This patch enables significant performance enhancements to the Cavium ThunderX2T99 LLVM backend, as observed by running SPEC2K6, by adding more detailed scheduling information. Related Bugzilla bug: http://bugs.llvm.org/show_bug.cgi?id=32562 Patch by: steleman Differential Revision: https://reviews.llvm.org/D31801 llvm-svn: 306462
* [WebAssembly] Add support for printing relocations with llvm-objdumpSam Clegg2017-06-274-3/+31
| | | | | | Differential Revision: https://reviews.llvm.org/D34658 llvm-svn: 306461
* [WebAssembly] Add data size and alignement to linking sectionSam Clegg2017-06-2713-72/+163
| | | | | | | | | The overal size of the data section (including BSS) is otherwise not included in the wasm binary. Differential Revision: https://reviews.llvm.org/D34657 llvm-svn: 306459
* [Hexagon] Use proper predicate register state when expanding PS_vselectKrzysztof Parzyszek2017-06-272-3/+68
| | | | llvm-svn: 306458
* [InstCombine] Propagate nsw flag when turning mul by pow2 into shift when ↵Craig Topper2017-06-272-7/+5
| | | | | | | | | | | | the constant is a vector splat or the scalar bit width is larger than 64-bits The check to see if we can propagate the nsw flag used m_ConstantInt(uint64_t*&) which doesn't work with splat vectors and has a restriction that the bitwidth of the ConstantInt must be 64-bits are less. This patch changes it to use m_APInt to remove both these issues Differential Revision: https://reviews.llvm.org/D34699 llvm-svn: 306457
* [Constants] Fix copy-pasto in llvm_unreachable message. NFCCraig Topper2017-06-271-1/+1
| | | | llvm-svn: 306456
* [CGP] simplify code to get bswap in memcmp expansion; NFCISanjay Patel2017-06-271-3/+1
| | | | llvm-svn: 306452
* [AMDGPU] Add 2 new alignbit patternsStanislav Mekhanoshin2017-06-272-0/+151
| | | | | | Differential Revision: https://reviews.llvm.org/D34655 llvm-svn: 306449
* [CodeExtractor] Prevent extraction of block involving blockaddressSerge Guelton2017-06-273-0/+106
| | | | | | | | | BlockAddress are only valid within their function context, which does not interact well with CodeExtractor. Detect this case and prevent it. Differential Revision: https://reviews.llvm.org/D33839 llvm-svn: 306448
* [AMDGPU] Simplify setcc (sext from i1 b), -1|0, ccStanislav Mekhanoshin2017-06-272-1/+321
| | | | | | | | | | | Depending on the compare code that can be either an argument of sext or negate of it. This helps to avoid v_cndmask_b64 instruction for sext. A reversed value can be further simplified and folded into its parent comparison if possible. Differential Revision: https://reviews.llvm.org/D34545 llvm-svn: 306446
* [Hexagon] Update kills in hexagon-nvj even more properly than beforeKrzysztof Parzyszek2017-06-273-36/+47
| | | | | | | Account for the fact that both, the feeder and the compare can be moved over instructions that kill registers. llvm-svn: 306443
* RenameIndependentSubregs: Fix infinite loopMatt Arsenault2017-06-272-1/+21
| | | | | | | | Apparently this replacement can really be substituting the same as the original register. Avoid restarting the loop when there's been no change in the register uses. llvm-svn: 306441
* [SROA] Fix APInt size when alloca address space is not 0Yaxun Liu2017-06-272-3/+33
| | | | | | | | SROA assumes alloca address space is 0, which causes assertion. This patch fixes that. Differential Revision: https://reviews.llvm.org/D34104 llvm-svn: 306440
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