summaryrefslogtreecommitdiffstats
path: root/llvm
Commit message (Collapse)AuthorAgeFilesLines
* fixed typosSanjay Patel2014-08-121-5/+5
| | | | llvm-svn: 215451
* Make the test a bit more strict.Rafael Espindola2014-08-121-2/+2
| | | | | | | Before it would pass even if @b or @c ended up pointing to a variable named @a123. llvm-svn: 215450
* Add a plugin testcase for merging weak variables.Rafael Espindola2014-08-122-0/+18
| | | | | | | | | I initially thought I could implement COMDATs with aliases by just internalizing GVs instead of dropping them. This is a counter example: Internalizing one of the @a would make @b and @c point to different variables. llvm-svn: 215447
* llvm/test/TableGen/*Foreach*.td: Remove XFAIL:vg_leak. They have not been ↵NAKAMURA Takumi2014-08-124-4/+0
| | | | | | failing since r215176. llvm-svn: 215445
* Reverted my "Testing commit access" commit.Toma Tabacu2014-08-121-0/+1
| | | | llvm-svn: 215441
* Testing commit access.Toma Tabacu2014-08-121-1/+0
| | | | llvm-svn: 215440
* llvm-objdump: print contents of MachO __unwind_info sectionsTim Northover2014-08-125-11/+306
| | | | llvm-svn: 215437
* Have MachineRegisterInfo take and store the MachineFunction itEric Christopher2014-08-123-7/+7
| | | | | | | | was created for rather than the TargetMachine since we only needed the TM for the subtarget and we can get that from the MF. llvm-svn: 215432
* [MachineCombiner] Fix for ICE bug 20598Gerolf Hoflehner2014-08-122-1/+108
| | | | | | | | | | | | | | | | | | The combiner ignored DBG nodes when checking the uses of a virtual register. It combined a sequence like %vreg1 = madd %vreg2, %vreg3,... DBG_VALUE (%vreg1 ...) %vreg4 = add %vreg1,... to %vreg4 = madd %vreg2, %vreg3 leaving behind a dangling DBG_VALUE with a definition. This triggered an assertion in the MachineTraceMetrics.cpp module. llvm-svn: 215431
* IR: Print a newline when dumping TypesJustin Bogner2014-08-123-4/+4
| | | | | | | | | | | | Type::dump() doesn't print a newline, which makes for a poor experience in a debugger. This looks like it was an ommission considering Value::dump() two lines above, so I've changed Type to add a newline as well. Of the two in-tree callers, one added a newline anyway, and I've updated the other one to use Type::print instead. llvm-svn: 215421
* [OCaml] Expose Llvm.get_operand_use.Peter Zotov2014-08-123-0/+11
| | | | | | Patch by Gabriel Radanne <drupyog@zoho.com> llvm-svn: 215420
* [LLVM-C] Expose User::getOperandUse as LLVMGetOperandUse.Peter Zotov2014-08-122-0/+12
| | | | | | Patch by Gabriel Radanne <drupyog@zoho.com> llvm-svn: 215419
* DebugLocEntry: Restore the comparison predicate from before theAdrian Prantl2014-08-122-1/+5
| | | | | | | | | refactoring in 215384. This way it can unique multiple entries describing the same piece even if they don't have the exact same location. (The same piece may get merged in and be added from OpenRanges). There ought to be a more elegant solution for this, though. llvm-svn: 215418
* msan: Handle musttail callsReid Kleckner2014-08-122-0/+23
| | | | | | | | | | | | | | | | First, avoid calling setTailCall(false) on musttail calls. The funciton prototypes should be "congruent", so the shadow layout should be exactly the same. Second, avoid inserting instrumentation after a musttail call to propagate the return value shadow. We don't need to propagate the result of a tail call, it should already be in the right place. Reviewed By: eugenis Differential Revision: http://reviews.llvm.org/D4331 llvm-svn: 215415
* Move helper for getting a terminating musttail call to BasicBlockReid Kleckner2014-08-123-30/+45
| | | | | | | | | | | No functional change. To be used in future commits that need to look for such instructions. Reviewed By: rafael Differential Revision: http://reviews.llvm.org/D4504 llvm-svn: 215413
* Revert "Partially revert r214761 that asserted that all concrete debug info ↵David Blaikie2014-08-121-3/+1
| | | | | | | | | | | variables had DIEs, due to a failure on Darwin." I believe this was addressed by r215157 and r215227, so let's have another go at the bots, etc. This reverts commit r214880. llvm-svn: 215412
* [MachineSink] Improve the compile time by preserving the dominance informationQuentin Colombet2014-08-111-39/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | as long as possible. ** Context ** Each time the dominance information is modified, the dominator tree analysis switches in a slow query mode. After a few queries without any modification on the dominator tree, it performs an expensive update of its internal structure to provide fast queries again. ** Problem ** Prior to this patch, the MachineSink pass was splitting the critical edges on demand while relying heavy on the dominator tree information. In some cases, this leads to pathological behavior where: - We end up in the slow query mode right after splitting an edge. - We update the dominance information. - We break the dominance information again, thus ending up in the slow query mode and so on. ** Proposed Solution ** To mitigate this effect, this patch postpones all the splitting of the edges at the end of each iteration of the main loop. The benefits are: - The dominance information is valid for the life time of an iteration. - This simplifies the code as we do not have to special treat instructions that are sunk on critical edges. Indeed, the related block will be available through the next iteration. The downside is that when edges splitting is required, this incurs an additional iteration of the main loop compared to the previous scheme. ** Performance ** Thanks to this patch, the motivating example compiles in 6+ minutes instead of 10+ minutes. No test case added as the motivating example as nothing special but being huge! I have measured only noise for both the compile time and the runtime on the llvm test-suite + SPECs with Os and O3. Note: The current implementation of MachineBasicBlock::SplitCriticalEdge also uses the dominance information and therefore, hits this problem. A subsequent patch will address that. <rdar://problem/17894619> llvm-svn: 215410
* [x86] Fold extract_vector_elt of a load into the Load's address computation.Michael J. Spencer2014-08-112-91/+144
| | | | llvm-svn: 215409
* Add a couple of convenience accessors to DebugLocEntry::Value to furtherAdrian Prantl2014-08-112-13/+12
| | | | | | simplify common usage patterns. llvm-svn: 215407
* R600/SIInstrInfo.cpp: Suppress an warning. [-Wunused-variable]NAKAMURA Takumi2014-08-111-0/+1
| | | | llvm-svn: 215406
* [ARM] Mark VMOVDRR with the RegSequence property and implement the relatedQuentin Colombet2014-08-113-0/+46
| | | | | | | | | | | | | target hook. This patch teaches the compiler that: dX = VMOVDRR rY, rZ is the same as: dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1 <rdar://problem/12702965> llvm-svn: 215404
* Make these DebugLocEntry::Value comparison operators friend functionsAdrian Prantl2014-08-111-24/+34
| | | | | | as suggested by dblaikie in a comment on r215384. llvm-svn: 215403
* Add missing closing namespace comment.Jim Grosbach2014-08-111-1/+1
| | | | llvm-svn: 215402
* AArch64: Tidy up a few comments.Jim Grosbach2014-08-111-2/+2
| | | | | | Have the comments match the actual parameter names. Found via clang-tidy. llvm-svn: 215401
* InstCombine: Combine (add (and %a, %b) (or %a, %b)) to (add %a, %b)David Majnemer2014-08-112-1/+63
| | | | | | | | | | | | | | What follows bellow is a correctness proof of the transform using CVC3. $ < t.cvc A, B : BITVECTOR(32); QUERY BVPLUS(32, A & B, A | B) = BVPLUS(32, A, B); $ cvc3 < t.cvc Valid. llvm-svn: 215400
* R600/SI: Add a ComplexPattern for selecting MUBUF _OFFSET variantTom Stellard2014-08-1111-177/+326
| | | | | | | This saves us from having to copy a 64-bit 0 value into VGPRs for BUFFER_* instruction which only have a 12-bit immediate offset. llvm-svn: 215399
* R600/SI: Add an _OFFEN variant MUBUF_STORE_* and use it for scratch writesTom Stellard2014-08-112-23/+34
| | | | llvm-svn: 215398
* R600/SI: Add check for low 32 bits of encoding to mubuf testsTom Stellard2014-08-111-7/+7
| | | | | | | | There are no variable values like registers encoded in the low 32 bits of MUBUF instructions, so it is relatively easy to check these bits, and it will help prevent us from introducing encoding bugs. llvm-svn: 215397
* R600/SI: Clear lds bit on MUBUF instructions used for private storesTom Stellard2014-08-112-10/+10
| | | | | | | | This bit was left uninitialized, which was causing some random failures of piglit tests. NOTE: This is a candidate for the 3.5 branch. llvm-svn: 215396
* R600/SI: Fix broken testTom Stellard2014-08-111-3/+5
| | | | llvm-svn: 215395
* Add isRegSequence property.Quentin Colombet2014-08-118-1/+112
| | | | | | | | | | | This patch adds a new property: isRegSequence and the related target hooks: TargetIntrInfo::getRegSequenceInputs and TargetInstrInfo::getRegSequenceLikeInputs to specify that a target specific instruction is a (kind of) REG_SEQUENCE. <rdar://problem/12702965> llvm-svn: 215394
* [AArch64] Fix registerAllocator assigns same register for base and wback inQuentin Colombet2014-08-112-7/+18
| | | | | | | | pre/post-index load and store. Patch by Steven Wu <stevenwu@apple.com> llvm-svn: 215390
* Debug info: Remove an obsolete constructor from DebugLocEntry.Adrian Prantl2014-08-111-2/+2
| | | | llvm-svn: 215387
* Debug info: Modify DebugLocEntry::addValue to take multiple values so itAdrian Prantl2014-08-112-8/+9
| | | | | | only has to sort/unique values once per batch. llvm-svn: 215386
* Debug info: Further simplify the implementation of buildLocationList byAdrian Prantl2014-08-111-6/+6
| | | | | | getting rid of the redundant DIVariable in the OpenRanges pair. llvm-svn: 215385
* Debug Info: Move the sorting and uniqueing of pieces from emitLocPieces()Adrian Prantl2014-08-112-18/+22
| | | | | | | into buildLocationList(). By keeping the list of Values sorted, DebugLocEntry::Merge can also merge multi-piece entries. llvm-svn: 215384
* Debug info: Refactor DebugLocEntry's Merge function to makeAdrian Prantl2014-08-112-14/+37
| | | | | | | | | | | | buildLocationLists easier to read. The previous implementation conflated the merging of individual pieces and the merging of entire DebugLocEntries. By splitting this functionality into two separate functions the intention of the code should be clearer. llvm-svn: 215383
* ARM: try harder to detect non-IT eligible instructionsSaleem Abdulrasool2014-08-112-15/+49
| | | | | | | | | | | | | | | | | | | For many Thumb-1 register register instructions, setting the CPSR is not permitted inside an IT block. We would not correctly flag those instructions. The previous change to identify this scenario was insufficient as it did not actually catch all the instances. The current list is formed by manual inspection of the ARMv6M ARM. The change to the Thumb2 IT block test is due to the fact that the new more stringent checking of the MIs results in the If Conversion pass being prevented from executing (since not all the instructions in the BB are predicable). This results in code gen changes. Thanks to Tim Northover for pointing out that the previous patch was insufficient and hinting that the use of the v6M ARM would be much easier to use than the v7 or v8! llvm-svn: 215382
* Fix using -plugin-opt=apiflie when also using -plugin-opt=emit-llvm.Rafael Espindola2014-08-112-18/+33
| | | | llvm-svn: 215378
* Correct a missing RUN line in the ARM codegen test for fneg ops. We should ↵Sanjay Patel2014-08-111-1/+4
| | | | | | | | | | also explicitly specify +/-neonfp. The bug was introduced at r99570 when use of "-arm-use-neon-fp" was removed. Differential Revision: http://reviews.llvm.org/D4846 llvm-svn: 215377
* Add missing test for r215031Reid Kleckner2014-08-111-0/+13
| | | | llvm-svn: 215374
* MC: Diagnose an unexpected token in COFF .section instead of assertingReid Kleckner2014-08-112-0/+7
| | | | | | | This can easily arise when trying to assemble and ELF style .section directive for a COFF object file. llvm-svn: 215373
* Fix typos:Sylvestre Ledru2014-08-117-7/+7
| | | | | | | * libaries => libraries * avaiable => available llvm-svn: 215366
* Fix use of uninitialized variable.Rafael Espindola2014-08-113-2/+26
| | | | | | | Fixes linking bitcode files that use the new style comdats for constructors with ones that don't. llvm-svn: 215364
* Use an early return. NFC.Rafael Espindola2014-08-111-8/+9
| | | | llvm-svn: 215363
* Revert r215359 - [mips] Implement .ent, .end, .frame, .mask and .fmask ↵Daniel Sanders2014-08-115-369/+22
| | | | | | | | assembler directives It seems to cause an lld test (elf/Mips/hilo16-3.test) to fail. Reverted while we investigate. llvm-svn: 215361
* [mips] Implement .ent, .end, .frame, .mask and .fmask assembler directivesDaniel Sanders2014-08-115-22/+369
| | | | | | | | Patch by Matheus Almeida and Toma Tabacu Differential Revision: http://reviews.llvm.org/D4179 llvm-svn: 215359
* PeepholeOptimizer: make parameter ref to SmallPtrSetImplHans Wennborg2014-08-111-2/+2
| | | | | | | This makes the function type independent of the in-line size of LocalMIs. llvm-svn: 215356
* Make this SmallVector size a power of two as suggested by ChandlerHans Wennborg2014-08-111-1/+1
| | | | llvm-svn: 215355
* AArch64: add support for dynamic-loader relocationsTim Northover2014-08-115-1/+47
| | | | | | | | | LLD needs them, and it's good to be able to print them properly when our object dumpers encounter them. Patch by Daniel Stewart. llvm-svn: 215352
OpenPOWER on IntegriCloud