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* Remove the plumbing of 64-bitness from PrepareTailCall and functionsEric Christopher2016-07-071-13/+13
| | | | | | called by it. llvm-svn: 274711
* Sink call to get the MachineFunction into EmitTailCallStoreFPAndRetAddrEric Christopher2016-07-071-10/+7
| | | | | | and remove the argument. llvm-svn: 274710
* Remove unnecessary subtarget parameters in PPCTargetLowering.Eric Christopher2016-07-072-31/+26
| | | | llvm-svn: 274709
* [PM] Port TailCallElimSean Silva2016-07-065-2/+88
| | | | llvm-svn: 274708
* Fix missing member initializersMatt Arsenault2016-07-061-1/+1
| | | | | | | This fixes the -Werror build with some combination of warning flags. llvm-svn: 274707
* [PM] Port CorrelatedValuePropagationSean Silva2016-07-065-7/+54
| | | | llvm-svn: 274705
* fix documentation comment. NFC.Junmo Park2016-07-061-2/+1
| | | | llvm-svn: 274704
* Minor code cleanup. NFC.Junmo Park2016-07-061-1/+1
| | | | llvm-svn: 274702
* ThinLTO: Add test cases for promote+internalize.Peter Collingbourne2016-07-062-1/+43
| | | | | | | | | This tests the effect of both promotion and internalization on a module, and helps show that D21883 is NFC wrt promotion+internalization. Differential Revision: http://reviews.llvm.org/D21915 llvm-svn: 274699
* [InstCombine] enhance (select X, C1, C2 --> ext X) to handle vectorsSanjay Patel2016-07-062-27/+46
| | | | | | | | | By replacing dyn_cast of ConstantInt with m_Zero/m_One/m_AllOnes, we allow these transforms for splat vectors. Differential Revision: http://reviews.llvm.org/D21899 llvm-svn: 274696
* Minor formatting change, NFCVedant Kumar2016-07-061-7/+3
| | | | | | | The rest of llvm-cov does not use LLVM_ATTRIBUTE_UNUSED. Leave unused params unnamed to be consistent. llvm-svn: 274694
* Add testing coverage for r274582.Manman Ren2016-07-061-0/+21
| | | | llvm-svn: 274693
* [X86] Transform setcc + movzbl into xorl + setccMichael Kuperstein2016-07-0632-288/+523
| | | | | | | | | | | xorl + setcc is generally the preferred sequence due to the partial register stall setcc + movzbl suffers from. As a bonus, it also encodes one byte smaller. This fixes PR28146. Differential Revision: http://reviews.llvm.org/D21774 llvm-svn: 274692
* [llvm-cov] Add support for creating html reportsVedant Kumar2016-07-069-2/+615
| | | | | | | | Based on a patch by Harlan Haskins! Differential Revision: http://reviews.llvm.org/D18278 llvm-svn: 274688
* AArch64: Change modeling of zero cycle zeroing.Matthias Braun2016-07-064-26/+76
| | | | | | | | | | | | | | | | | On CPUs with the zero cycle zeroing feature enabled "movi v.2d" should be used to zero a vector register. This was previously done at instruction selection time, however the register coalescer sometimes widened multiple vregs to the Q width because of that leading to extra spills. This patch leaves the decision on how to zero a register to the AsmPrinter phase where it doesn't affect register allocation anymore. This patch also sets isAsCheapAsAMove=1 on FMOVS0, FMOVD0. This fixes http://llvm.org/PR27454, rdar://25866262 Differential Revision: http://reviews.llvm.org/D21826 llvm-svn: 274686
* AArch64: Replace a RegScavenger instance with LivePhysRegsMatthias Braun2016-07-063-16/+35
| | | | | | | | | | | | | | findScratchNonCalleeSaveRegister() just needs a simple liveness analysis, use LivePhysRegs for that as it is simpler and does not depend on the kill flags. This commit adds a convenience function available() to LivePhysRegs: This function returns true if the given register is not reserved and neither the register nor any of its aliases are alive. Differential Revision: http://reviews.llvm.org/D21865 llvm-svn: 274685
* [MemorySSA] Reinstate the legacy printer and verifier.Chad Rosier2016-07-0619-15/+58
| | | | | | Differential Revision: http://reviews.llvm.org/D22058 llvm-svn: 274679
* Add initial support for R_386_GOT32X.Rafael Espindola2016-07-068-11/+53
| | | | | | This adds it only for movl mov@GOT(%reg), %reg. llvm-svn: 274678
* [CodeView] Emit an appropriate symbol kind for globalsDavid Majnemer2016-07-066-9/+32
| | | | | | | We emitted debug info for globals/functions as if they all had external linkage. Instead, emit local symbol records when appropriate. llvm-svn: 274676
* [CodeView] Unions are always sealedDavid Majnemer2016-07-062-2/+3
| | | | | | | It is impossible to inherit from a union. We are missing a way to represent this in IR for classes/structs... llvm-svn: 274675
* [NVPTX] Add sm_60, sm_61, sm_62 targets to LLVM.Justin Lebar2016-07-064-1/+28
| | | | | | | | | | Reviewers: tra Subscribers: jholewinski, llvm-commits Differential Revision: http://reviews.llvm.org/D22068 llvm-svn: 274674
* [LIR] Fix mis-compilation with unwinding.Haicheng Wu2016-07-062-0/+41
| | | | | | | | To fix PR27859, bail out if there is an instruction may throw. Differential Revision: http://reviews.llvm.org/D20638 llvm-svn: 274673
* [InstCombine] use more specific pattern matchers; NFCISanjay Patel2016-07-061-12/+10
| | | | | | | | Follow-up from r274465: we don't need to capture the value in these cases, so just match the constant that we're looking for. m_One/m_Zero work with vector splats as well as scalars. llvm-svn: 274670
* Add 'thinlto_src_module' metadata to imported functionPiotr Padlewski2016-07-062-10/+17
| | | | | | | | | | | | | | Added metadata to be able to make statistics on how many functions that have been imported have been removed. Also module name might be helpfull when debugging. Reviewers: tejohnson, eraman Subscribers: mehdi_amini, llvm-commits Differential Revision: http://reviews.llvm.org/D21943 llvm-svn: 274668
* [esan|wset] Fix incorrect memory size assertDerek Bruening2016-07-063-2/+75
| | | | | | | | | | | | | | Summary: Fixes an incorrect assert that fails on 128-bit-sized loads or stores. Augments the wset tests to include this case. Reviewers: aizatsky Subscribers: vitalybuka, zhaoqin, kcc, eugenis, llvm-commits Differential Revision: http://reviews.llvm.org/D22062 llvm-svn: 274666
* NVPTX: Replace uses of cuda.syncthreads with nvvm.barrier0Justin Bogner2016-07-0611-28/+23
| | | | | | | Everywhere where cuda.syncthreads or __syncthreads is used, use the properly namespaced nvvm.barrier0 instead. llvm-svn: 274664
* NVPTX: Make the llvm.nvvm.shfl intrinsics and builtin names consistentJustin Bogner2016-07-062-24/+24
| | | | | | | The intrinsics here use nvvm, but the builtins and tablegen variable names were using ptx. Stick to the modern names here. llvm-svn: 274662
* Retry: "Emit CodeView type records for nested classes."Adrian McCarthy2016-07-063-7/+127
| | | | | | | | | | Now with a corrected test to account for a recently supported properties bit in the debug info of a struct. Original review: http://reviews.llvm.org/D21939 This reverts commit 970c3fd497a28d25dd69526eb52594a696c37968. llvm-svn: 274661
* [DSE] Avoid iterator invalidation bugs.Chad Rosier2016-07-062-123/+34
| | | | | | | | | | The dse_with_dbg_value.ll test committed with r273141 is removed because this we no longer performs any type of back tracking, which is what was causing the codegen differences with and without debug information. Differential Revision: http://reviews.llvm.org/D21613 llvm-svn: 274660
* [Conduct] Refine what "rare cases" means wrt violations outside our spaces.Paul Robinson2016-07-061-1/+2
| | | | | | | | | | Text suggested by Daniel Berlin. While it is likely to be exactly what the advisory committee would do anyway, codifying it does no harm and helps reassure people that rare does not mean arbitrary. Differential Revision: http://reviews.llvm.org/D21981 llvm-svn: 274659
* [x86] fix cost of SINT_TO_FP for i32 --> float (PR21356, PR28434)Sanjay Patel2016-07-062-7/+7
| | | | | | | | | | | | | This is "cvtdq2ps" which does not appear to be particularly slow on any CPU according to Agner's tables. Choosing "5" as a cost here as suggested in: https://llvm.org/bugs/show_bug.cgi?id=21356 ...but it seems very conservative given that the instruction is fully pipelined, and I think these costs are supposed to model throughput. Note that related costs are also most likely too high, but this fixes PR21356 and partly fixes PR28434. llvm-svn: 274658
* Work around PR28400 a bit harder.Sean Silva2016-07-062-2/+24
| | | | | | | | | | We were still crashing in the "no change" case because LVI was not getting invalidated. See the thread "Should analyses be able to hold AssertingVH to IR? (related to PR28400)" for more discussion. llvm-svn: 274656
* TailDuplicator: Remove live-in updating logicMatthias Braun2016-07-062-19/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This logic was introduced in r157663 and does not make any sense to me. The motivating example in rdar://11538365 looks like this: This is the tail: BB#16: derived from LLVM BB %if.end68 Live Ins: %R0 %R4 %R5 Predecessors according to CFG: BB#15 BB#5 tBLXi pred:14, pred:%noreg, <ga:@CFRelease>, %R0<kill>, <regmask>, %LR<imp-def,dead>, %SP<imp-use>, %SP<imp-def> t2B <BB#20>, pred:14, pred:%noreg Successors according to CFG: BB#20 This is the predBB: BB#5: Live Ins: %R5 Predecessors according to CFG: BB#4 %R4<def> = t2MOVi 0, pred:14, pred:%noreg, opt:%noreg t2B <BB#16>, pred:14, pred:%noreg Successors according to CFG: BB#16 However this is invalid machine code to begin with, if %R0 is live-in to BB#16 then it must be live-in to BB#5 as well if BB#5 does not define it. We should not need logic to retroactively fix broken machine code and in fact the example from r157663 passes cleanly with the code removed and I do not see any (newly) failing tests with the machine verifier enabled. Differential Revision: http://reviews.llvm.org/D22031 llvm-svn: 274655
* [X86] Sort cast cost tables. NFC.Michael Kuperstein2016-07-061-124/+123
| | | | | | | Cast cost tables are now sorted, for each cast type, lexicographically on [source base type, source vector width, dest base type, base vector width]. llvm-svn: 274653
* [SystemZ] Remove AND mask of bottom 6 bits when result is used for shift/rotateElliot Colp2016-07-065-3/+249
| | | | | | | | | | On SystemZ, shift and rotate instructions only use the bottom 6 bits of the shift/rotate amount. Therefore, if the amount is ANDed with an immediate mask that has all of the bottom 6 bits set, we can remove the AND operation entirely. Differential Revision: http://reviews.llvm.org/D21854 llvm-svn: 274650
* NFC changed names in FunctionImportPiotr Padlewski2016-07-061-14/+14
| | | | llvm-svn: 274649
* [X86][SSE] Fixed typo in insertps lowering.Simon Pilgrim2016-07-061-1/+1
| | | | | | | | We were checking for 2 insertions (which is caught earlier in the pattern matching loop) instead of the case where we have no insertions. Turns out this code never fires as we always try to lower to insertps after trying to lower to blendps, which would catch these cases - I'm about to make some changes to support combining to insertps which could cause this to fire so I don't want to remove it. llvm-svn: 274648
* [pdb] Round trip the PDB stream between YAML and binary PDB.Zachary Turner2016-07-0624-28/+377
| | | | | | This gets writing of the PDB stream working. llvm-svn: 274647
* Ensure all uses of permute instructions feed vector storesKit Barton2016-07-062-0/+75
| | | | | | | | | | | | | | | There is a problem in VSXSwapRemoval where it is incorrectly removing permute instructions. In this case, the permute is feeding both a vector store and also a non-store instruction. In this case, the permute cannot be removed. The fix is to simply look at all the uses of the vector register defined by the permute and ensure that all the uses are vector store instructions. This problem was reported in PR 27735 (https://llvm.org/bugs/show_bug.cgi?id=27735). Test case based on the original problem reported. Phabricator Review: http://reviews.llvm.org/D21802 llvm-svn: 274645
* [DAGCombiner] Fix visitSTORE to continue processing current SDNode, if ↵Tim Shen2016-07-062-6/+82
| | | | | | | | | | | | | | | | | findBetterNeighborChains doesn't actually CombineTo it. Summary: findBetterNeighborChains may or may not find a better chain for each node it finds, which include the node ("St") that visitSTORE is currently processing. If no better chain is found for St, visitSTORE should continue instead of return SDValue(St, 0), as if it's CombinedTo'ed. This fixes bug 28130. There might be other ways to make the test pass (see D21409). I think both of the patches are fixing actual bugs revealed by the same testcase. Reviewers: echristo, wschmidt, hfinkel, kbarton, amehsan, arsenm, nemanjai, bogner Subscribers: mehdi_amini, nemanjai, llvm-commits Differential Revision: http://reviews.llvm.org/D21692 llvm-svn: 274644
* [TTI] The cost model should not assume vector casts get completely scalarizedMichael Kuperstein2016-07-067-221/+241
| | | | | | | | | | | | | | | | The cost model should not assume vector casts get completely scalarized, since on targets that have vector support, the common case is a partial split up to the legal vector size. So, when a vector cast gets split, the resulting casts end up legal and cheap. Instead of pessimistically assuming scalarization, base TTI can use the costs the concrete TTI provides for the split vector, plus a fudge factor to account for the cost of the split itself. This fudge factor is currently 1 by default, except on AMDGPU where inserts and extracts are considered free. Differential Revision: http://reviews.llvm.org/D21251 llvm-svn: 274642
* Add a default parameter for getRegisteredOptions.Zachary Turner2016-07-061-1/+1
| | | | llvm-svn: 274640
* Disable hash verification of enums.Zachary Turner2016-07-062-1/+3
| | | | llvm-svn: 274639
* Prune RelocVisitor.h include to avoid including COFF.h from MCJIT.hReid Kleckner2016-07-065-1/+7
| | | | | | | This helps to mitigate the conflict between COFF.h and winnt.h, which is PR28399. llvm-svn: 274637
* fix typo; NFCSanjay Patel2016-07-061-1/+1
| | | | llvm-svn: 274636
* Revert "Emit CodeView type records for nested classes."Adrian McCarthy2016-07-063-127/+7
| | | | | | This reverts commit 256b29322c827a2d94da56468c936596f5509032. llvm-svn: 274632
* [X86][SSE] Added test cases for missed opportunities to combine pshufb to ↵Simon Pilgrim2016-07-063-0/+82
| | | | | | pslldq/psrldq llvm-svn: 274631
* Emit CodeView type records for nested classes.Adrian McCarthy2016-07-063-7/+127
| | | | | | Differential Revision: http://reviews.llvm.org/D21939 llvm-svn: 274629
* [LV] Don't widen trivial induction variablesMatthew Simpson2016-07-065-24/+256
| | | | | | | | | | | | | | | | | | | | We currently always vectorize induction variables. However, if an induction variable is only used for counting loop iterations or computing addresses with getelementptr instructions, we don't need to do this. Vectorizing these trivial induction variables can create vector code that is difficult to simplify later on. This is especially true when the unroll factor is greater than one, and we create vector arithmetic when computing step vectors. With this patch, we check if an induction variable is only used for counting iterations or computing addresses, and if so, scalarize the arithmetic when computing step vectors instead. This allows for greater simplification. This patch addresses the suboptimal pointer arithmetic sequence seen in PR27881. Reference: https://llvm.org/bugs/show_bug.cgi?id=27881 Differential Revision: http://reviews.llvm.org/D21620 llvm-svn: 274627
* Re-commit of 274613.Elena Demikhovsky2016-07-0613-329/+379
| | | | | | | The prev commit failed on compilation. A minor change in one pattern in lib/Target/X86/X86InstrAVX512.td fixes the failure. llvm-svn: 274626
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